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This commit is contained in:
Markus Koch 2016-02-21 16:50:27 +01:00
parent 1aef5adfad
commit 4a05a6ed85
12 changed files with 3646 additions and 3016 deletions
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14
FSMC.sch
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@ -491,10 +491,6 @@ Wire Wire Line
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Wire Wire Line Wire Wire Line
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220
audio.sch
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@ -44,7 +44,7 @@ EELAYER 25 0
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@ -55,34 +55,34 @@ Comment3 ""
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@ -57,58 +57,58 @@ $EndDescr
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Text Label 3600 1700 0 60 ~ 0 Text Label 2550 1800 0 60 ~ 0
FTMS FTMS
Text Label 3600 1600 0 60 ~ 0 Text Label 2550 1700 0 60 ~ 0
FTDI FTDI
Text Label 3600 1500 0 60 ~ 0 Text Label 2550 1600 0 60 ~ 0
FTDO FTDO
NoConn ~ 4900 1400 NoConn ~ 3850 1500
NoConn ~ 4900 1500 NoConn ~ 3850 1600
NoConn ~ 4000 1400 NoConn ~ 2950 1500
Text Label 4750 2600 0 60 ~ 0 Text Label 4500 2950 0 60 ~ 0
JTCK JTCK
Text Label 4750 2700 0 60 ~ 0 Text Label 4500 3050 0 60 ~ 0
JTMS JTMS
Text Label 4750 2800 0 60 ~ 0 Text Label 4500 3150 0 60 ~ 0
JTDI JTDI
Text Label 4750 2900 0 60 ~ 0 Text Label 4500 3250 0 60 ~ 0
JTDO JTDO
Text Label 4750 3000 0 60 ~ 0 Text Label 4500 3350 0 60 ~ 0
JRST_N JRST_N
Text Label 1850 2800 0 60 ~ 0 Text Label 1850 2800 0 60 ~ 0
OSCIN OSCIN
Text Label 1850 3100 0 60 ~ 0 Text Label 1850 3000 0 60 ~ 0
OSCOUT OSCOUT
Wire Wire Line Wire Wire Line
4000 1800 3550 1800 2950 1900 2500 1900
Wire Wire Line Wire Wire Line
3550 1700 4000 1700 2500 1800 2950 1800
Wire Wire Line Wire Wire Line
3550 1600 4000 1600 2500 1700 2950 1700
Wire Wire Line Wire Wire Line
4000 1500 3550 1500 2950 1600 2500 1600
Wire Wire Line Wire Wire Line
3550 800 3550 1300 2500 900 2500 1400
Wire Wire Line Wire Wire Line
3750 900 3750 850 2700 1000 2700 950
Wire Wire Line Wire Wire Line
3750 850 3550 850 2700 950 2500 950
Connection ~ 3550 850 Connection ~ 2500 950
Wire Wire Line Wire Wire Line
3750 1200 3750 1250 2700 1300 2700 1350
Wire Wire Line Wire Wire Line
5150 1400 5150 1600 4100 1500 4100 1700
Wire Wire Line Wire Wire Line
5150 1600 4900 1600 4100 1700 3850 1700
Wire Wire Line Wire Wire Line
5150 1700 5150 1900 4100 1800 4100 2000
Wire Wire Line Wire Wire Line
5150 1800 4900 1800 4100 1900 3850 1900
Wire Wire Line Wire Wire Line
4900 1700 5150 1700 3850 1800 4100 1800
Connection ~ 5150 1800 Connection ~ 4100 1900
Wire Wire Line Wire Wire Line
1750 3000 2250 3000 1750 3000 2250 3000
Wire Wire Line Wire Wire Line
@ -271,43 +271,157 @@ Wire Wire Line
1450 2900 1450 3550 1450 2900 1450 3550
Connection ~ 1550 2900 Connection ~ 1550 2900
Wire Wire Line Wire Wire Line
4650 2600 5050 2600 4400 2950 4800 2950
Wire Wire Line Wire Wire Line
5050 2700 4650 2700 4800 3050 4400 3050
Wire Wire Line Wire Wire Line
4650 2800 5050 2800 4400 3150 4800 3150
Wire Wire Line Wire Wire Line
5050 2900 4650 2900 4800 3250 4400 3250
Wire Wire Line Wire Wire Line
4650 3000 5050 3000 4400 3350 4800 3350
Wire Wire Line Wire Wire Line
5000 3150 5000 3100 4750 3500 4750 3450
Wire Wire Line Wire Wire Line
5000 3100 5050 3100 4750 3450 4800 3450
Wire Wire Line
1850 3100 1800 3100
Wire Wire Line
1800 3100 1800 3000
$Comp $Comp
L VFPGA33 #PWR302 L VFPGA33 #PWR303
U 1 1 56CA6859 U 1 1 56CA6859
P 3550 800 P 2500 900
F 0 "#PWR302" H 3550 650 50 0001 C CNN F 0 "#PWR303" H 2500 750 50 0001 C CNN
F 1 "VFPGA33" H 3568 974 50 0000 C CNN F 1 "VFPGA33" H 2518 1074 50 0000 C CNN
F 2 "" H 3550 800 50 0000 C CNN F 2 "" H 2500 900 50 0000 C CNN
F 3 "" H 3550 800 50 0000 C CNN F 3 "" H 2500 900 50 0000 C CNN
1 3550 800 1 2500 900
1 0 0 -1 1 0 0 -1
$EndComp $EndComp
$Comp $Comp
L VFPGA33 #PWR305 L VFPGA33 #PWR306
U 1 1 56CA6C73 U 1 1 56CA6C73
P 5150 1400 P 4100 1500
F 0 "#PWR305" H 5150 1250 50 0001 C CNN F 0 "#PWR306" H 4100 1350 50 0001 C CNN
F 1 "VFPGA33" H 5168 1574 50 0000 C CNN F 1 "VFPGA33" H 4118 1674 50 0000 C CNN
F 2 "" H 5150 1400 50 0000 C CNN F 2 "" H 4100 1500 50 0000 C CNN
F 3 "" H 5150 1400 50 0000 C CNN F 3 "" H 4100 1500 50 0000 C CNN
1 5150 1400 1 4100 1500
1 0 0 -1
$EndComp
$Comp
L CONN_02X03 P301
U 1 1 56CD008F
P 2650 4750
F 0 "P301" H 2650 5066 50 0000 C CNN
F 1 "CONN_02X03" H 2650 4974 50 0000 C CNN
F 2 "" H 2650 3550 50 0000 C CNN
F 3 "" H 2650 3550 50 0000 C CNN
1 2650 4750
1 0 0 -1
$EndComp
Wire Wire Line
2900 4650 2950 4650
Wire Wire Line
2950 4650 2950 4950
Wire Wire Line
2900 4850 2950 4850
Connection ~ 2950 4850
Wire Wire Line
2900 4750 2950 4750
Connection ~ 2950 4750
$Comp
L GND #PWR305
U 1 1 56CD0193
P 2950 4950
F 0 "#PWR305" H 2950 4700 50 0001 C CNN
F 1 "GND" H 2958 4776 50 0000 C CNN
F 2 "" H 2950 4950 50 0000 C CNN
F 3 "" H 2950 4950 50 0000 C CNN
1 2950 4950
1 0 0 -1
$EndComp
Wire Wire Line
2250 3150 1850 3150
Text Label 1850 3150 0 60 ~ 0
NRST
Wire Wire Line
2250 3250 1850 3250
Text Label 1850 3250 0 60 ~ 0
BOOT0
Wire Wire Line
2450 3450 1850 3450
Text Label 1850 3450 0 60 ~ 0
BOOT1
Wire Wire Line
2400 4650 1550 4650
Wire Wire Line
2400 4750 1550 4750
Wire Wire Line
2400 4850 1550 4850
Text Label 1550 4650 0 60 ~ 0
NRST
Text Label 1550 4750 0 60 ~ 0
BOOT0
Text Label 1550 4850 0 60 ~ 0
BOOT1
$Comp
L R R301
U 1 1 56CD0D17
P 2050 4400
F 0 "R301" H 1950 4250 50 0000 L CNN
F 1 "10k" V 2050 4350 50 0000 L CNN
F 2 "" V 1980 4400 50 0000 C CNN
F 3 "" H 2050 4400 50 0000 C CNN
1 2050 4400
1 0 0 -1
$EndComp
Wire Wire Line
2350 4550 2350 4650
Connection ~ 2350 4650
Wire Wire Line
2200 4550 2200 4750
Connection ~ 2200 4750
Wire Wire Line
2050 4550 2050 4850
Connection ~ 2050 4850
$Comp
L R R302
U 1 1 56CD0F59
P 2200 4400
F 0 "R302" H 2100 4250 50 0000 L CNN
F 1 "10k" V 2200 4350 50 0000 L CNN
F 2 "" V 2130 4400 50 0000 C CNN
F 3 "" H 2200 4400 50 0000 C CNN
1 2200 4400
1 0 0 -1
$EndComp
$Comp
L R R303
U 1 1 56CD0F97
P 2350 4400
F 0 "R303" H 2250 4250 50 0000 L CNN
F 1 "10k" V 2350 4350 50 0000 L CNN
F 2 "" V 2280 4400 50 0000 C CNN
F 3 "" H 2350 4400 50 0000 C CNN
1 2350 4400
1 0 0 -1
$EndComp
Wire Wire Line
2350 4250 2350 4200
Wire Wire Line
2350 4200 2050 4200
Wire Wire Line
2050 4200 2050 4250
Wire Wire Line
2200 4100 2200 4250
Connection ~ 2200 4200
$Comp
L VSTM33 #PWR302
U 1 1 56CD10CF
P 2200 4100
F 0 "#PWR302" H 2200 3950 50 0001 C CNN
F 1 "VSTM33" H 2218 4274 50 0000 C CNN
F 2 "" H 2200 4100 50 0000 C CNN
F 3 "" H 2200 4100 50 0000 C CNN
1 2200 4100
1 0 0 -1 1 0 0 -1
$EndComp $EndComp
$EndSCHEMATC $EndSCHEMATC

3
display.sch
View File

@ -299,8 +299,6 @@ Text Label 2950 4950 2 60 ~ 0
DB3 DB3
Text Label 2950 4850 2 60 ~ 0 Text Label 2950 4850 2 60 ~ 0
RS RS
Wire Wire Line
1350 4850 1050 4850
Wire Wire Line Wire Wire Line
1350 4950 1050 4950 1350 4950 1050 4950
Wire Wire Line Wire Wire Line
@ -476,4 +474,5 @@ Text HLabel 4600 3100 0 60 Output ~ 0
T_BUSY T_BUSY
Text HLabel 4600 3200 0 60 Output ~ 0 Text HLabel 4600 3200 0 60 Output ~ 0
T_IRQ T_IRQ
NoConn ~ 1350 4850
$EndSCHEMATC $EndSCHEMATC

30
fpgna-cache.lib
View File

@ -92,6 +92,36 @@ X P6 6 -200 -250 150 R 50 50 1 1 P
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #
# CONN_02X03
#
DEF CONN_02X03 P 0 1 Y N 1 F N
F0 "P" 0 200 50 H V C CNN
F1 "CONN_02X03" 0 -200 50 H V C CNN
F2 "" 0 -1200 50 H V C CNN
F3 "" 0 -1200 50 H V C CNN
$FPLIST
Pin_Header_Straight_2X03
Pin_Header_Angled_2X03
Socket_Strip_Straight_2X03
Socket_Strip_Angled_2X03
$ENDFPLIST
DRAW
S -100 -95 -50 -105 0 1 0 N
S -100 5 -50 -5 0 1 0 N
S -100 105 -50 95 0 1 0 N
S -100 150 100 -150 0 1 0 N
S 50 -95 100 -105 0 1 0 N
S 50 5 100 -5 0 1 0 N
S 50 105 100 95 0 1 0 N
X P1 1 -250 100 150 R 50 50 1 1 P
X P2 2 250 100 150 L 50 50 1 1 P
X P3 3 -250 0 150 R 50 50 1 1 P
X P4 4 250 0 150 L 50 50 1 1 P
X P5 5 -250 -100 150 R 50 50 1 1 P
X P6 6 250 -100 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# CP # CP
# #
DEF CP C 0 10 N Y 1 F N DEF CP C 0 10 N Y 1 F N

3421
fpgna.kicad_pcb
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File diff suppressed because it is too large Load Diff

1606
fpgna.net
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File diff suppressed because it is too large Load Diff

244
fpgna.sch
View File

@ -55,181 +55,195 @@ Comment3 ""
Comment4 "" Comment4 ""
$EndDescr $EndDescr
$Sheet $Sheet
S 3550 3550 2050 1400 S 1750 2050 1000 1150
U 563244F7 U 563244F7
F0 "powersupply" 60 F0 "powersupply" 60
F1 "power.sch" 60 F1 "power.sch" 60
F2 "CHG_ACTIVE_N" O R 5600 3900 60 F2 "CHG_ACTIVE_N" O R 2750 2300 60
F3 "USB_PRESENT_N" O R 5600 3800 60 F3 "USB_PRESENT_N" O R 2750 2600 60
F4 "CHARGE_ENABLE" I R 5600 4000 60 F4 "CHARGE_ENABLE" I R 2750 2400 60
F5 "SYS_VOLTAGE" O R 5600 4200 60 F5 "SYS_VOLTAGE" O R 2750 2200 60
F6 "CLK_50M" O L 3550 3800 60 F6 "FPGA_ENABLE_N" I R 2750 2500 60
F7 "FPGA_ENABLE_N" I R 5600 4300 60
$EndSheet $EndSheet
$Sheet $Sheet
S 2450 1450 1000 1100 S 1750 3400 1000 1100
U 56337D98 U 56337D98
F0 "debug" 60 F0 "debug" 60
F1 "debug.sch" 60 F1 "debug.sch" 60
F2 "JTDI" O R 3450 1800 60 F2 "JTDI" O R 2750 3750 60
F3 "JTMS" O R 3450 1600 60 F3 "JTMS" O R 2750 3550 60
F4 "JTDO" I R 3450 2250 60 F4 "JTDO" I R 2750 4200 60
F5 "JTCK" O R 3450 1700 60 F5 "JTCK" O R 2750 3650 60
F6 "JRST_N" O R 3450 2350 60 F6 "JRST_N" O R 2750 4300 60
F7 "BOOT1" O R 3450 2450 60 F7 "BOOT1" O R 2750 4400 60
$EndSheet $EndSheet
$Sheet $Sheet
S 6300 1100 2050 2150 S 5900 3050 2050 2150
U 56C43C85 U 56C43C85
F0 "FSMC" 60 F0 "FSMC" 60
F1 "FSMC.sch" 60 F1 "FSMC.sch" 60
F2 "BOOT1" I L 6300 2450 60 F2 "BOOT1" I L 5900 4400 60
F3 "JTDO" O L 6300 2250 60 F3 "JTDO" O L 5900 4200 60
F4 "JRST_N" I L 6300 2350 60 F4 "JRST_N" I L 5900 4300 60
F5 "BL0_N" O R 8350 2350 60 F5 "BL0_N" O R 7950 4300 60
F6 "BL1_N" O R 8350 2450 60 F6 "BL1_N" O R 7950 4400 60
F7 "A[19..23]" O R 8350 2550 60 F7 "A[19..23]" O R 7950 4500 60
F8 "SDIO_CMD" O L 6300 1250 60 F8 "SDIO_CMD" O L 5900 3200 60
F9 "T_CS" O R 8350 1350 60 F9 "T_CS" O R 7950 3300 60
F10 "T_CLK" O R 8350 1250 60 F10 "T_CLK" O R 7950 3200 60
F11 "T_DOUT" I R 8350 1550 60 F11 "T_DOUT" I R 7950 3500 60
F12 "T_DIN" O R 8350 1450 60 F12 "T_DIN" O R 7950 3400 60
$EndSheet $EndSheet
$Sheet $Sheet
S 8500 1100 1750 800 S 8100 3050 1750 800
U 56C579FC U 56C579FC
F0 "display" 60 F0 "display" 60
F1 "display.sch" 60 F1 "display.sch" 60
F2 "T_CLK" I L 8500 1250 60 F2 "T_CLK" I L 8100 3200 60
F3 "T_CS" I L 8500 1350 60 F3 "T_CS" I L 8100 3300 60
F4 "T_DIN" I L 8500 1450 60 F4 "T_DIN" I L 8100 3400 60
F5 "T_DOUT" O L 8500 1550 60 F5 "T_DOUT" O L 8100 3500 60
F6 "T_BUSY" O R 10250 1350 60 F6 "T_BUSY" O R 9850 3300 60
F7 "T_IRQ" O R 10250 1250 60 F7 "T_IRQ" O R 9850 3200 60
$EndSheet $EndSheet
$Sheet $Sheet
S 8500 2200 1350 800 S 8100 4150 1350 800
U 56C6F777 U 56C6F777
F0 "sdram" 60 F0 "sdram" 60
F1 "sdram.sch" 60 F1 "sdram.sch" 60
F2 "A[19..23]" I L 8500 2550 60 F2 "A[19..23]" I L 8100 4500 60
F3 "BL0_N" I L 8500 2350 60 F3 "BL0_N" I L 8100 4300 60
F4 "BL1_N" I L 8500 2450 60 F4 "BL1_N" I L 8100 4400 60
F5 "AWS" O R 9850 2300 60 F5 "AWS" O R 9450 4250 60
F6 "ABCK" O R 9850 2400 60 F6 "ABCK" O R 9450 4350 60
F7 "L3MODE" O R 9850 2800 60 F7 "L3MODE" O R 9450 4750 60
F8 "L3CLK" O R 9850 2900 60 F8 "L3DATA" O R 9450 4650 60
F9 "L3DATA" O R 9850 2700 60 F9 "ADATA" O R 9450 4550 60
F10 "ADATA" O R 9850 2600 60 F10 "ACLK" O R 9450 4450 60
F11 "ACLK" O R 9850 2500 60
$EndSheet $EndSheet
Wire Bus Line Wire Bus Line
8500 2550 8350 2550 8100 4500 7950 4500
Wire Wire Line Wire Wire Line
8350 2350 8500 2350 7950 4300 8100 4300
Wire Wire Line Wire Wire Line
8500 2450 8350 2450 8100 4400 7950 4400
$Sheet $Sheet
S 3600 1450 1000 500 S 4350 3050 1400 850
U 56C86141
F0 "userif" 60
F1 "userif.sch" 60
F2 "SW_A" O R 4600 1550 60
F3 "SW_D" O R 4600 1850 60
F4 "SW_B" O R 4600 1650 60
F5 "SW_C" O R 4600 1750 60
F6 "JTMS" I L 3600 1600 60
F7 "JTCK" I L 3600 1700 60
F8 "JTDI" I L 3600 1800 60
$EndSheet
$Sheet
S 4750 1100 1400 1000
U 56C7DD81 U 56C7DD81
F0 "sdcard" 60 F0 "sdcard" 60
F1 "sdcard.sch" 60 F1 "sdcard.sch" 60
F2 "SDIO_CMD" I R 6150 1250 60 F2 "SDIO_CMD" I R 5750 3200 60
F3 "T_IRQ" I L 4750 1250 60 F3 "T_IRQ" I L 4350 3200 60
F4 "T_BUSY" I L 4750 1350 60 F4 "T_BUSY" I L 4350 3300 60
F5 "SW_B" I L 4750 1650 60 F5 "SW_B" I L 4350 3600 60
F6 "SW_A" I L 4750 1550 60 F6 "SW_A" I L 4350 3500 60
F7 "SW_D" I L 4750 1850 60 F7 "SW_D" I L 4350 3800 60
F8 "SW_C" I L 4750 1750 60 F8 "SW_C" I L 4350 3700 60
F9 "SDCARD_DETECT" O L 4350 3400 60
$EndSheet $EndSheet
Wire Wire Line Wire Wire Line
8350 1250 8500 1250 7950 3200 8100 3200
Wire Wire Line Wire Wire Line
8500 1350 8350 1350 8100 3300 7950 3300
Wire Wire Line Wire Wire Line
8350 1450 8500 1450 7950 3400 8100 3400
Wire Wire Line Wire Wire Line
8500 1550 8350 1550 8100 3500 7950 3500
Wire Wire Line Wire Wire Line
10250 1250 10350 1250 9850 3200 9950 3200
Wire Wire Line Wire Wire Line
10350 1250 10350 950 9950 3200 9950 2900
Wire Wire Line Wire Wire Line
10350 950 4500 950 9950 2900 4250 2900
Wire Wire Line Wire Wire Line
4450 900 10400 900 4200 2850 10000 2850
Wire Wire Line Wire Wire Line
10400 900 10400 1350 10000 2850 10000 3300
Wire Wire Line Wire Wire Line
10400 1350 10250 1350 10000 3300 9850 3300
Wire Wire Line Wire Wire Line
4600 1550 4750 1550 5900 3200 5750 3200
Wire Wire Line Wire Wire Line
4600 1650 4750 1650 4250 2900 4250 3200
Wire Wire Line Wire Wire Line
4750 1750 4600 1750 4250 3200 4350 3200
Wire Wire Line Wire Wire Line
4600 1850 4750 1850 4350 3300 4200 3300
Wire Wire Line Wire Wire Line
6300 1250 6150 1250 4200 3300 4200 2850
Wire Wire Line Wire Wire Line
4500 950 4500 1250 2750 4400 5900 4400
Wire Wire Line Wire Wire Line
4500 1250 4750 1250 5900 4300 2750 4300
Wire Wire Line Wire Wire Line
4750 1350 4450 1350 2750 4200 5900 4200
Wire Wire Line
4450 1350 4450 900
Wire Wire Line
3450 2450 6300 2450
Wire Wire Line
6300 2350 3450 2350
Wire Wire Line
3450 2250 6300 2250
Wire Wire Line
3450 1600 3600 1600
Wire Wire Line
3600 1700 3450 1700
Wire Wire Line
3450 1800 3600 1800
$Sheet $Sheet
S 10000 2200 600 800 S 9600 4150 600 800
U 56CA5D53 U 56CA5D53
F0 "audio" 60 F0 "audio" 60
F1 "audio.sch" 60 F1 "audio.sch" 60
F2 "ACLK" I L 10000 2500 60 F2 "ACLK" I L 9600 4450 60
F3 "ABCK" I L 10000 2400 60 F3 "ABCK" I L 9600 4350 60
F4 "AWS" I L 10000 2300 60 F4 "AWS" I L 9600 4250 60
F5 "ADATA" I L 10000 2600 60 F5 "ADATA" I L 9600 4550 60
F6 "L3CLK" I L 10000 2900 60 F6 "L3MODE" I L 9600 4750 60
F7 "L3MODE" I L 10000 2800 60 F7 "L3DATA" I L 9600 4650 60
F8 "L3DATA" I L 10000 2700 60
$EndSheet $EndSheet
Wire Wire Line Wire Wire Line
9850 2300 10000 2300 9450 4250 9600 4250
Wire Wire Line Wire Wire Line
9850 2400 10000 2400 9450 4350 9600 4350
Wire Wire Line Wire Wire Line
10000 2500 9850 2500 9600 4450 9450 4450
Wire Wire Line Wire Wire Line
9850 2600 10000 2600 9450 4550 9600 4550
Wire Wire Line Wire Wire Line
10000 2700 9850 2700 9600 4650 9450 4650
Wire Wire Line Wire Wire Line
9850 2800 10000 2800 9450 4750 9600 4750
$Sheet
S 2900 2100 1200 1800
U 56C86141
F0 "userif" 60
F1 "userif.sch" 60
F2 "SW_A" O R 4100 3500 60
F3 "SW_D" O R 4100 3800 60
F4 "SW_B" O R 4100 3600 60
F5 "SW_C" O R 4100 3700 60
F6 "JTMS" I L 2900 3550 60
F7 "JTCK" I L 2900 3650 60
F8 "SYS_VOLTAGE" I L 2900 2200 60
F9 "JTDI" I L 2900 3750 60
F10 "CHG_ACTIVE_N" I L 2900 2300 60
F11 "CHARGE_ENABLE" O L 2900 2400 60
F12 "USB_PRESENT_N" I L 2900 2600 60
F13 "FPGA_ENABLE_N" O L 2900 2500 60
F14 "SDCARD_DETECT" I R 4100 3400 60
$EndSheet
Wire Wire Line Wire Wire Line
10000 2900 9850 2900 2900 2200 2750 2200
Wire Wire Line
2750 2300 2900 2300
Wire Wire Line
2900 2400 2750 2400
Wire Wire Line
2900 2500 2750 2500
Wire Wire Line
2750 2600 2900 2600
Wire Wire Line
4100 3500 4350 3500
Wire Wire Line
4350 3600 4100 3600
Wire Wire Line
4100 3700 4350 3700
Wire Wire Line
4350 3800 4100 3800
Wire Wire Line
2900 3550 2750 3550
Wire Wire Line
2750 3650 2900 3650
Wire Wire Line
2900 3750 2750 3750
Wire Wire Line
4350 3400 4100 3400
$EndSCHEMATC $EndSCHEMATC

508
power.sch
View File

File diff suppressed because it is too large Load Diff

37
sdcard.sch
View File

@ -44,7 +44,7 @@ EELAYER 25 0
EELAYER END EELAYER END
$Descr A4 11693 8268 $Descr A4 11693 8268
encoding utf-8 encoding utf-8
Sheet 8 9 Sheet 7 9
Title "" Title ""
Date "" Date ""
Rev "" Rev ""
@ -54,19 +54,6 @@ Comment2 ""
Comment3 "" Comment3 ""
Comment4 "" Comment4 ""
$EndDescr $EndDescr
$Comp
L STM32F407VGT U?
U 4 1 56C7DE2F
P 5800 2450
AR Path="/56C43C85/56C7DE2F" Ref="U?" Part="4"
AR Path="/56C7DD81/56C7DE2F" Ref="U4" Part="4"
F 0 "U4" H 6578 1653 60 0000 L CNN
F 1 "STM32F407VGT" H 6578 1547 60 0000 L CNN
F 2 "footprints:LQFP-100_14x14mm_Pitch0.5mm-SMALLCORNER" H 5300 2950 60 0001 C CNN
F 3 "" H 5300 2950 60 0000 C CNN
4 5800 2450
1 0 0 -1
$EndComp
Text HLabel 5600 2350 2 60 Input ~ 0 Text HLabel 5600 2350 2 60 Input ~ 0
SDIO_CMD SDIO_CMD
Text Label 3400 3750 2 60 ~ 0 Text Label 3400 3750 2 60 ~ 0
@ -300,4 +287,26 @@ F 3 "" H 1900 2450 50 0000 C CNN
$EndComp $EndComp
Wire Wire Line Wire Wire Line
2050 2450 1900 2450 2050 2450 1900 2450
NoConn ~ 5600 4050
$Comp
L STM32F407VGT U?
U 4 1 56C7DE2F
P 5800 2450
AR Path="/56C43C85/56C7DE2F" Ref="U?" Part="4"
AR Path="/56C7DD81/56C7DE2F" Ref="U4" Part="4"
F 0 "U4" H 6578 1653 60 0000 L CNN
F 1 "STM32F407VGT" H 6578 1547 60 0000 L CNN
F 2 "footprints:LQFP-100_14x14mm_Pitch0.5mm-SMALLCORNER" H 5300 2950 60 0001 C CNN
F 3 "" H 5300 2950 60 0000 C CNN
4 5800 2450
1 0 0 -1
$EndComp
NoConn ~ 5600 3950
NoConn ~ 5600 3850
NoConn ~ 5600 3050
NoConn ~ 5600 2950
Text HLabel 2950 2850 2 60 Output ~ 0
SDCARD_DETECT
Wire Wire Line
2950 2850 2900 2850
$EndSCHEMATC $EndSCHEMATC

169
sdram.sch
View File

@ -177,8 +177,8 @@ U 4 1 56C7D38D
P 9400 2300 P 9400 2300
AR Path="/56C43C85/56C7D38D" Ref="U?" Part="4" AR Path="/56C43C85/56C7D38D" Ref="U?" Part="4"
AR Path="/56C6F777/56C7D38D" Ref="U3" Part="4" AR Path="/56C6F777/56C7D38D" Ref="U3" Part="4"
F 0 "U3" H 9400 3237 60 0000 C CNN F 0 "U3" H 9400 3200 60 0000 C CNN
F 1 "LFXP2-5E-6TN144C" H 9400 3131 60 0000 C CNN F 1 "LFXP2-5E-6TN144C" H 9400 3100 60 0000 C CNN
F 2 "Housings_QFP:LQFP-144_20x20mm_Pitch0.5mm" H 8700 2650 60 0001 C CNN F 2 "Housings_QFP:LQFP-144_20x20mm_Pitch0.5mm" H 8700 2650 60 0001 C CNN
F 3 "http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/LatticeXP2/LatticeXP2FamilyDataSheet.pdf" H 8350 3550 60 0001 C CNN F 3 "http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/LatticeXP2/LatticeXP2FamilyDataSheet.pdf" H 8350 3550 60 0001 C CNN
F 4 "1.0" H 5750 3450 60 0001 C CNN "Version" F 4 "1.0" H 5750 3450 60 0001 C CNN "Version"
@ -224,10 +224,10 @@ F 3 "" H 5550 4100 50 0000 C CNN
-1 0 0 -1 -1 0 0 -1
$EndComp $EndComp
$Comp $Comp
L GND #PWR605 L GND #PWR608
U 1 1 56C80525 U 1 1 56C80525
P 6100 4400 P 6100 4400
F 0 "#PWR605" H 6100 4150 50 0001 C CNN F 0 "#PWR608" H 6100 4150 50 0001 C CNN
F 1 "GND" H 6108 4226 50 0000 C CNN F 1 "GND" H 6108 4226 50 0000 C CNN
F 2 "" H 6100 4400 50 0000 C CNN F 2 "" H 6100 4400 50 0000 C CNN
F 3 "" H 6100 4400 50 0000 C CNN F 3 "" H 6100 4400 50 0000 C CNN
@ -235,10 +235,10 @@ F 3 "" H 6100 4400 50 0000 C CNN
-1 0 0 -1 -1 0 0 -1
$EndComp $EndComp
$Comp $Comp
L GND #PWR604 L GND #PWR607
U 1 1 56C8052B U 1 1 56C8052B
P 5900 4400 P 5900 4400
F 0 "#PWR604" H 5900 4150 50 0001 C CNN F 0 "#PWR607" H 5900 4150 50 0001 C CNN
F 1 "GND" H 5908 4226 50 0000 C CNN F 1 "GND" H 5908 4226 50 0000 C CNN
F 2 "" H 5900 4400 50 0000 C CNN F 2 "" H 5900 4400 50 0000 C CNN
F 3 "" H 5900 4400 50 0000 C CNN F 3 "" H 5900 4400 50 0000 C CNN
@ -246,10 +246,10 @@ F 3 "" H 5900 4400 50 0000 C CNN
-1 0 0 -1 -1 0 0 -1
$EndComp $EndComp
$Comp $Comp
L GND #PWR602 L GND #PWR605
U 1 1 56C80531 U 1 1 56C80531
P 5650 4400 P 5650 4400
F 0 "#PWR602" H 5650 4150 50 0001 C CNN F 0 "#PWR605" H 5650 4150 50 0001 C CNN
F 1 "GND" H 5658 4226 50 0000 C CNN F 1 "GND" H 5658 4226 50 0000 C CNN
F 2 "" H 5650 4400 50 0000 C CNN F 2 "" H 5650 4400 50 0000 C CNN
F 3 "" H 5650 4400 50 0000 C CNN F 3 "" H 5650 4400 50 0000 C CNN
@ -257,10 +257,10 @@ F 3 "" H 5650 4400 50 0000 C CNN
-1 0 0 -1 -1 0 0 -1
$EndComp $EndComp
$Comp $Comp
L VFPGA33 #PWR601 L VFPGA33 #PWR604
U 1 1 56C8053D U 1 1 56C8053D
P 5550 3850 P 5550 3850
F 0 "#PWR601" H 5550 3700 50 0001 C CNN F 0 "#PWR604" H 5550 3700 50 0001 C CNN
F 1 "VFPGA33" H 5568 4024 50 0000 C CNN F 1 "VFPGA33" H 5568 4024 50 0000 C CNN
F 2 "" H 5550 3850 50 0000 C CNN F 2 "" H 5550 3850 50 0000 C CNN
F 3 "" H 5550 3850 50 0000 C CNN F 3 "" H 5550 3850 50 0000 C CNN
@ -268,10 +268,10 @@ F 3 "" H 5550 3850 50 0000 C CNN
-1 0 0 -1 -1 0 0 -1
$EndComp $EndComp
$Comp $Comp
L VFPGA33 #PWR603 L VFPGA33 #PWR606
U 1 1 56C80543 U 1 1 56C80543
P 5750 3750 P 5750 3750
F 0 "#PWR603" H 5750 3600 50 0001 C CNN F 0 "#PWR606" H 5750 3600 50 0001 C CNN
F 1 "VFPGA33" H 5768 3924 50 0000 C CNN F 1 "VFPGA33" H 5768 3924 50 0000 C CNN
F 2 "" H 5750 3750 50 0000 C CNN F 2 "" H 5750 3750 50 0000 C CNN
F 3 "" H 5750 3750 50 0000 C CNN F 3 "" H 5750 3750 50 0000 C CNN
@ -301,10 +301,10 @@ F 3 "" H 8150 4100 50 0000 C CNN
-1 0 0 -1 -1 0 0 -1
$EndComp $EndComp
$Comp $Comp
L GND #PWR613 L GND #PWR616
U 1 1 56C8079E U 1 1 56C8079E
P 8700 4400 P 8700 4400
F 0 "#PWR613" H 8700 4150 50 0001 C CNN F 0 "#PWR616" H 8700 4150 50 0001 C CNN
F 1 "GND" H 8708 4226 50 0000 C CNN F 1 "GND" H 8708 4226 50 0000 C CNN
F 2 "" H 8700 4400 50 0000 C CNN F 2 "" H 8700 4400 50 0000 C CNN
F 3 "" H 8700 4400 50 0000 C CNN F 3 "" H 8700 4400 50 0000 C CNN
@ -312,10 +312,10 @@ F 3 "" H 8700 4400 50 0000 C CNN
-1 0 0 -1 -1 0 0 -1
$EndComp $EndComp
$Comp $Comp
L GND #PWR612 L GND #PWR615
U 1 1 56C807A4 U 1 1 56C807A4
P 8500 4400 P 8500 4400
F 0 "#PWR612" H 8500 4150 50 0001 C CNN F 0 "#PWR615" H 8500 4150 50 0001 C CNN
F 1 "GND" H 8508 4226 50 0000 C CNN F 1 "GND" H 8508 4226 50 0000 C CNN
F 2 "" H 8500 4400 50 0000 C CNN F 2 "" H 8500 4400 50 0000 C CNN
F 3 "" H 8500 4400 50 0000 C CNN F 3 "" H 8500 4400 50 0000 C CNN
@ -323,10 +323,10 @@ F 3 "" H 8500 4400 50 0000 C CNN
-1 0 0 -1 -1 0 0 -1
$EndComp $EndComp
$Comp $Comp
L GND #PWR610 L GND #PWR613
U 1 1 56C807AA U 1 1 56C807AA
P 8250 4400 P 8250 4400
F 0 "#PWR610" H 8250 4150 50 0001 C CNN F 0 "#PWR613" H 8250 4150 50 0001 C CNN
F 1 "GND" H 8258 4226 50 0000 C CNN F 1 "GND" H 8258 4226 50 0000 C CNN
F 2 "" H 8250 4400 50 0000 C CNN F 2 "" H 8250 4400 50 0000 C CNN
F 3 "" H 8250 4400 50 0000 C CNN F 3 "" H 8250 4400 50 0000 C CNN
@ -334,10 +334,10 @@ F 3 "" H 8250 4400 50 0000 C CNN
-1 0 0 -1 -1 0 0 -1
$EndComp $EndComp
$Comp $Comp
L VFPGA33 #PWR609 L VFPGA33 #PWR612
U 1 1 56C807B6 U 1 1 56C807B6
P 8150 3850 P 8150 3850
F 0 "#PWR609" H 8150 3700 50 0001 C CNN F 0 "#PWR612" H 8150 3700 50 0001 C CNN
F 1 "VFPGA33" H 8168 4024 50 0000 C CNN F 1 "VFPGA33" H 8168 4024 50 0000 C CNN
F 2 "" H 8150 3850 50 0000 C CNN F 2 "" H 8150 3850 50 0000 C CNN
F 3 "" H 8150 3850 50 0000 C CNN F 3 "" H 8150 3850 50 0000 C CNN
@ -345,10 +345,10 @@ F 3 "" H 8150 3850 50 0000 C CNN
-1 0 0 -1 -1 0 0 -1
$EndComp $EndComp
$Comp $Comp
L VFPGA33 #PWR611 L VFPGA33 #PWR614
U 1 1 56C807BC U 1 1 56C807BC
P 8350 3750 P 8350 3750
F 0 "#PWR611" H 8350 3600 50 0001 C CNN F 0 "#PWR614" H 8350 3600 50 0001 C CNN
F 1 "VFPGA33" H 8368 3924 50 0000 C CNN F 1 "VFPGA33" H 8368 3924 50 0000 C CNN
F 2 "" H 8350 3750 50 0000 C CNN F 2 "" H 8350 3750 50 0000 C CNN
F 3 "" H 8350 3750 50 0000 C CNN F 3 "" H 8350 3750 50 0000 C CNN
@ -367,10 +367,10 @@ F 3 "" H 7700 4200 50 0000 C CNN
-1 0 0 -1 -1 0 0 -1
$EndComp $EndComp
$Comp $Comp
L GND #PWR606 L GND #PWR609
U 1 1 56C8090E U 1 1 56C8090E
P 7500 4400 P 7500 4400
F 0 "#PWR606" H 7500 4150 50 0001 C CNN F 0 "#PWR609" H 7500 4150 50 0001 C CNN
F 1 "GND" H 7508 4226 50 0000 C CNN F 1 "GND" H 7508 4226 50 0000 C CNN
F 2 "" H 7500 4400 50 0000 C CNN F 2 "" H 7500 4400 50 0000 C CNN
F 3 "" H 7500 4400 50 0000 C CNN F 3 "" H 7500 4400 50 0000 C CNN
@ -378,10 +378,10 @@ F 3 "" H 7500 4400 50 0000 C CNN
-1 0 0 -1 -1 0 0 -1
$EndComp $EndComp
$Comp $Comp
L GND #PWR608 L GND #PWR611
U 1 1 56C80914 U 1 1 56C80914
P 7700 4400 P 7700 4400
F 0 "#PWR608" H 7700 4150 50 0001 C CNN F 0 "#PWR611" H 7700 4150 50 0001 C CNN
F 1 "GND" H 7708 4226 50 0000 C CNN F 1 "GND" H 7708 4226 50 0000 C CNN
F 2 "" H 7700 4400 50 0000 C CNN F 2 "" H 7700 4400 50 0000 C CNN
F 3 "" H 7700 4400 50 0000 C CNN F 3 "" H 7700 4400 50 0000 C CNN
@ -389,10 +389,10 @@ F 3 "" H 7700 4400 50 0000 C CNN
-1 0 0 -1 -1 0 0 -1
$EndComp $EndComp
$Comp $Comp
L VFPGA33 #PWR607 L VFPGA33 #PWR610
U 1 1 56C8091F U 1 1 56C8091F
P 7700 3750 P 7700 3750
F 0 "#PWR607" H 7700 3600 50 0001 C CNN F 0 "#PWR610" H 7700 3600 50 0001 C CNN
F 1 "VFPGA33" H 7718 3924 50 0000 C CNN F 1 "VFPGA33" H 7718 3924 50 0000 C CNN
F 2 "" H 7700 3750 50 0000 C CNN F 2 "" H 7700 3750 50 0000 C CNN
F 3 "" H 7700 3750 50 0000 C CNN F 3 "" H 7700 3750 50 0000 C CNN
@ -411,10 +411,10 @@ F 3 "" H 10300 4200 50 0000 C CNN
-1 0 0 -1 -1 0 0 -1
$EndComp $EndComp
$Comp $Comp
L GND #PWR614 L GND #PWR617
U 1 1 56C80AD8 U 1 1 56C80AD8
P 10100 4400 P 10100 4400
F 0 "#PWR614" H 10100 4150 50 0001 C CNN F 0 "#PWR617" H 10100 4150 50 0001 C CNN
F 1 "GND" H 10108 4226 50 0000 C CNN F 1 "GND" H 10108 4226 50 0000 C CNN
F 2 "" H 10100 4400 50 0000 C CNN F 2 "" H 10100 4400 50 0000 C CNN
F 3 "" H 10100 4400 50 0000 C CNN F 3 "" H 10100 4400 50 0000 C CNN
@ -422,10 +422,10 @@ F 3 "" H 10100 4400 50 0000 C CNN
-1 0 0 -1 -1 0 0 -1
$EndComp $EndComp
$Comp $Comp
L GND #PWR616 L GND #PWR619
U 1 1 56C80ADE U 1 1 56C80ADE
P 10300 4400 P 10300 4400
F 0 "#PWR616" H 10300 4150 50 0001 C CNN F 0 "#PWR619" H 10300 4150 50 0001 C CNN
F 1 "GND" H 10308 4226 50 0000 C CNN F 1 "GND" H 10308 4226 50 0000 C CNN
F 2 "" H 10300 4400 50 0000 C CNN F 2 "" H 10300 4400 50 0000 C CNN
F 3 "" H 10300 4400 50 0000 C CNN F 3 "" H 10300 4400 50 0000 C CNN
@ -433,10 +433,10 @@ F 3 "" H 10300 4400 50 0000 C CNN
-1 0 0 -1 -1 0 0 -1
$EndComp $EndComp
$Comp $Comp
L VFPGA33 #PWR615 L VFPGA33 #PWR618
U 1 1 56C80AE9 U 1 1 56C80AE9
P 10300 3750 P 10300 3750
F 0 "#PWR615" H 10300 3600 50 0001 C CNN F 0 "#PWR618" H 10300 3600 50 0001 C CNN
F 1 "VFPGA33" H 10318 3924 50 0000 C CNN F 1 "VFPGA33" H 10318 3924 50 0000 C CNN
F 2 "" H 10300 3750 50 0000 C CNN F 2 "" H 10300 3750 50 0000 C CNN
F 3 "" H 10300 3750 50 0000 C CNN F 3 "" H 10300 3750 50 0000 C CNN
@ -549,19 +549,17 @@ Entry Wire Line
5750 2400 5850 2300 5750 2400 5850 2300
Entry Wire Line Entry Wire Line
5750 2500 5850 2400 5750 2500 5850 2400
Text HLabel 5600 2800 0 60 Output ~ 0 Text HLabel 5650 3000 0 60 Output ~ 0
AWS AWS
Text HLabel 5600 2700 0 60 Output ~ 0 Text HLabel 5650 3100 0 60 Output ~ 0
ABCK ABCK
Text HLabel 5600 2600 0 60 Output ~ 0 Text HLabel 5650 2600 0 60 Output ~ 0
ADATA ADATA
Text HLabel 5600 2500 0 60 Output ~ 0 Text HLabel 5650 2800 0 60 Output ~ 0
ACLK ACLK
Text HLabel 5600 3100 0 60 Output ~ 0 Text HLabel 5650 2700 0 60 Output ~ 0
L3DATA L3DATA
Text HLabel 5600 3000 0 60 Output ~ 0 Text HLabel 5650 2500 0 60 Output ~ 0
L3CLK
Text HLabel 5600 2900 0 60 Output ~ 0
L3MODE L3MODE
Wire Wire Line Wire Wire Line
5700 2500 5650 2500 5700 2500 5650 2500
@ -720,17 +718,15 @@ Wire Wire Line
Wire Wire Line Wire Wire Line
6150 3200 5850 3200 6150 3200 5850 3200
Wire Wire Line Wire Wire Line
6150 3100 5850 3100 6150 3100 5650 3100
Wire Wire Line Wire Wire Line
6150 3000 5850 3000 6150 3000 5650 3000
Wire Wire Line Wire Wire Line
6150 2900 5850 2900 6150 2600 5650 2600
Wire Wire Line Wire Wire Line
6150 2800 5850 2800 6150 2800 5650 2800
Wire Wire Line Wire Wire Line
6150 2700 5850 2700 6150 2700 5650 2700
Wire Wire Line
6150 2600 5850 2600
Wire Wire Line Wire Wire Line
5800 2500 6150 2500 5800 2500 6150 2500
Wire Wire Line Wire Wire Line
@ -823,4 +819,79 @@ Wire Wire Line
3100 2800 2850 2800 3100 2800 2850 2800
Wire Wire Line Wire Wire Line
3100 2700 2850 2700 3100 2700 2850 2700
Wire Wire Line
6150 2900 5750 2900
$Comp
L TCXO_DFAS11 X601
U 1 1 56CA3014
P 2850 5400
F 0 "X601" H 2850 5700 70 0000 C CNN
F 1 "TCXO_DFAS11" H 2850 5400 50 0000 C CNN
F 2 "Crystals:Crystal_SMD_0603_4Pads" H 2850 5400 60 0001 C CNN
F 3 "" H 2850 5400 60 0000 C CNN
1 2850 5400
1 0 0 -1
$EndComp
$Comp
L GND #PWR603
U 1 1 56CA301B
P 3650 5650
F 0 "#PWR603" H 3650 5400 50 0001 C CNN
F 1 "GND" H 3650 5500 50 0000 C CNN
F 2 "" H 3650 5650 60 0000 C CNN
F 3 "" H 3650 5650 60 0000 C CNN
1 3650 5650
1 0 0 -1
$EndComp
$Comp
L VFPGA33 #PWR601
U 1 1 56CA3022
P 1950 5150
F 0 "#PWR601" H 1950 5000 50 0001 C CNN
F 1 "VFPGA33" H 1968 5324 50 0000 C CNN
F 2 "" H 1950 5150 50 0000 C CNN
F 3 "" H 1950 5150 50 0000 C CNN
1 1950 5150
1 0 0 -1
$EndComp
Wire Wire Line
1950 5150 1950 5300
Wire Wire Line
3650 5650 3650 5550
Wire Wire Line
3650 5550 3550 5550
Wire Wire Line
3950 5250 3550 5250
Text Label 3950 5250 2 60 ~ 0
CLK_50M
Text Label 5750 2900 0 60 ~ 0
CLK_50M
$Comp
L C 100n601
U 1 1 56CA32A6
P 1950 5450
F 0 "100n601" H 2065 5496 50 0000 L CNN
F 1 "C" H 2065 5404 50 0000 L CNN
F 2 "" H 1988 5300 50 0001 C CNN
F 3 "" H 1950 5450 50 0000 C CNN
1 1950 5450
1 0 0 -1
$EndComp
$Comp
L GND #PWR602
U 1 1 56CA3322
P 1950 5650
F 0 "#PWR602" H 1950 5400 50 0001 C CNN
F 1 "GND" H 1950 5500 50 0000 C CNN
F 2 "" H 1950 5650 60 0000 C CNN
F 3 "" H 1950 5650 60 0000 C CNN
1 1950 5650
1 0 0 -1
$EndComp
Wire Wire Line
1950 5650 1950 5600
Wire Wire Line
2150 5250 1950 5250
Connection ~ 1950 5250
NoConn ~ 2150 5550
$EndSCHEMATC $EndSCHEMATC

84
userif.sch
View File

@ -44,7 +44,7 @@ EELAYER 25 0
EELAYER END EELAYER END
$Descr A4 11693 8268 $Descr A4 11693 8268
encoding utf-8 encoding utf-8
Sheet 7 9 Sheet 9 9
Title "" Title ""
Date "" Date ""
Rev "" Rev ""
@ -393,11 +393,7 @@ RGBLED2
Wire Wire Line Wire Wire Line
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Wire Wire Line Wire Wire Line
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Wire Wire Line
9850 2650 9850 2850
Wire Wire Line
9850 2850 9850 3000
Wire Wire Line Wire Wire Line
9800 2850 9850 2850 9800 2850 9850 2850
Connection ~ 9850 2850 Connection ~ 9850 2850
@ -405,10 +401,10 @@ Wire Wire Line
9800 2650 9850 2650 9800 2650 9850 2650
Connection ~ 9850 2650 Connection ~ 9850 2650
$Comp $Comp
L GND #PWR? L GND #PWR709
U 1 1 56C8F2B5 U 1 1 56C8F2B5
P 9850 3000 P 9850 3000
F 0 "#PWR?" H 9850 2750 50 0001 C CNN F 0 "#PWR709" H 9850 2750 50 0001 C CNN
F 1 "GND" H 9858 2826 50 0000 C CNN F 1 "GND" H 9858 2826 50 0000 C CNN
F 2 "" H 9850 3000 50 0000 C CNN F 2 "" H 9850 3000 50 0000 C CNN
F 3 "" H 9850 3000 50 0000 C CNN F 3 "" H 9850 3000 50 0000 C CNN
@ -416,34 +412,34 @@ F 3 "" H 9850 3000 50 0000 C CNN
1 0 0 -1 1 0 0 -1
$EndComp $EndComp
$Comp $Comp
L R R? L R R701
U 1 1 56C8FF13 U 1 1 56C8FF13
P 9200 2450 P 9200 2450
F 0 "R?" V 9100 2450 50 0000 C CNN F 0 "R701" V 9100 2450 50 0000 C CNN
F 1 "220" V 9200 2450 50 0000 C CNN F 1 "220" V 9200 2450 50 0000 C CNN
F 2 "" V 9130 2450 50 0000 C CNN F 2 "" V 9130 2450 50 0001 C CNN
F 3 "" H 9200 2450 50 0000 C CNN F 3 "" H 9200 2450 50 0000 C CNN
1 9200 2450 1 9200 2450
0 1 1 0 0 1 1 0
$EndComp $EndComp
$Comp $Comp
L R R? L R R702
U 1 1 56C90060 U 1 1 56C90060
P 9200 2650 P 9200 2650
F 0 "R?" V 9100 2650 50 0000 C CNN F 0 "R702" V 9100 2650 50 0000 C CNN
F 1 "220" V 9200 2650 50 0000 C CNN F 1 "220" V 9200 2650 50 0000 C CNN
F 2 "" V 9130 2650 50 0000 C CNN F 2 "" V 9130 2650 50 0001 C CNN
F 3 "" H 9200 2650 50 0000 C CNN F 3 "" H 9200 2650 50 0000 C CNN
1 9200 2650 1 9200 2650
0 1 1 0 0 1 1 0
$EndComp $EndComp
$Comp $Comp
L R R? L R R703
U 1 1 56C90098 U 1 1 56C90098
P 9200 2850 P 9200 2850
F 0 "R?" V 9100 2850 50 0000 C CNN F 0 "R703" V 9100 2850 50 0000 C CNN
F 1 "220" V 9200 2850 50 0000 C CNN F 1 "220" V 9200 2850 50 0000 C CNN
F 2 "" V 9130 2850 50 0000 C CNN F 2 "" V 9130 2850 50 0001 C CNN
F 3 "" H 9200 2850 50 0000 C CNN F 3 "" H 9200 2850 50 0000 C CNN
1 9200 2850 1 9200 2850
0 1 1 0 0 1 1 0
@ -454,40 +450,34 @@ Wire Wire Line
9400 2650 9350 2650 9400 2650 9350 2650
Wire Wire Line Wire Wire Line
9350 2450 9400 2450 9350 2450 9400 2450
$Comp
L SW_PUSH SW?
U 1 1 56C90B91
P 9500 3550
F 0 "SW?" H 9500 3806 50 0000 C CNN
F 1 "DOWN" H 9500 3714 50 0000 C CNN
F 2 "smd:Tactile_Switch" H 9500 3550 50 0001 C CNN
F 3 "" H 9500 3550 50 0000 C CNN
1 9500 3550
1 0 0 -1
$EndComp
Wire Wire Line
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Wire Wire Line
9850 3550 9850 3700
$Comp
L GND #PWR?
U 1 1 56C90DD8
P 9850 3700
F 0 "#PWR?" H 9850 3450 50 0001 C CNN
F 1 "GND" H 9858 3526 50 0000 C CNN
F 2 "" H 9850 3700 50 0000 C CNN
F 3 "" H 9850 3700 50 0000 C CNN
1 9850 3700
1 0 0 -1
$EndComp
Wire Wire Line
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Text Label 8600 3550 0 60 ~ 0
BTN_STBY
Text HLabel 2650 5500 0 60 Input ~ 0 Text HLabel 2650 5500 0 60 Input ~ 0
JTMS JTMS
Text HLabel 2650 5600 0 60 Input ~ 0 Text HLabel 2650 5600 0 60 Input ~ 0
JTCK JTCK
Text HLabel 2650 5700 0 60 Input ~ 0 Text HLabel 2650 5700 0 60 Input ~ 0
JTDI JTDI
Wire Wire Line
3100 4600 2550 4600
Text HLabel 2550 4500 0 60 Input ~ 0
SYS_VOLTAGE
Text HLabel 2550 4700 0 60 Input ~ 0
CHG_ACTIVE_N
Text HLabel 2550 4900 0 60 Output ~ 0
CHARGE_ENABLE
Text HLabel 2550 4800 0 60 Output ~ 0
FPGA_ENABLE_N
Text HLabel 2550 4600 0 60 Input ~ 0
USB_PRESENT_N
Wire Wire Line
2550 4500 3100 4500
Wire Wire Line
2550 4700 3100 4700
Wire Wire Line
3100 4800 2550 4800
Wire Wire Line
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Wire Wire Line
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Text HLabel 2650 5400 0 60 Input ~ 0
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