More or less done

2016-02-21 16:50:27 +01:00 · 2016-02-21 16:50:27 +01:00 · 4a05a6ed85
commit 4a05a6ed85
parent 1aef5adfad
12 changed files with 3646 additions and 3016 deletions
--- a/FSMC.sch
+++ b/FSMC.sch
@ -491,10 +491,6 @@ Wire Wire Line
 	4050 4500 3750 4500
 Wire Wire Line
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-Wire Wire Line
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 Wire Wire Line
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@ -535,4 +531,14 @@ Text HLabel 2300 2050 2    60   Input ~ 0
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+NoConn ~ 2200 1450
+NoConn ~ 2200 1150
+NoConn ~ 2200 1250
+NoConn ~ 2200 750 
+NoConn ~ 2200 650 
 $EndSCHEMATC
--- a/audio.sch
+++ b/audio.sch
@ -44,7 +44,7 @@ EELAYER 25 0
 EELAYER END
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@ -292,18 +323,14 @@ Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
 	1750 3000 2250 3000
 Wire Wire Line
@ -271,43 +271,157 @@ Wire Wire Line
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 Connection ~ 1550 2900
 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
-	5000 3100 5050 3100
-Wire Wire Line
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-Wire Wire Line
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 $Comp
-L VFPGA33 #PWR302
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 U 1 1 56CA6859
-P 3550 800
-F 0 "#PWR302" H 3550 650 50  0001 C CNN
-F 1 "VFPGA33" H 3568 974 50  0000 C CNN
-F 2 "" H 3550 800 50  0000 C CNN
-F 3 "" H 3550 800 50  0000 C CNN
-	1    3550 800 
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+F 3 "" H 2500 900 50  0000 C CNN
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 	1    0    0    -1  
 $EndComp
 $Comp
-L VFPGA33 #PWR305
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 U 1 1 56CA6C73
-P 5150 1400
-F 0 "#PWR305" H 5150 1250 50  0001 C CNN
-F 1 "VFPGA33" H 5168 1574 50  0000 C CNN
-F 2 "" H 5150 1400 50  0000 C CNN
-F 3 "" H 5150 1400 50  0000 C CNN
-	1    5150 1400
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+L VSTM33 #PWR302
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+F 3 "" H 2200 4100 50  0000 C CNN
+	1    2200 4100
 	1    0    0    -1  
 $EndComp
 $EndSCHEMATC
--- a/display.sch
+++ b/display.sch
@ -299,8 +299,6 @@ Text Label 2950 4950 2    60   ~ 0
 DB3
 Text Label 2950 4850 2    60   ~ 0
 RS
-Wire Wire Line
-	1350 4850 1050 4850
 Wire Wire Line
 	1350 4950 1050 4950
 Wire Wire Line
@ -476,4 +474,5 @@ Text HLabel 4600 3100 0    60   Output ~ 0
 T_BUSY
 Text HLabel 4600 3200 0    60   Output ~ 0
 T_IRQ
+NoConn ~ 1350 4850
 $EndSCHEMATC
--- a/fpgna-cache.lib
+++ b/fpgna-cache.lib
@ -92,6 +92,36 @@ X P6 6 -200 -250 150 R 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
+# CONN_02X03
+#
+DEF CONN_02X03 P 0 1 Y N 1 F N
+F0 "P" 0 200 50 H V C CNN
+F1 "CONN_02X03" 0 -200 50 H V C CNN
+F2 "" 0 -1200 50 H V C CNN
+F3 "" 0 -1200 50 H V C CNN
+$FPLIST
+ Pin_Header_Straight_2X03
+ Pin_Header_Angled_2X03
+ Socket_Strip_Straight_2X03
+ Socket_Strip_Angled_2X03
+$ENDFPLIST
+DRAW
+S -100 -95 -50 -105 0 1 0 N
+S -100 5 -50 -5 0 1 0 N
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+S -100 150 100 -150 0 1 0 N
+S 50 -95 100 -105 0 1 0 N
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+X P1 1 -250 100 150 R 50 50 1 1 P
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+X P4 4 250 0 150 L 50 50 1 1 P
+X P5 5 -250 -100 150 R 50 50 1 1 P
+X P6 6 250 -100 150 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
 # CP
 #
 DEF CP C 0 10 N Y 1 F N
--- a/fpgna.kicad_pcb
+++ b/fpgna.kicad_pcb
--- a/fpgna.net
+++ b/fpgna.net
--- a/fpgna.sch
+++ b/fpgna.sch
@ -55,181 +55,195 @@ Comment3 ""
 Comment4 ""
 $EndDescr
 $Sheet
-S 3550 3550 2050 1400
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 U 563244F7
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 F1 "power.sch" 60
-F2 "CHG_ACTIVE_N" O R 5600 3900 60 
-F3 "USB_PRESENT_N" O R 5600 3800 60 
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-F5 "SYS_VOLTAGE" O R 5600 4200 60 
-F6 "CLK_50M" O L 3550 3800 60 
-F7 "FPGA_ENABLE_N" I R 5600 4300 60 
+F2 "CHG_ACTIVE_N" O R 2750 2300 60 
+F3 "USB_PRESENT_N" O R 2750 2600 60 
+F4 "CHARGE_ENABLE" I R 2750 2400 60 
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 $EndSheet
 $Sheet
-S 2450 1450 1000 1100
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 U 56337D98
 F0 "debug" 60
 F1 "debug.sch" 60
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-F5 "JTCK" O R 3450 1700 60 
-F6 "JRST_N" O R 3450 2350 60 
-F7 "BOOT1" O R 3450 2450 60 
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 $EndSheet
 $Sheet
-S 6300 1100 2050 2150
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 U 56C43C85
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 F1 "FSMC.sch" 60
-F2 "BOOT1" I L 6300 2450 60 
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-F4 "JRST_N" I L 6300 2350 60 
-F5 "BL0_N" O R 8350 2350 60 
-F6 "BL1_N" O R 8350 2450 60 
-F7 "A[19..23]" O R 8350 2550 60 
-F8 "SDIO_CMD" O L 6300 1250 60 
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-F10 "T_CLK" O R 8350 1250 60 
-F11 "T_DOUT" I R 8350 1550 60 
-F12 "T_DIN" O R 8350 1450 60 
+F2 "BOOT1" I L 5900 4400 60 
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+F8 "SDIO_CMD" O L 5900 3200 60 
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+F10 "T_CLK" O R 7950 3200 60 
+F11 "T_DOUT" I R 7950 3500 60 
+F12 "T_DIN" O R 7950 3400 60 
 $EndSheet
 $Sheet
-S 8500 1100 1750 800 
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 U 56C579FC
 F0 "display" 60
 F1 "display.sch" 60
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-F3 "T_CS" I L 8500 1350 60 
-F4 "T_DIN" I L 8500 1450 60 
-F5 "T_DOUT" O L 8500 1550 60 
-F6 "T_BUSY" O R 10250 1350 60 
-F7 "T_IRQ" O R 10250 1250 60 
+F2 "T_CLK" I L 8100 3200 60 
+F3 "T_CS" I L 8100 3300 60 
+F4 "T_DIN" I L 8100 3400 60 
+F5 "T_DOUT" O L 8100 3500 60 
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+F7 "T_IRQ" O R 9850 3200 60 
 $EndSheet
 $Sheet
-S 8500 2200 1350 800 
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 U 56C6F777
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 F1 "sdram.sch" 60
-F2 "A[19..23]" I L 8500 2550 60 
-F3 "BL0_N" I L 8500 2350 60 
-F4 "BL1_N" I L 8500 2450 60 
-F5 "AWS" O R 9850 2300 60 
-F6 "ABCK" O R 9850 2400 60 
-F7 "L3MODE" O R 9850 2800 60 
-F8 "L3CLK" O R 9850 2900 60 
-F9 "L3DATA" O R 9850 2700 60 
-F10 "ADATA" O R 9850 2600 60 
-F11 "ACLK" O R 9850 2500 60 
+F2 "A[19..23]" I L 8100 4500 60 
+F3 "BL0_N" I L 8100 4300 60 
+F4 "BL1_N" I L 8100 4400 60 
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+F8 "L3DATA" O R 9450 4650 60 
+F9 "ADATA" O R 9450 4550 60 
+F10 "ACLK" O R 9450 4450 60 
 $EndSheet
 Wire Bus Line
-	8500 2550 8350 2550
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 Wire Wire Line
-	8350 2350 8500 2350
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 Wire Wire Line
-	8500 2450 8350 2450
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 $Sheet
-S 3600 1450 1000 500 
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-F0 "userif" 60
-F1 "userif.sch" 60
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-F6 "JTMS" I L 3600 1600 60 
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-F8 "JTDI" I L 3600 1800 60 
-$EndSheet
-$Sheet
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 F1 "sdcard.sch" 60
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-F3 "T_IRQ" I L 4750 1250 60 
-F4 "T_BUSY" I L 4750 1350 60 
-F5 "SW_B" I L 4750 1650 60 
-F6 "SW_A" I L 4750 1550 60 
-F7 "SW_D" I L 4750 1850 60 
-F8 "SW_C" I L 4750 1750 60 
+F2 "SDIO_CMD" I R 5750 3200 60 
+F3 "T_IRQ" I L 4350 3200 60 
+F4 "T_BUSY" I L 4350 3300 60 
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+F6 "SW_A" I L 4350 3500 60 
+F7 "SW_D" I L 4350 3800 60 
+F8 "SW_C" I L 4350 3700 60 
+F9 "SDCARD_DETECT" O L 4350 3400 60 
 $EndSheet
 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
-	10350 950  4500 950 
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
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 Wire Wire Line
-	4750 1350 4450 1350
-Wire Wire Line
-	4450 1350 4450 900 
-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
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-Wire Wire Line
-	3450 1600 3600 1600
-Wire Wire Line
-	3600 1700 3450 1700
-Wire Wire Line
-	3450 1800 3600 1800
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 $Sheet
-S 10000 2200 600  800 
+S 9600 4150 600  800 
 U 56CA5D53
 F0 "audio" 60
 F1 "audio.sch" 60
-F2 "ACLK" I L 10000 2500 60 
-F3 "ABCK" I L 10000 2400 60 
-F4 "AWS" I L 10000 2300 60 
-F5 "ADATA" I L 10000 2600 60 
-F6 "L3CLK" I L 10000 2900 60 
-F7 "L3MODE" I L 10000 2800 60 
-F8 "L3DATA" I L 10000 2700 60 
+F2 "ACLK" I L 9600 4450 60 
+F3 "ABCK" I L 9600 4350 60 
+F4 "AWS" I L 9600 4250 60 
+F5 "ADATA" I L 9600 4550 60 
+F6 "L3MODE" I L 9600 4750 60 
+F7 "L3DATA" I L 9600 4650 60 
 $EndSheet
 Wire Wire Line
-	9850 2300 10000 2300
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 Wire Wire Line
-	9850 2400 10000 2400
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 Wire Wire Line
-	10000 2500 9850 2500
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 Wire Wire Line
-	9850 2600 10000 2600
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 Wire Wire Line
-	10000 2700 9850 2700
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 Wire Wire Line
-	9850 2800 10000 2800
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+$Sheet
+S 2900 2100 1200 1800
+U 56C86141
+F0 "userif" 60
+F1 "userif.sch" 60
+F2 "SW_A" O R 4100 3500 60 
+F3 "SW_D" O R 4100 3800 60 
+F4 "SW_B" O R 4100 3600 60 
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+F6 "JTMS" I L 2900 3550 60 
+F7 "JTCK" I L 2900 3650 60 
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+F11 "CHARGE_ENABLE" O L 2900 2400 60 
+F12 "USB_PRESENT_N" I L 2900 2600 60 
+F13 "FPGA_ENABLE_N" O L 2900 2500 60 
+F14 "SDCARD_DETECT" I R 4100 3400 60 
+$EndSheet
 Wire Wire Line
-	10000 2900 9850 2900
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+Wire Wire Line
+	2750 2300 2900 2300
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+	2900 2400 2750 2400
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+	2900 3750 2750 3750
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+	4350 3400 4100 3400
 $EndSCHEMATC
--- a/power.sch
+++ b/power.sch
--- a/sdcard.sch
+++ b/sdcard.sch
@ -44,7 +44,7 @@ EELAYER 25 0
 EELAYER END
 $Descr A4 11693 8268
 encoding utf-8
-Sheet 8 9
+Sheet 7 9
 Title ""
 Date ""
 Rev ""
@ -54,19 +54,6 @@ Comment2 ""
 Comment3 ""
 Comment4 ""
 $EndDescr
-$Comp
-L STM32F407VGT U?
-U 4 1 56C7DE2F
-P 5800 2450
-AR Path="/56C43C85/56C7DE2F" Ref="U?"  Part="4" 
-AR Path="/56C7DD81/56C7DE2F" Ref="U4"  Part="4" 
-F 0 "U4" H 6578 1653 60  0000 L CNN
-F 1 "STM32F407VGT" H 6578 1547 60  0000 L CNN
-F 2 "footprints:LQFP-100_14x14mm_Pitch0.5mm-SMALLCORNER" H 5300 2950 60  0001 C CNN
-F 3 "" H 5300 2950 60  0000 C CNN
-	4    5800 2450
-	1    0    0    -1  
-$EndComp
 Text HLabel 5600 2350 2    60   Input ~ 0
 SDIO_CMD
 Text Label 3400 3750 2    60   ~ 0
@ -300,4 +287,26 @@ F 3 "" H 1900 2450 50  0000 C CNN
 $EndComp
 Wire Wire Line
 	2050 2450 1900 2450
+NoConn ~ 5600 4050
+$Comp
+L STM32F407VGT U?
+U 4 1 56C7DE2F
+P 5800 2450
+AR Path="/56C43C85/56C7DE2F" Ref="U?"  Part="4" 
+AR Path="/56C7DD81/56C7DE2F" Ref="U4"  Part="4" 
+F 0 "U4" H 6578 1653 60  0000 L CNN
+F 1 "STM32F407VGT" H 6578 1547 60  0000 L CNN
+F 2 "footprints:LQFP-100_14x14mm_Pitch0.5mm-SMALLCORNER" H 5300 2950 60  0001 C CNN
+F 3 "" H 5300 2950 60  0000 C CNN
+	4    5800 2450
+	1    0    0    -1  
+$EndComp
+NoConn ~ 5600 3950
+NoConn ~ 5600 3850
+NoConn ~ 5600 3050
+NoConn ~ 5600 2950
+Text HLabel 2950 2850 2    60   Output ~ 0
+SDCARD_DETECT
+Wire Wire Line
+	2950 2850 2900 2850
 $EndSCHEMATC
--- a/sdram.sch
+++ b/sdram.sch
@ -177,8 +177,8 @@ U 4 1 56C7D38D
 P 9400 2300
 AR Path="/56C43C85/56C7D38D" Ref="U?"  Part="4" 
 AR Path="/56C6F777/56C7D38D" Ref="U3"  Part="4" 
-F 0 "U3" H 9400 3237 60  0000 C CNN
-F 1 "LFXP2-5E-6TN144C" H 9400 3131 60  0000 C CNN
+F 0 "U3" H 9400 3200 60  0000 C CNN
+F 1 "LFXP2-5E-6TN144C" H 9400 3100 60  0000 C CNN
 F 2 "Housings_QFP:LQFP-144_20x20mm_Pitch0.5mm" H 8700 2650 60  0001 C CNN
 F 3 "http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/LatticeXP2/LatticeXP2FamilyDataSheet.pdf" H 8350 3550 60  0001 C CNN
 F 4 "1.0" H 5750 3450 60  0001 C CNN "Version"
@ -224,10 +224,10 @@ F 3 "" H 5550 4100 50  0000 C CNN
 	-1   0    0    -1  
 $EndComp
 $Comp
-L GND #PWR605
+L GND #PWR608
 U 1 1 56C80525
 P 6100 4400
-F 0 "#PWR605" H 6100 4150 50  0001 C CNN
+F 0 "#PWR608" H 6100 4150 50  0001 C CNN
 F 1 "GND" H 6108 4226 50  0000 C CNN
 F 2 "" H 6100 4400 50  0000 C CNN
 F 3 "" H 6100 4400 50  0000 C CNN
@ -235,10 +235,10 @@ F 3 "" H 6100 4400 50  0000 C CNN
 	-1   0    0    -1  
 $EndComp
 $Comp
-L GND #PWR604
+L GND #PWR607
 U 1 1 56C8052B
 P 5900 4400
-F 0 "#PWR604" H 5900 4150 50  0001 C CNN
+F 0 "#PWR607" H 5900 4150 50  0001 C CNN
 F 1 "GND" H 5908 4226 50  0000 C CNN
 F 2 "" H 5900 4400 50  0000 C CNN
 F 3 "" H 5900 4400 50  0000 C CNN
@ -246,10 +246,10 @@ F 3 "" H 5900 4400 50  0000 C CNN
 	-1   0    0    -1  
 $EndComp
 $Comp
-L GND #PWR602
+L GND #PWR605
 U 1 1 56C80531
 P 5650 4400
-F 0 "#PWR602" H 5650 4150 50  0001 C CNN
+F 0 "#PWR605" H 5650 4150 50  0001 C CNN
 F 1 "GND" H 5658 4226 50  0000 C CNN
 F 2 "" H 5650 4400 50  0000 C CNN
 F 3 "" H 5650 4400 50  0000 C CNN
@ -257,10 +257,10 @@ F 3 "" H 5650 4400 50  0000 C CNN
 	-1   0    0    -1  
 $EndComp
 $Comp
-L VFPGA33 #PWR601
+L VFPGA33 #PWR604
 U 1 1 56C8053D
 P 5550 3850
-F 0 "#PWR601" H 5550 3700 50  0001 C CNN
+F 0 "#PWR604" H 5550 3700 50  0001 C CNN
 F 1 "VFPGA33" H 5568 4024 50  0000 C CNN
 F 2 "" H 5550 3850 50  0000 C CNN
 F 3 "" H 5550 3850 50  0000 C CNN
@ -268,10 +268,10 @@ F 3 "" H 5550 3850 50  0000 C CNN
 	-1   0    0    -1  
 $EndComp
 $Comp
-L VFPGA33 #PWR603
+L VFPGA33 #PWR606
 U 1 1 56C80543
 P 5750 3750
-F 0 "#PWR603" H 5750 3600 50  0001 C CNN
+F 0 "#PWR606" H 5750 3600 50  0001 C CNN
 F 1 "VFPGA33" H 5768 3924 50  0000 C CNN
 F 2 "" H 5750 3750 50  0000 C CNN
 F 3 "" H 5750 3750 50  0000 C CNN
@ -301,10 +301,10 @@ F 3 "" H 8150 4100 50  0000 C CNN
 	-1   0    0    -1  
 $EndComp
 $Comp
-L GND #PWR613
+L GND #PWR616
 U 1 1 56C8079E
 P 8700 4400
-F 0 "#PWR613" H 8700 4150 50  0001 C CNN
+F 0 "#PWR616" H 8700 4150 50  0001 C CNN
 F 1 "GND" H 8708 4226 50  0000 C CNN
 F 2 "" H 8700 4400 50  0000 C CNN
 F 3 "" H 8700 4400 50  0000 C CNN
@ -312,10 +312,10 @@ F 3 "" H 8700 4400 50  0000 C CNN
 	-1   0    0    -1  
 $EndComp
 $Comp
-L GND #PWR612
+L GND #PWR615
 U 1 1 56C807A4
 P 8500 4400
-F 0 "#PWR612" H 8500 4150 50  0001 C CNN
+F 0 "#PWR615" H 8500 4150 50  0001 C CNN
 F 1 "GND" H 8508 4226 50  0000 C CNN
 F 2 "" H 8500 4400 50  0000 C CNN
 F 3 "" H 8500 4400 50  0000 C CNN
@ -323,10 +323,10 @@ F 3 "" H 8500 4400 50  0000 C CNN
 	-1   0    0    -1  
 $EndComp
 $Comp
-L GND #PWR610
+L GND #PWR613
 U 1 1 56C807AA
 P 8250 4400
-F 0 "#PWR610" H 8250 4150 50  0001 C CNN
+F 0 "#PWR613" H 8250 4150 50  0001 C CNN
 F 1 "GND" H 8258 4226 50  0000 C CNN
 F 2 "" H 8250 4400 50  0000 C CNN
 F 3 "" H 8250 4400 50  0000 C CNN
@ -334,10 +334,10 @@ F 3 "" H 8250 4400 50  0000 C CNN
 	-1   0    0    -1  
 $EndComp
 $Comp
-L VFPGA33 #PWR609
+L VFPGA33 #PWR612
 U 1 1 56C807B6
 P 8150 3850
-F 0 "#PWR609" H 8150 3700 50  0001 C CNN
+F 0 "#PWR612" H 8150 3700 50  0001 C CNN
 F 1 "VFPGA33" H 8168 4024 50  0000 C CNN
 F 2 "" H 8150 3850 50  0000 C CNN
 F 3 "" H 8150 3850 50  0000 C CNN
@ -345,10 +345,10 @@ F 3 "" H 8150 3850 50  0000 C CNN
 	-1   0    0    -1  
 $EndComp
 $Comp
-L VFPGA33 #PWR611
+L VFPGA33 #PWR614
 U 1 1 56C807BC
 P 8350 3750
-F 0 "#PWR611" H 8350 3600 50  0001 C CNN
+F 0 "#PWR614" H 8350 3600 50  0001 C CNN
 F 1 "VFPGA33" H 8368 3924 50  0000 C CNN
 F 2 "" H 8350 3750 50  0000 C CNN
 F 3 "" H 8350 3750 50  0000 C CNN
@ -367,10 +367,10 @@ F 3 "" H 7700 4200 50  0000 C CNN
 	-1   0    0    -1  
 $EndComp
 $Comp
-L GND #PWR606
+L GND #PWR609
 U 1 1 56C8090E
 P 7500 4400
-F 0 "#PWR606" H 7500 4150 50  0001 C CNN
+F 0 "#PWR609" H 7500 4150 50  0001 C CNN
 F 1 "GND" H 7508 4226 50  0000 C CNN
 F 2 "" H 7500 4400 50  0000 C CNN
 F 3 "" H 7500 4400 50  0000 C CNN
@ -378,10 +378,10 @@ F 3 "" H 7500 4400 50  0000 C CNN
 	-1   0    0    -1  
 $EndComp
 $Comp
-L GND #PWR608
+L GND #PWR611
 U 1 1 56C80914
 P 7700 4400
-F 0 "#PWR608" H 7700 4150 50  0001 C CNN
+F 0 "#PWR611" H 7700 4150 50  0001 C CNN
 F 1 "GND" H 7708 4226 50  0000 C CNN
 F 2 "" H 7700 4400 50  0000 C CNN
 F 3 "" H 7700 4400 50  0000 C CNN
@ -389,10 +389,10 @@ F 3 "" H 7700 4400 50  0000 C CNN
 	-1   0    0    -1  
 $EndComp
 $Comp
-L VFPGA33 #PWR607
+L VFPGA33 #PWR610
 U 1 1 56C8091F
 P 7700 3750
-F 0 "#PWR607" H 7700 3600 50  0001 C CNN
+F 0 "#PWR610" H 7700 3600 50  0001 C CNN
 F 1 "VFPGA33" H 7718 3924 50  0000 C CNN
 F 2 "" H 7700 3750 50  0000 C CNN
 F 3 "" H 7700 3750 50  0000 C CNN
@ -411,10 +411,10 @@ F 3 "" H 10300 4200 50  0000 C CNN
 	-1   0    0    -1  
 $EndComp
 $Comp
-L GND #PWR614
+L GND #PWR617
 U 1 1 56C80AD8
 P 10100 4400
-F 0 "#PWR614" H 10100 4150 50  0001 C CNN
+F 0 "#PWR617" H 10100 4150 50  0001 C CNN
 F 1 "GND" H 10108 4226 50  0000 C CNN
 F 2 "" H 10100 4400 50  0000 C CNN
 F 3 "" H 10100 4400 50  0000 C CNN
@ -422,10 +422,10 @@ F 3 "" H 10100 4400 50  0000 C CNN
 	-1   0    0    -1  
 $EndComp
 $Comp
-L GND #PWR616
+L GND #PWR619
 U 1 1 56C80ADE
 P 10300 4400
-F 0 "#PWR616" H 10300 4150 50  0001 C CNN
+F 0 "#PWR619" H 10300 4150 50  0001 C CNN
 F 1 "GND" H 10308 4226 50  0000 C CNN
 F 2 "" H 10300 4400 50  0000 C CNN
 F 3 "" H 10300 4400 50  0000 C CNN
@ -433,10 +433,10 @@ F 3 "" H 10300 4400 50  0000 C CNN
 	-1   0    0    -1  
 $EndComp
 $Comp
-L VFPGA33 #PWR615
+L VFPGA33 #PWR618
 U 1 1 56C80AE9
 P 10300 3750
-F 0 "#PWR615" H 10300 3600 50  0001 C CNN
+F 0 "#PWR618" H 10300 3600 50  0001 C CNN
 F 1 "VFPGA33" H 10318 3924 50  0000 C CNN
 F 2 "" H 10300 3750 50  0000 C CNN
 F 3 "" H 10300 3750 50  0000 C CNN
@ -549,19 +549,17 @@ Entry Wire Line
 	5750 2400 5850 2300
 Entry Wire Line
 	5750 2500 5850 2400
-Text HLabel 5600 2800 0    60   Output ~ 0
+Text HLabel 5650 3000 0    60   Output ~ 0
 AWS
-Text HLabel 5600 2700 0    60   Output ~ 0
+Text HLabel 5650 3100 0    60   Output ~ 0
 ABCK
-Text HLabel 5600 2600 0    60   Output ~ 0
+Text HLabel 5650 2600 0    60   Output ~ 0
 ADATA
-Text HLabel 5600 2500 0    60   Output ~ 0
+Text HLabel 5650 2800 0    60   Output ~ 0
 ACLK
-Text HLabel 5600 3100 0    60   Output ~ 0
+Text HLabel 5650 2700 0    60   Output ~ 0
 L3DATA
-Text HLabel 5600 3000 0    60   Output ~ 0
-L3CLK
-Text HLabel 5600 2900 0    60   Output ~ 0
+Text HLabel 5650 2500 0    60   Output ~ 0
 L3MODE
 Wire Wire Line
 	5700 2500 5650 2500
@ -720,17 +718,15 @@ Wire Wire Line
 Wire Wire Line
 	6150 3200 5850 3200
 Wire Wire Line
-	6150 3100 5850 3100
+	6150 3100 5650 3100
 Wire Wire Line
-	6150 3000 5850 3000
+	6150 3000 5650 3000
 Wire Wire Line
-	6150 2900 5850 2900
+	6150 2600 5650 2600
 Wire Wire Line
-	6150 2800 5850 2800
+	6150 2800 5650 2800
 Wire Wire Line
-	6150 2700 5850 2700
-Wire Wire Line
-	6150 2600 5850 2600
+	6150 2700 5650 2700
 Wire Wire Line
 	5800 2500 6150 2500
 Wire Wire Line
@ -823,4 +819,79 @@ Wire Wire Line
 	3100 2800 2850 2800
 Wire Wire Line
 	3100 2700 2850 2700
+Wire Wire Line
+	6150 2900 5750 2900
+$Comp
+L TCXO_DFAS11 X601
+U 1 1 56CA3014
+P 2850 5400
+F 0 "X601" H 2850 5700 70  0000 C CNN
+F 1 "TCXO_DFAS11" H 2850 5400 50  0000 C CNN
+F 2 "Crystals:Crystal_SMD_0603_4Pads" H 2850 5400 60  0001 C CNN
+F 3 "" H 2850 5400 60  0000 C CNN
+	1    2850 5400
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR603
+U 1 1 56CA301B
+P 3650 5650
+F 0 "#PWR603" H 3650 5400 50  0001 C CNN
+F 1 "GND" H 3650 5500 50  0000 C CNN
+F 2 "" H 3650 5650 60  0000 C CNN
+F 3 "" H 3650 5650 60  0000 C CNN
+	1    3650 5650
+	1    0    0    -1  
+$EndComp
+$Comp
+L VFPGA33 #PWR601
+U 1 1 56CA3022
+P 1950 5150
+F 0 "#PWR601" H 1950 5000 50  0001 C CNN
+F 1 "VFPGA33" H 1968 5324 50  0000 C CNN
+F 2 "" H 1950 5150 50  0000 C CNN
+F 3 "" H 1950 5150 50  0000 C CNN
+	1    1950 5150
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	1950 5150 1950 5300
+Wire Wire Line
+	3650 5650 3650 5550
+Wire Wire Line
+	3650 5550 3550 5550
+Wire Wire Line
+	3950 5250 3550 5250
+Text Label 3950 5250 2    60   ~ 0
+CLK_50M
+Text Label 5750 2900 0    60   ~ 0
+CLK_50M
+$Comp
+L C 100n601
+U 1 1 56CA32A6
+P 1950 5450
+F 0 "100n601" H 2065 5496 50  0000 L CNN
+F 1 "C" H 2065 5404 50  0000 L CNN
+F 2 "" H 1988 5300 50  0001 C CNN
+F 3 "" H 1950 5450 50  0000 C CNN
+	1    1950 5450
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR602
+U 1 1 56CA3322
+P 1950 5650
+F 0 "#PWR602" H 1950 5400 50  0001 C CNN
+F 1 "GND" H 1950 5500 50  0000 C CNN
+F 2 "" H 1950 5650 60  0000 C CNN
+F 3 "" H 1950 5650 60  0000 C CNN
+	1    1950 5650
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	1950 5650 1950 5600
+Wire Wire Line
+	2150 5250 1950 5250
+Connection ~ 1950 5250
+NoConn ~ 2150 5550
 $EndSCHEMATC
--- a/userif.sch
+++ b/userif.sch
@ -44,7 +44,7 @@ EELAYER 25 0
 EELAYER END
 $Descr A4 11693 8268
 encoding utf-8
-Sheet 7 9
+Sheet 9 9
 Title ""
 Date ""
 Rev ""
@ -393,11 +393,7 @@ RGBLED2
 Wire Wire Line
 	9800 2450 9850 2450
 Wire Wire Line
-	9850 2450 9850 2650
-Wire Wire Line
-	9850 2650 9850 2850
-Wire Wire Line
-	9850 2850 9850 3000
+	9850 2450 9850 3000
 Wire Wire Line
 	9800 2850 9850 2850
 Connection ~ 9850 2850
@ -405,10 +401,10 @@ Wire Wire Line
 	9800 2650 9850 2650
 Connection ~ 9850 2650
 $Comp
-L GND #PWR?
+L GND #PWR709
 U 1 1 56C8F2B5
 P 9850 3000
-F 0 "#PWR?" H 9850 2750 50  0001 C CNN
+F 0 "#PWR709" H 9850 2750 50  0001 C CNN
 F 1 "GND" H 9858 2826 50  0000 C CNN
 F 2 "" H 9850 3000 50  0000 C CNN
 F 3 "" H 9850 3000 50  0000 C CNN
@ -416,34 +412,34 @@ F 3 "" H 9850 3000 50  0000 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L R R?
+L R R701
 U 1 1 56C8FF13
 P 9200 2450
-F 0 "R?" V 9100 2450 50  0000 C CNN
+F 0 "R701" V 9100 2450 50  0000 C CNN
 F 1 "220" V 9200 2450 50  0000 C CNN
-F 2 "" V 9130 2450 50  0000 C CNN
+F 2 "" V 9130 2450 50  0001 C CNN
 F 3 "" H 9200 2450 50  0000 C CNN
 	1    9200 2450
 	0    1    1    0   
 $EndComp
 $Comp
-L R R?
+L R R702
 U 1 1 56C90060
 P 9200 2650
-F 0 "R?" V 9100 2650 50  0000 C CNN
+F 0 "R702" V 9100 2650 50  0000 C CNN
 F 1 "220" V 9200 2650 50  0000 C CNN
-F 2 "" V 9130 2650 50  0000 C CNN
+F 2 "" V 9130 2650 50  0001 C CNN
 F 3 "" H 9200 2650 50  0000 C CNN
 	1    9200 2650
 	0    1    1    0   
 $EndComp
 $Comp
-L R R?
+L R R703
 U 1 1 56C90098
 P 9200 2850
-F 0 "R?" V 9100 2850 50  0000 C CNN
+F 0 "R703" V 9100 2850 50  0000 C CNN
 F 1 "220" V 9200 2850 50  0000 C CNN
-F 2 "" V 9130 2850 50  0000 C CNN
+F 2 "" V 9130 2850 50  0001 C CNN
 F 3 "" H 9200 2850 50  0000 C CNN
 	1    9200 2850
 	0    1    1    0   
@ -454,40 +450,34 @@ Wire Wire Line
 	9400 2650 9350 2650
 Wire Wire Line
 	9350 2450 9400 2450
-$Comp
-L SW_PUSH SW?
-U 1 1 56C90B91
-P 9500 3550
-F 0 "SW?" H 9500 3806 50  0000 C CNN
-F 1 "DOWN" H 9500 3714 50  0000 C CNN
-F 2 "smd:Tactile_Switch" H 9500 3550 50  0001 C CNN
-F 3 "" H 9500 3550 50  0000 C CNN
-	1    9500 3550
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	9800 3550 9850 3550
-Wire Wire Line
-	9850 3550 9850 3700
-$Comp
-L GND #PWR?
-U 1 1 56C90DD8
-P 9850 3700
-F 0 "#PWR?" H 9850 3450 50  0001 C CNN
-F 1 "GND" H 9858 3526 50  0000 C CNN
-F 2 "" H 9850 3700 50  0000 C CNN
-F 3 "" H 9850 3700 50  0000 C CNN
-	1    9850 3700
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	9200 3550 8600 3550
-Text Label 8600 3550 0    60   ~ 0
-BTN_STBY
 Text HLabel 2650 5500 0    60   Input ~ 0
 JTMS
 Text HLabel 2650 5600 0    60   Input ~ 0
 JTCK
 Text HLabel 2650 5700 0    60   Input ~ 0
 JTDI
+Wire Wire Line
+	3100 4600 2550 4600
+Text HLabel 2550 4500 0    60   Input ~ 0
+SYS_VOLTAGE
+Text HLabel 2550 4700 0    60   Input ~ 0
+CHG_ACTIVE_N
+Text HLabel 2550 4900 0    60   Output ~ 0
+CHARGE_ENABLE
+Text HLabel 2550 4800 0    60   Output ~ 0
+FPGA_ENABLE_N
+Text HLabel 2550 4600 0    60   Input ~ 0
+USB_PRESENT_N
+Wire Wire Line
+	2550 4500 3100 4500
+Wire Wire Line
+	2550 4700 3100 4700
+Wire Wire Line
+	3100 4800 2550 4800
+Wire Wire Line
+	2550 4900 3100 4900
+Wire Wire Line
+	3100 5400 2650 5400
+Text HLabel 2650 5400 0    60   Input ~ 0
+SDCARD_DETECT
 $EndSCHEMATC