electronics/fpgna
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This commit is contained in:
Markus Koch 2016-03-05 22:27:05 +01:00
parent bc439332a0
commit a19f63603c
9 changed files with 3524 additions and 3585 deletions
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54
FSMC.sch
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@ -193,10 +193,10 @@ F 3 "" H 5950 6900 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GND #PWR404
L GND #PWR405
U 1 1 56C67B1F
P 5400 7200
F 0 "#PWR404" H 5400 6950 50 0001 C CNN
F 0 "#PWR405" H 5400 6950 50 0001 C CNN
F 1 "GND" H 5408 7026 50 0000 C CNN
F 2 "" H 5400 7200 50 0000 C CNN
F 3 "" H 5400 7200 50 0000 C CNN
@ -204,10 +204,10 @@ F 3 "" H 5400 7200 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GND #PWR405
L GND #PWR406
U 1 1 56C67B55
P 5600 7200
F 0 "#PWR405" H 5600 6950 50 0001 C CNN
F 0 "#PWR406" H 5600 6950 50 0001 C CNN
F 1 "GND" H 5608 7026 50 0000 C CNN
F 2 "" H 5600 7200 50 0000 C CNN
F 3 "" H 5600 7200 50 0000 C CNN
@ -215,10 +215,10 @@ F 3 "" H 5600 7200 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GND #PWR407
L GND #PWR408
U 1 1 56C67C80
P 5850 7200
F 0 "#PWR407" H 5850 6950 50 0001 C CNN
F 0 "#PWR408" H 5850 6950 50 0001 C CNN
F 1 "GND" H 5858 7026 50 0000 C CNN
F 2 "" H 5850 7200 50 0000 C CNN
F 3 "" H 5850 7200 50 0000 C CNN
@ -237,10 +237,10 @@ F 3 "" H 3800 7000 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GND #PWR403
L GND #PWR404
U 1 1 56C680A6
P 4000 7200
F 0 "#PWR403" H 4000 6950 50 0001 C CNN
F 0 "#PWR404" H 4000 6950 50 0001 C CNN
F 1 "GND" H 4008 7026 50 0000 C CNN
F 2 "" H 4000 7200 50 0000 C CNN
F 3 "" H 4000 7200 50 0000 C CNN
@ -248,10 +248,10 @@ F 3 "" H 4000 7200 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GND #PWR402
L GND #PWR403
U 1 1 56C6815E
P 3800 7200
F 0 "#PWR402" H 3800 6950 50 0001 C CNN
F 0 "#PWR403" H 3800 6950 50 0001 C CNN
F 1 "GND" H 3808 7026 50 0000 C CNN
F 2 "" H 3800 7200 50 0000 C CNN
F 3 "" H 3800 7200 50 0000 C CNN
@ -259,10 +259,10 @@ F 3 "" H 3800 7200 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L VFPGA33 #PWR408
L VFPGA33 #PWR409
U 1 1 56C6B01D
P 5950 6650
F 0 "#PWR408" H 5950 6500 50 0001 C CNN
F 0 "#PWR409" H 5950 6500 50 0001 C CNN
F 1 "VFPGA33" H 5950 6790 50 0000 C CNN
F 2 "" H 5950 6650 50 0000 C CNN
F 3 "" H 5950 6650 50 0000 C CNN
@ -270,10 +270,10 @@ F 3 "" H 5950 6650 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L VFPGA33 #PWR406
L VFPGA33 #PWR407
U 1 1 56C6B114
P 5750 6550
F 0 "#PWR406" H 5750 6400 50 0001 C CNN
F 0 "#PWR407" H 5750 6400 50 0001 C CNN
F 1 "VFPGA33" H 5750 6690 50 0000 C CNN
F 2 "" H 5750 6550 50 0000 C CNN
F 3 "" H 5750 6550 50 0000 C CNN
@ -281,10 +281,10 @@ F 3 "" H 5750 6550 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L VFPGA33 #PWR401
L VFPGA33 #PWR402
U 1 1 56C6B644
P 3800 6550
F 0 "#PWR401" H 3800 6400 50 0001 C CNN
F 0 "#PWR402" H 3800 6400 50 0001 C CNN
F 1 "VFPGA33" H 3800 6690 50 0000 C CNN
F 2 "" H 3800 6550 50 0000 C CNN
F 3 "" H 3800 6550 50 0000 C CNN
@ -534,9 +534,6 @@ T_DIN
NoConn ~ 2200 1750
NoConn ~ 2200 1650
NoConn ~ 2200 1550
NoConn ~ 2200 1450
NoConn ~ 2200 1150
NoConn ~ 2200 1250
NoConn ~ 2200 750
NoConn ~ 2200 650
Wire Wire Line
@ -547,4 +544,23 @@ Wire Wire Line
5350 6300 5700 6300
Text Label 5700 6300 2 60 ~ 0
ADV_N
$Comp
L VSTM33 #PWR401
U 1 1 56DBD022
P 2950 1350
F 0 "#PWR401" H 2950 1200 50 0001 C CNN
F 1 "VSTM33" H 2968 1524 50 0000 C CNN
F 2 "" H 2950 1350 50 0000 C CNN
F 3 "" H 2950 1350 50 0000 C CNN
1 2950 1350
1 0 0 -1
$EndComp
Wire Wire Line
2950 1350 2950 1450
Text Notes 3000 1450 0 60 ~ 0
Need to route Power\nthrough this pin
NoConn ~ 2200 1150
Wire Wire Line
2950 1450 2200 1450
NoConn ~ 2200 1250
$EndSCHEMATC

32
audio.sch
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@ -278,17 +278,6 @@ AOUTR
Text Label 4200 2900 0 60 ~ 0
DACVREF
$Comp
L VSTM33 #PWR808
U 1 1 56CB0E9B
P 6150 2950
F 0 "#PWR808" H 6150 2800 50 0001 C CNN
F 1 "VSTM33" H 6168 3124 50 0000 C CNN
F 2 "" H 6150 2950 50 0000 C CNN
F 3 "" H 6150 2950 50 0000 C CNN
1 6150 2950
1 0 0 -1
$EndComp
$Comp
L R R801
U 1 1 56CC26E6
P 4100 2350
@ -459,17 +448,28 @@ F 3 "" H 3900 3250 50 0000 C CNN
1 3900 3250
1 0 0 -1
$EndComp
Text Label 4250 2350 0 60 ~ 0
APPSEL
$Comp
L VSTM33 #PWR802
U 1 1 56D95CF4
L VFPGA33 #PWR808
U 1 1 56DB2570
P 6150 2950
F 0 "#PWR808" H 6150 2800 50 0001 C CNN
F 1 "VFPGA33" H 6168 3124 50 0000 C CNN
F 2 "" H 6150 2950 50 0000 C CNN
F 3 "" H 6150 2950 50 0000 C CNN
1 6150 2950
1 0 0 -1
$EndComp
$Comp
L VFPGA33 #PWR802
U 1 1 56DB2EA0
P 3900 2850
F 0 "#PWR802" H 3900 2700 50 0001 C CNN
F 1 "VSTM33" H 3918 3024 50 0000 C CNN
F 1 "VFPGA33" H 3918 3024 50 0000 C CNN
F 2 "" H 3900 2850 50 0000 C CNN
F 3 "" H 3900 2850 50 0000 C CNN
1 3900 2850
1 0 0 -1
$EndComp
Text Label 4250 2350 0 60 ~ 0
APPSEL
$EndSCHEMATC

75
debug.sch
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@ -57,12 +57,12 @@ $EndDescr
$Comp
L Lattice-JTAG P302
U 1 1 56338EF4
P 3400 1700
F 0 "P302" H 3200 1350 60 0000 C CNN
F 1 "Lattice-JTAG" H 3400 2050 60 0000 C CNN
F 2 "Pin_Headers:Pin_Header_Angled_2x05" H 3400 1700 60 0001 C CNN
F 3 "" H 3400 1700 60 0000 C CNN
1 3400 1700
P 3600 1700
F 0 "P302" H 3400 1350 60 0000 C CNN
F 1 "Lattice-JTAG" H 3600 2050 60 0000 C CNN
F 2 "Pin_Headers:Pin_Header_Angled_2x05" H 3600 1700 60 0001 C CNN
F 3 "" H 3600 1700 60 0000 C CNN
1 3600 1700
1 0 0 1
$EndComp
$Comp
@ -103,12 +103,12 @@ $EndComp
$Comp
L GND #PWR307
U 1 1 568DA1F8
P 4100 2000
F 0 "#PWR307" H 4100 1750 50 0001 C CNN
F 1 "GND" H 4100 1850 50 0000 C CNN
F 2 "" H 4100 2000 60 0000 C CNN
F 3 "" H 4100 2000 60 0000 C CNN
1 4100 2000
P 4300 2000
F 0 "#PWR307" H 4300 1750 50 0001 C CNN
F 1 "GND" H 4300 1850 50 0000 C CNN
F 2 "" H 4300 2000 60 0000 C CNN
F 3 "" H 4300 2000 60 0000 C CNN
1 4300 2000
1 0 0 -1
$EndComp
$Comp
@ -208,9 +208,8 @@ Text Label 2550 1700 0 60 ~ 0
FTDI
Text Label 2550 1600 0 60 ~ 0
FTDO
NoConn ~ 3850 1500
NoConn ~ 3850 1600
NoConn ~ 2950 1500
NoConn ~ 4050 1500
NoConn ~ 4050 1600
Text Label 4500 2950 0 60 ~ 0
JTCK
Text Label 4500 3050 0 60 ~ 0
@ -239,12 +238,12 @@ $EndComp
$Comp
L VFPGA33 #PWR306
U 1 1 56CA6C73
P 4100 1500
F 0 "#PWR306" H 4100 1350 50 0001 C CNN
F 1 "VFPGA33" H 4118 1674 50 0000 C CNN
F 2 "" H 4100 1500 50 0000 C CNN
F 3 "" H 4100 1500 50 0000 C CNN
1 4100 1500
P 4300 1500
F 0 "#PWR306" H 4300 1350 50 0001 C CNN
F 1 "VFPGA33" H 4318 1674 50 0000 C CNN
F 2 "" H 4300 1500 50 0000 C CNN
F 3 "" H 4300 1500 50 0000 C CNN
1 4300 1500
1 0 0 -1
$EndComp
$Comp
@ -326,13 +325,13 @@ F 3 "" H 2200 4100 50 0000 C CNN
1 0 0 -1
$EndComp
Wire Wire Line
2950 1900 2500 1900
3150 1900 2500 1900
Wire Wire Line
2500 1800 2950 1800
2500 1800 3150 1800
Wire Wire Line
2500 1700 2950 1700
2500 1700 3150 1700
Wire Wire Line
2950 1600 2500 1600
3150 1600 2500 1600
Wire Wire Line
2500 900 2500 1400
Wire Wire Line
@ -343,16 +342,16 @@ Connection ~ 2500 950
Wire Wire Line
2700 1300 2700 1350
Wire Wire Line
4100 1500 4100 1700
4300 1500 4300 1700
Wire Wire Line
4100 1700 3850 1700
4300 1700 4050 1700
Wire Wire Line
4100 1800 4100 2000
4300 1800 4300 2000
Wire Wire Line
4100 1900 3850 1900
4300 1900 4050 1900
Wire Wire Line
3850 1800 4100 1800
Connection ~ 4100 1900
4050 1800 4300 1800
Connection ~ 4300 1900
Wire Wire Line
1750 3000 2250 3000
Wire Wire Line
@ -401,11 +400,11 @@ Wire Wire Line
Wire Wire Line
2450 3450 1850 3450
Wire Wire Line
2400 4650 1550 4650
1550 4650 2400 4650
Wire Wire Line
2400 4750 1550 4750
1550 4750 2400 4750
Wire Wire Line
2400 4850 1550 4850
1550 4850 2400 4850
Wire Wire Line
2350 4550 2350 4650
Connection ~ 2350 4650
@ -416,12 +415,16 @@ Wire Wire Line
2050 4550 2050 4850
Connection ~ 2050 4850
Wire Wire Line
2350 4250 2350 4200
2350 4200 2350 4250
Wire Wire Line
2350 4200 2050 4200
2050 4200 2350 4200
Wire Wire Line
2050 4200 2050 4250
Wire Wire Line
2200 4100 2200 4250
Connection ~ 2200 4200
Text HLabel 3100 1500 0 60 Output ~ 0
FRST
Wire Wire Line
3150 1500 3100 1500
$EndSCHEMATC

15
display.sch
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@ -474,17 +474,8 @@ Text HLabel 4600 3100 0 60 Output ~ 0
T_BUSY
Text HLabel 4600 3200 0 60 Output ~ 0
T_IRQ
Text HLabel 1300 4850 0 60 Input ~ 0
FRST
Wire Wire Line
1350 4850 1050 4850
$Comp
L TEST_1P W501
U 1 1 56CC3477
P 1050 4850
F 0 "W501" H 1108 4970 50 0000 L CNN
F 1 "PR24A" H 1108 4878 50 0000 L CNN
F 2 "SMD_Packages:1Pin" H 1250 4850 50 0001 C CNN
F 3 "" H 1250 4850 50 0000 C CNN
1 1050 4850
1 0 0 -1
$EndComp
1350 4850 1300 4850
$EndSCHEMATC

13
fpgna-cache.lib
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@ -1014,19 +1014,6 @@ X VCC 4 -700 150 300 R 50 50 1 1 W
ENDDRAW
ENDDEF
#
# TEST_1P
#
DEF TEST_1P W 0 30 N N 1 F N
F0 "W" 0 270 50 H V C CNN
F1 "TEST_1P" 0 200 50 H V C CNN
F2 "" 200 0 50 H V C CNN
F3 "" 200 0 50 H V C CNN
DRAW
C 0 130 30 0 1 0 N
X 1 1 0 0 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# UDA1330ATS
#
DEF UDA1330ATS U 0 40 Y Y 4 L N

5399
fpgna.kicad_pcb
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File diff suppressed because it is too large Load Diff

1390
fpgna.net
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File diff suppressed because it is too large Load Diff

12
fpgna.sch
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@ -77,6 +77,7 @@ F4 "JTDO" I R 2750 4200 60
F5 "JTCK" O R 2750 3650 60
F6 "JRST_N" O R 2750 4300 60
F7 "BOOT1" O R 2750 4400 60
F8 "FRST" O R 2750 4000 60
$EndSheet
$Sheet
S 5900 3050 2050 2150
@ -107,6 +108,7 @@ F4 "T_DIN" I L 8100 3400 60
F5 "T_DOUT" O L 8100 3500 60
F6 "T_BUSY" O R 9850 3300 60
F7 "T_IRQ" O R 9850 3200 60
F8 "FRST" I R 9850 3500 60
$EndSheet
$Sheet
S 8100 4150 1350 800
@ -254,4 +256,14 @@ Wire Wire Line
1650 4700 1650 2850
Wire Wire Line
1650 2850 1750 2850
Wire Wire Line
9850 3500 10350 3500
Wire Wire Line
10350 3500 10350 5300
Wire Wire Line
10350 5300 2850 5300
Wire Wire Line
2850 5300 2850 4000
Wire Wire Line
2850 4000 2750 4000
$EndSCHEMATC

119
power.sch
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@ -475,10 +475,10 @@ F 3 "" H 7050 1200 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L VBAT #PWR254
L VBAT #PWR253
U 1 1 56C1ED5D
P 9300 2750
F 0 "#PWR254" H 9300 2600 50 0001 C CNN
F 0 "#PWR253" H 9300 2600 50 0001 C CNN
F 1 "VBAT" H 9300 2890 50 0000 C CNN
F 2 "" H 9300 2750 50 0000 C CNN
F 3 "" H 9300 2750 50 0000 C CNN
@ -486,10 +486,10 @@ F 3 "" H 9300 2750 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L VUSB #PWR247
L VUSB #PWR246
U 1 1 56C1F811
P 8200 2750
F 0 "#PWR247" H 8200 2600 50 0001 C CNN
F 0 "#PWR246" H 8200 2600 50 0001 C CNN
F 1 "VUSB" H 8200 2890 50 0000 C CNN
F 2 "" H 8200 2750 50 0000 C CNN
F 3 "" H 8200 2750 50 0000 C CNN
@ -513,10 +513,10 @@ F 4 "TODO: Verify pinout" H 9877 3150 60 0000 L CNN "TODO"
1 0 0 1
$EndComp
$Comp
L VBAT #PWR257
L VBAT #PWR256
U 1 1 56C23113
P 9550 2750
F 0 "#PWR257" H 9550 2600 50 0001 C CNN
F 0 "#PWR256" H 9550 2600 50 0001 C CNN
F 1 "VBAT" H 9550 2890 50 0000 C CNN
F 2 "" H 9550 2750 50 0000 C CNN
F 3 "" H 9550 2750 50 0000 C CNN
@ -524,10 +524,10 @@ F 3 "" H 9550 2750 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GND #PWR248
L GND #PWR247
U 1 1 56C23816
P 8200 3950
F 0 "#PWR248" H 8200 3700 50 0001 C CNN
F 0 "#PWR247" H 8200 3700 50 0001 C CNN
F 1 "GND" H 8200 3800 50 0000 C CNN
F 2 "" H 8200 3950 60 0000 C CNN
F 3 "" H 8200 3950 60 0000 C CNN
@ -535,10 +535,10 @@ F 3 "" H 8200 3950 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GND #PWR258
L GND #PWR257
U 1 1 56C23E07
P 9550 3400
F 0 "#PWR258" H 9550 3150 50 0001 C CNN
F 0 "#PWR257" H 9550 3150 50 0001 C CNN
F 1 "GND" H 9550 3250 50 0000 C CNN
F 2 "" H 9550 3400 60 0000 C CNN
F 3 "" H 9550 3400 60 0000 C CNN
@ -546,10 +546,10 @@ F 3 "" H 9550 3400 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L R R212
L R R210
U 1 1 56C24FD6
P 9300 3700
F 0 "R212" V 9380 3700 50 0000 C CNN
F 0 "R210" V 9380 3700 50 0000 C CNN
F 1 "2.2k" V 9300 3700 50 0000 C CNN
F 2 "Resistors_SMD:R_0603" V 9230 3700 30 0001 C CNN
F 3 "" H 9300 3700 30 0000 C CNN
@ -558,10 +558,10 @@ F 4 "TODO: Check value" H 9850 3700 60 0000 C CNN "TODO"
1 0 0 -1
$EndComp
$Comp
L GND #PWR255
L GND #PWR254
U 1 1 56C253CE
P 9300 4500
F 0 "#PWR255" H 9300 4250 50 0001 C CNN
F 0 "#PWR254" H 9300 4250 50 0001 C CNN
F 1 "GND" H 9300 4350 50 0000 C CNN
F 2 "" H 9300 4500 60 0000 C CNN
F 3 "" H 9300 4500 60 0000 C CNN
@ -569,10 +569,10 @@ F 3 "" H 9300 4500 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L VUSB #PWR252
L VUSB #PWR251
U 1 1 56C2BB98
P 8600 950
F 0 "#PWR252" H 8600 800 50 0001 C CNN
F 0 "#PWR251" H 8600 800 50 0001 C CNN
F 1 "VUSB" H 8600 1090 50 0000 C CNN
F 2 "" H 8600 950 50 0000 C CNN
F 3 "" H 8600 950 50 0000 C CNN
@ -580,10 +580,10 @@ F 3 "" H 8600 950 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L VBAT #PWR251
L VBAT #PWR250
U 1 1 56C2D4CD
P 8400 950
F 0 "#PWR251" H 8400 800 50 0001 C CNN
F 0 "#PWR250" H 8400 800 50 0001 C CNN
F 1 "VBAT" H 8400 1090 50 0000 C CNN
F 2 "" H 8400 950 50 0000 C CNN
F 3 "" H 8400 950 50 0000 C CNN
@ -602,10 +602,10 @@ F 3 "" H 8900 1500 50 0000 C CNN
0 -1 -1 0
$EndComp
$Comp
L R R211
L R R209
U 1 1 56C2F66F
P 8900 1950
F 0 "R211" V 8980 1950 50 0000 C CNN
F 0 "R209" V 8980 1950 50 0000 C CNN
F 1 "10k" V 8900 1950 50 0000 C CNN
F 2 "Resistors_SMD:R_0603" V 8830 1950 30 0001 C CNN
F 3 "" H 8900 1950 30 0000 C CNN
@ -613,10 +613,10 @@ F 3 "" H 8900 1950 30 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GND #PWR253
L GND #PWR252
U 1 1 56C307A1
P 8900 2150
F 0 "#PWR253" H 8900 1900 50 0001 C CNN
F 0 "#PWR252" H 8900 1900 50 0001 C CNN
F 1 "GND" H 8900 2000 50 0000 C CNN
F 2 "" H 8900 2150 60 0000 C CNN
F 3 "" H 8900 2150 60 0000 C CNN
@ -646,10 +646,10 @@ F 3 "" H 1000 1000 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L VSYS #PWR256
L VSYS #PWR255
U 1 1 56C39AFF
P 9350 950
F 0 "#PWR256" H 9350 800 50 0001 C CNN
F 0 "#PWR255" H 9350 800 50 0001 C CNN
F 1 "VSYS" H 9350 1090 50 0000 C CNN
F 2 "" H 9350 950 50 0000 C CNN
F 3 "" H 9350 950 50 0000 C CNN
@ -657,10 +657,10 @@ F 3 "" H 9350 950 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L R R213
L R R211
U 1 1 56C590A7
P 9650 4300
F 0 "R213" V 9730 4300 50 0000 C CNN
F 0 "R211" V 9730 4300 50 0000 C CNN
F 1 "10k" V 9650 4300 50 0000 C CNN
F 2 "Resistors_SMD:R_0603" V 9580 4300 30 0001 C CNN
F 3 "" H 9650 4300 30 0000 C CNN
@ -670,10 +670,10 @@ $EndComp
Text HLabel 9800 4100 2 60 Input ~ 0
CHARGE_ENABLE
$Comp
L R R214
L R R212
U 1 1 56C1FB0E
P 9700 1150
F 0 "R214" V 9780 1150 50 0000 C CNN
F 0 "R212" V 9780 1150 50 0000 C CNN
F 1 "10k" V 9700 1150 50 0000 C CNN
F 2 "Resistors_SMD:R_0603" V 9630 1150 30 0001 C CNN
F 3 "" H 9700 1150 30 0000 C CNN
@ -681,10 +681,10 @@ F 3 "" H 9700 1150 30 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L R R215
L R R213
U 1 1 56C20160
P 9700 1550
F 0 "R215" V 9780 1550 50 0000 C CNN
F 0 "R213" V 9780 1550 50 0000 C CNN
F 1 "10k" V 9700 1550 50 0000 C CNN
F 2 "Resistors_SMD:R_0603" V 9630 1550 30 0001 C CNN
F 3 "" H 9700 1550 30 0000 C CNN
@ -692,10 +692,10 @@ F 3 "" H 9700 1550 30 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L VSYS #PWR260
L VSYS #PWR259
U 1 1 56C208D6
P 9700 950
F 0 "#PWR260" H 9700 800 50 0001 C CNN
F 0 "#PWR259" H 9700 800 50 0001 C CNN
F 1 "VSYS" H 9700 1090 50 0000 C CNN
F 2 "" H 9700 950 50 0000 C CNN
F 3 "" H 9700 950 50 0000 C CNN
@ -703,10 +703,10 @@ F 3 "" H 9700 950 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GND #PWR261
L GND #PWR260
U 1 1 56C20CEB
P 9700 1800
F 0 "#PWR261" H 9700 1550 50 0001 C CNN
F 0 "#PWR260" H 9700 1550 50 0001 C CNN
F 1 "GND" H 9700 1650 50 0000 C CNN
F 2 "" H 9700 1800 60 0000 C CNN
F 3 "" H 9700 1800 60 0000 C CNN
@ -719,7 +719,7 @@ U 1 1 56C21EC8
P 9900 1550
F 0 "D203" V 9854 1619 50 0000 L CNN
F 1 "3.3V" V 9946 1619 50 0000 L CNN
F 2 "Diodes_SMD:MELF_Standard" H 9900 1550 50 0001 C CNN
F 2 "Diodes_SMD:MiniMELF_Standard" H 9900 1550 50 0001 C CNN
F 3 "" H 9900 1550 50 0000 C CNN
1 9900 1550
0 1 1 0
@ -1935,10 +1935,10 @@ Wire Wire Line
8100 6150 8500 6150
Connection ~ 8300 6150
$Comp
L GND #PWR250
L GND #PWR249
U 1 1 56CA9ED8
P 8300 6200
F 0 "#PWR250" H 8300 5950 50 0001 C CNN
F 0 "#PWR249" H 8300 5950 50 0001 C CNN
F 1 "GND" H 8300 6050 50 0000 C CNN
F 2 "" H 8300 6200 60 0000 C CNN
F 3 "" H 8300 6200 60 0000 C CNN
@ -1950,10 +1950,10 @@ Wire Wire Line
Wire Wire Line
8300 5850 8300 5800
$Comp
L VFPGA33 #PWR249
L VFPGA33 #PWR248
U 1 1 56CAA2F9
P 8300 5800
F 0 "#PWR249" H 8300 5650 50 0001 C CNN
F 0 "#PWR248" H 8300 5650 50 0001 C CNN
F 1 "VFPGA33" H 8318 5974 50 0000 C CNN
F 2 "" H 8300 5800 50 0000 C CNN
F 3 "" H 8300 5800 50 0000 C CNN
@ -1985,10 +1985,10 @@ Wire Wire Line
Wire Wire Line
9600 4100 9800 4100
$Comp
L GND #PWR259
L GND #PWR258
U 1 1 56CAF6AE
P 9650 4500
F 0 "#PWR259" H 9650 4250 50 0001 C CNN
F 0 "#PWR258" H 9650 4250 50 0001 C CNN
F 1 "GND" H 9650 4350 50 0000 C CNN
F 2 "" H 9650 4500 60 0000 C CNN
F 3 "" H 9650 4500 60 0000 C CNN
@ -2129,4 +2129,41 @@ Text Label 9550 3250 0 60 ~ 0
B+
Text Notes 7050 3300 0 60 ~ 0
These need SW Pullup
$Comp
L R R214
U 1 1 56DB2A43
P 9950 5900
F 0 "R214" H 10020 5946 50 0000 L CNN
F 1 "0" H 10020 5854 50 0000 L CNN
F 2 "Resistors_SMD:R_0603" V 9880 5900 50 0001 C CNN
F 3 "" H 9950 5900 50 0000 C CNN
1 9950 5900
1 0 0 -1
$EndComp
$Comp
L VFPGA33 #PWR261
U 1 1 56DB2F63
P 9950 5650
F 0 "#PWR261" H 9950 5500 50 0001 C CNN
F 1 "VFPGA33" H 9968 5824 50 0000 C CNN
F 2 "" H 9950 5650 50 0000 C CNN
F 3 "" H 9950 5650 50 0000 C CNN
1 9950 5650
1 0 0 -1
$EndComp
Wire Wire Line
9950 5650 9950 5750
Wire Wire Line
9950 6050 9950 6100
Wire Wire Line
9950 6100 9850 6100
Wire Wire Line
9850 6100 9850 5700
Wire Wire Line
9850 5700 9950 5700
Connection ~ 9950 5700
Text Label 7900 1050 0 60 ~ 0
USHLD
Text Label 4800 7000 0 60 ~ 0
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