From ac26402b8e1b95785ba0a6e43a99c3b5e98e3767 Mon Sep 17 00:00:00 2001 From: Makise Kurisu Date: Mon, 22 Feb 2016 08:53:49 +0100 Subject: [PATCH] Fixed audio buffer, fixed a few NC errors --- FSMC.sch | 54 +- audio.sch | 179 +- debug.sch | 32 +- display.sch | 28 +- fpgna-cache.lib | 38 +- fpgna.kicad_pcb | 4604 +++++++++++++++++++++++------------------------ fpgna.net | 1780 +++++++++--------- fpgna.sch | 8 + power.sch | 451 ++--- sdcard.sch | 32 +- sdram.sch | 80 +- userif.sch | 36 +- 12 files changed, 3624 insertions(+), 3698 deletions(-) diff --git a/FSMC.sch b/FSMC.sch index 4c82302..38b92ae 100644 --- a/FSMC.sch +++ b/FSMC.sch @@ -193,10 +193,10 @@ F 3 "" H 5950 6900 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR404 +L GND #PWR70 U 1 1 56C67B1F P 5400 7200 -F 0 "#PWR404" H 5400 6950 50 0001 C CNN +F 0 "#PWR70" H 5400 6950 50 0001 C CNN F 1 "GND" H 5408 7026 50 0000 C CNN F 2 "" H 5400 7200 50 0000 C CNN F 3 "" H 5400 7200 50 0000 C CNN @@ -204,10 +204,10 @@ F 3 "" H 5400 7200 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR405 +L GND #PWR71 U 1 1 56C67B55 P 5600 7200 -F 0 "#PWR405" H 5600 6950 50 0001 C CNN +F 0 "#PWR71" H 5600 6950 50 0001 C CNN F 1 "GND" H 5608 7026 50 0000 C CNN F 2 "" H 5600 7200 50 0000 C CNN F 3 "" H 5600 7200 50 0000 C CNN @@ -215,10 +215,10 @@ F 3 "" H 5600 7200 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR407 +L GND #PWR73 U 1 1 56C67C80 P 5850 7200 -F 0 "#PWR407" H 5850 6950 50 0001 C CNN +F 0 "#PWR73" H 5850 6950 50 0001 C CNN F 1 "GND" H 5858 7026 50 0000 C CNN F 2 "" H 5850 7200 50 0000 C CNN F 3 "" H 5850 7200 50 0000 C CNN @@ -237,10 +237,10 @@ F 3 "" H 3800 7000 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR403 +L GND #PWR69 U 1 1 56C680A6 P 4000 7200 -F 0 "#PWR403" H 4000 6950 50 0001 C CNN +F 0 "#PWR69" H 4000 6950 50 0001 C CNN F 1 "GND" H 4008 7026 50 0000 C CNN F 2 "" H 4000 7200 50 0000 C CNN F 3 "" H 4000 7200 50 0000 C CNN @@ -248,10 +248,10 @@ F 3 "" H 4000 7200 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR402 +L GND #PWR68 U 1 1 56C6815E P 3800 7200 -F 0 "#PWR402" H 3800 6950 50 0001 C CNN +F 0 "#PWR68" H 3800 6950 50 0001 C CNN F 1 "GND" H 3808 7026 50 0000 C CNN F 2 "" H 3800 7200 50 0000 C CNN F 3 "" H 3800 7200 50 0000 C CNN @@ -259,10 +259,10 @@ F 3 "" H 3800 7200 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VFPGA33 #PWR408 +L VFPGA33 #PWR74 U 1 1 56C6B01D P 5950 6650 -F 0 "#PWR408" H 5950 6500 50 0001 C CNN +F 0 "#PWR74" H 5950 6500 50 0001 C CNN F 1 "VFPGA33" H 5950 6790 50 0000 C CNN F 2 "" H 5950 6650 50 0000 C CNN F 3 "" H 5950 6650 50 0000 C CNN @@ -270,10 +270,10 @@ F 3 "" H 5950 6650 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VFPGA33 #PWR406 +L VFPGA33 #PWR72 U 1 1 56C6B114 P 5750 6550 -F 0 "#PWR406" H 5750 6400 50 0001 C CNN +F 0 "#PWR72" H 5750 6400 50 0001 C CNN F 1 "VFPGA33" H 5750 6690 50 0000 C CNN F 2 "" H 5750 6550 50 0000 C CNN F 3 "" H 5750 6550 50 0000 C CNN @@ -281,10 +281,10 @@ F 3 "" H 5750 6550 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VFPGA33 #PWR401 +L VFPGA33 #PWR67 U 1 1 56C6B644 P 3800 6550 -F 0 "#PWR401" H 3800 6400 50 0001 C CNN +F 0 "#PWR67" H 3800 6400 50 0001 C CNN F 1 "VFPGA33" H 3800 6690 50 0000 C CNN F 2 "" H 3800 6550 50 0000 C CNN F 3 "" H 3800 6550 50 0000 C CNN @@ -331,13 +331,13 @@ Text Label 5700 5100 2 60 ~ 0 DA12 Text Label 3750 4900 0 60 ~ 0 CLK -Text Label 5700 6000 2 60 ~ 0 +Text Label 3750 4800 0 60 ~ 0 OE_N -Text Label 5700 6100 2 60 ~ 0 +Text Label 5700 6000 2 60 ~ 0 WE_N -Text Label 5700 6200 2 60 ~ 0 +Text Label 5700 6100 2 60 ~ 0 WAIT_N -Text Label 5700 6300 2 60 ~ 0 +Text Label 5700 6200 2 60 ~ 0 E1_N Wire Wire Line 2200 4250 2700 4250 @@ -477,14 +477,14 @@ Wire Wire Line 5350 5800 5700 5800 Wire Wire Line 5350 5900 5700 5900 +Wire Wire Line + 3750 4800 4050 4800 Wire Wire Line 5350 6000 5700 6000 Wire Wire Line 5350 6100 5700 6100 Wire Wire Line 5350 6200 5700 6200 -Wire Wire Line - 5350 6300 5700 6300 Wire Wire Line 4050 4400 3750 4400 Wire Wire Line @@ -531,8 +531,6 @@ Text HLabel 2300 2050 2 60 Input ~ 0 T_DOUT Text HLabel 2300 2150 2 60 Output ~ 0 T_DIN -NoConn ~ 4050 4700 -NoConn ~ 4050 4800 NoConn ~ 2200 1750 NoConn ~ 2200 1650 NoConn ~ 2200 1550 @@ -541,4 +539,12 @@ NoConn ~ 2200 1150 NoConn ~ 2200 1250 NoConn ~ 2200 750 NoConn ~ 2200 650 +Wire Wire Line + 4050 4700 3750 4700 +Text HLabel 3750 4700 0 60 Output ~ 0 +BACKLIGHT_EN_N +Wire Wire Line + 5350 6300 5700 6300 +Text Label 5700 6300 2 60 ~ 0 +ADV_N $EndSCHEMATC diff --git a/audio.sch b/audio.sch index f22029a..7c81fdb 100644 --- a/audio.sch +++ b/audio.sch @@ -57,20 +57,20 @@ $EndDescr $Comp L UDA1330ATS U201 U 2 1 56CA5DE6 -P 4750 1750 -F 0 "U201" H 5277 1478 60 0000 L CNN -F 1 "UDA1330ATS" H 5277 1372 60 0000 L CNN -F 2 "Housings_SSOP:SSOP-16_5.3x6.2mm_Pitch0.65mm" H 4750 1800 60 0001 C CNN -F 3 "" H 4750 1800 60 0000 C CNN - 2 4750 1750 +P 4750 1800 +F 0 "U201" H 5277 1528 60 0000 L CNN +F 1 "UDA1330ATS" H 5277 1422 60 0000 L CNN +F 2 "Housings_SSOP:SSOP-16_5.3x6.2mm_Pitch0.65mm" H 4750 1850 60 0001 C CNN +F 3 "" H 4750 1850 60 0000 C CNN + 2 4750 1800 1 0 0 -1 $EndComp $Comp L UDA1330ATS U201 U 3 1 56CA5E46 P 5250 2800 -F 0 "U201" H 5500 2987 60 0000 C CNN -F 1 "UDA1330ATS" H 5500 2881 60 0000 C CNN +F 0 "U201" H 5500 2950 60 0000 C CNN +F 1 "UDA1330ATS" H 5500 2850 60 0000 C CNN F 2 "Housings_SSOP:SSOP-16_5.3x6.2mm_Pitch0.65mm" H 5250 2850 60 0001 C CNN F 3 "" H 5250 2850 60 0000 C CNN 3 5250 2800 @@ -87,13 +87,13 @@ F 3 "" H 4750 3750 60 0000 C CNN 4 4750 3700 1 0 0 -1 $EndComp -Text Label 4250 2000 0 60 ~ 0 +Text Label 4250 2050 0 60 ~ 0 ABCK -Text Label 4250 2100 0 60 ~ 0 +Text Label 4250 2150 0 60 ~ 0 AWS -Text Label 4250 2200 0 60 ~ 0 +Text Label 4250 2250 0 60 ~ 0 ADATA -Text Label 4250 1850 0 60 ~ 0 +Text Label 4250 1900 0 60 ~ 0 ACLK $Comp L CP_Small C902 @@ -118,23 +118,23 @@ F 3 "" H 4200 3050 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR901 +L GND #PWR110 U 1 1 56CAEAE3 P 4350 3250 -F 0 "#PWR901" H 4350 3000 50 0001 C CNN +F 0 "#PWR110" H 4350 3000 50 0001 C CNN F 1 "GND" H 4358 3076 50 0000 C CNN F 2 "" H 4350 3250 50 0000 C CNN F 3 "" H 4350 3250 50 0000 C CNN 1 4350 3250 1 0 0 -1 $EndComp -Text HLabel 4200 1850 0 60 Input ~ 0 +Text HLabel 4200 1900 0 60 Input ~ 0 ACLK -Text HLabel 4200 2000 0 60 Input ~ 0 +Text HLabel 4200 2050 0 60 Input ~ 0 ABCK -Text HLabel 4200 2100 0 60 Input ~ 0 +Text HLabel 4200 2150 0 60 Input ~ 0 AWS -Text HLabel 4200 2200 0 60 Input ~ 0 +Text HLabel 4200 2250 0 60 Input ~ 0 ADATA $Comp L LM358N U901 @@ -145,28 +145,17 @@ F 1 "LM358N" H 6100 2450 50 0000 L CNN F 2 "Housings_SOIC:SOIC-8_3.9x4.9mm_Pitch1.27mm" H 6050 2600 50 0001 C CNN F 3 "" H 6050 2600 50 0000 C CNN 1 6050 2600 - 1 0 0 -1 -$EndComp -$Comp -L LM358N U901 -U 2 1 56CB0820 -P 6050 3300 -F 0 "U901" H 6100 3450 50 0000 C CNN -F 1 "LM358N" H 6150 3150 50 0000 C CNN -F 2 "Housings_SOIC:SOIC-8_3.9x4.9mm_Pitch1.27mm" H 6050 3300 50 0001 C CNN -F 3 "" H 6050 3300 50 0000 C CNN - 2 6050 3300 1 0 0 1 $EndComp $Comp -L GND #PWR904 +L GND #PWR113 U 1 1 56CB0D63 -P 5750 3000 -F 0 "#PWR904" H 5750 2750 50 0001 C CNN -F 1 "GND" H 5758 2826 50 0000 C CNN -F 2 "" H 5750 3000 50 0000 C CNN -F 3 "" H 5750 3000 50 0000 C CNN - 1 5750 3000 +P 5950 3750 +F 0 "#PWR113" H 5950 3500 50 0001 C CNN +F 1 "GND" H 5958 3576 50 0000 C CNN +F 2 "" H 5950 3750 50 0000 C CNN +F 3 "" H 5950 3750 50 0000 C CNN + 1 5950 3750 1 0 0 -1 $EndComp $Comp @@ -214,10 +203,10 @@ F 3 "" H 6750 3150 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR907 +L GND #PWR115 U 1 1 56CB17E2 P 6550 3000 -F 0 "#PWR907" H 6550 2750 50 0001 C CNN +F 0 "#PWR115" H 6550 2750 50 0001 C CNN F 1 "GND" H 6558 2826 50 0000 C CNN F 2 "" H 6550 3000 50 0000 C CNN F 3 "" H 6550 3000 50 0000 C CNN @@ -236,10 +225,10 @@ F 3 "" H 7950 2750 50 0000 C CNN -1 0 0 1 $EndComp $Comp -L GND #PWR908 +L GND #PWR116 U 1 1 56CB19A0 P 7300 3600 -F 0 "#PWR908" H 7300 3350 50 0001 C CNN +F 0 "#PWR116" H 7300 3350 50 0001 C CNN F 1 "GND" H 7308 3426 50 0000 C CNN F 2 "" H 7300 3600 50 0000 C CNN F 3 "" H 7300 3600 50 0000 C CNN @@ -247,10 +236,10 @@ F 3 "" H 7300 3600 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR903 +L GND #PWR111 U 1 1 56CB318B P 4500 4250 -F 0 "#PWR903" H 4500 4000 50 0001 C CNN +F 0 "#PWR111" H 4500 4000 50 0001 C CNN F 1 "GND" H 4508 4076 50 0000 C CNN F 2 "" H 4500 4250 50 0000 C CNN F 3 "" H 4500 4250 50 0000 C CNN @@ -258,14 +247,14 @@ F 3 "" H 4500 4250 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR902 +L GND #PWR109 U 1 1 56CB240D -P 4500 2350 -F 0 "#PWR902" H 4500 2100 50 0001 C CNN -F 1 "GND" H 4508 2176 50 0000 C CNN -F 2 "" H 4500 2350 50 0000 C CNN -F 3 "" H 4500 2350 50 0000 C CNN - 1 4500 2350 +P 3900 2400 +F 0 "#PWR109" H 3900 2150 50 0001 C CNN +F 1 "GND" H 3908 2226 50 0000 C CNN +F 2 "" H 3900 2400 50 0000 C CNN +F 3 "" H 3900 2400 50 0000 C CNN + 1 3900 2400 1 0 0 -1 $EndComp Text HLabel 4000 4100 0 60 Input ~ 0 @@ -277,18 +266,7 @@ L3DATA Text Label 4050 4000 0 60 ~ 0 L3MODE Text Label 4050 3900 0 60 ~ 0 -ABCLK -$Comp -L VFPGA33 #PWR905 -U 1 1 56CE3E99 -P 5950 2200 -F 0 "#PWR905" H 5950 2050 50 0001 C CNN -F 1 "VFPGA33" H 5968 2374 50 0000 C CNN -F 2 "" H 5950 2200 50 0000 C CNN -F 3 "" H 5950 2200 50 0000 C CNN - 1 5950 2200 - 1 0 0 -1 -$EndComp +ABCK Text Label 5450 2900 0 60 ~ 0 DACL Text Label 5450 3000 0 60 ~ 0 @@ -300,26 +278,26 @@ AOUTR Text Label 4200 2900 0 60 ~ 0 DACVREF $Comp -L VSTM33 #PWR906 +L VSTM33 #PWR114 U 1 1 56CB0E9B -P 6250 3550 -F 0 "#PWR906" H 6250 3400 50 0001 C CNN -F 1 "VSTM33" H 6268 3724 50 0000 C CNN -F 2 "" H 6250 3550 50 0000 C CNN -F 3 "" H 6250 3550 50 0000 C CNN - 1 6250 3550 +P 6150 2950 +F 0 "#PWR114" H 6150 2800 50 0001 C CNN +F 1 "VSTM33" H 6168 3124 50 0000 C CNN +F 2 "" H 6150 2950 50 0000 C CNN +F 3 "" H 6150 2950 50 0000 C CNN + 1 6150 2950 1 0 0 -1 $EndComp Wire Wire Line - 4550 1850 4200 1850 + 4550 1900 4200 1900 Wire Wire Line - 4550 2000 4200 2000 + 4550 2050 4200 2050 Wire Wire Line - 4550 2100 4200 2100 + 4550 2150 4200 2150 Wire Wire Line - 4550 2200 4200 2200 + 4550 2250 4200 2250 Wire Wire Line - 4550 2300 4500 2300 + 4250 2350 4550 2350 Wire Wire Line 4500 2950 4500 2900 Wire Wire Line @@ -364,12 +342,6 @@ Wire Wire Line 5700 2250 5700 2500 Wire Wire Line 5700 2500 5750 2500 -Wire Wire Line - 5950 3600 6250 3600 -Wire Wire Line - 6250 3600 6250 3550 -Wire Wire Line - 5950 2200 5950 2300 Connection ~ 6400 2600 Connection ~ 6400 3300 Wire Wire Line @@ -401,8 +373,6 @@ Wire Wire Line 7450 2850 7250 2850 Wire Wire Line 7250 2850 7250 3300 -Wire Wire Line - 4500 2300 4500 2350 Wire Wire Line 4500 3800 4550 3800 Wire Wire Line @@ -413,11 +383,54 @@ Wire Wire Line 4550 4000 4000 4000 Wire Wire Line 4550 3900 4050 3900 +$Comp +L R R9 +U 1 1 56CC26E6 +P 4100 2350 +F 0 "R9" V 4200 2450 50 0000 C CNN +F 1 "0" V 4100 2350 50 0000 C CNN +F 2 "" V 4030 2350 50 0000 C CNN +F 3 "" H 4100 2350 50 0000 C CNN + 1 4100 2350 + 0 1 1 0 +$EndComp Wire Wire Line - 5750 2950 5750 3000 + 3900 2400 3900 2350 +Wire Wire Line + 3900 2350 3950 2350 +$Comp +L LM358N U901 +U 2 1 56CB0820 +P 6050 3300 +F 0 "U901" H 6100 3450 50 0000 C CNN +F 1 "LM358N" H 6150 3150 50 0000 C CNN +F 2 "Housings_SOIC:SOIC-8_3.9x4.9mm_Pitch1.27mm" H 6050 3300 50 0001 C CNN +F 3 "" H 6050 3300 50 0000 C CNN + 2 6050 3300 + 1 0 0 -1 +$EndComp Wire Wire Line 5950 2900 5950 3000 Wire Wire Line - 5950 2950 5750 2950 + 5950 3600 5950 3750 +Wire Wire Line + 6150 2950 5950 2950 Connection ~ 5950 2950 +$Comp +L GND #PWR112 +U 1 1 56CC3803 +P 5600 2300 +F 0 "#PWR112" H 5600 2050 50 0001 C CNN +F 1 "GND" H 5608 2126 50 0000 C CNN +F 2 "" H 5600 2300 50 0000 C CNN +F 3 "" H 5600 2300 50 0000 C CNN + 1 5600 2300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5600 2300 5950 2300 +Text Label 6050 3650 0 60 ~ 0 +FBR +Text Label 6050 2250 0 60 ~ 0 +FBL $EndSCHEMATC diff --git a/debug.sch b/debug.sch index cb6e1b4..1e8b595 100644 --- a/debug.sch +++ b/debug.sch @@ -90,10 +90,10 @@ F 3 "" H 2700 1150 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR304 +L GND #PWR62 U 1 1 5633954D P 2700 1350 -F 0 "#PWR304" H 2700 1100 50 0001 C CNN +F 0 "#PWR62" H 2700 1100 50 0001 C CNN F 1 "GND" H 2700 1200 50 0000 C CNN F 2 "" H 2700 1350 60 0000 C CNN F 3 "" H 2700 1350 60 0000 C CNN @@ -101,10 +101,10 @@ F 3 "" H 2700 1350 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR307 +L GND #PWR65 U 1 1 568DA1F8 P 4100 2000 -F 0 "#PWR307" H 4100 1750 50 0001 C CNN +F 0 "#PWR65" H 4100 1750 50 0001 C CNN F 1 "GND" H 4100 1850 50 0000 C CNN F 2 "" H 4100 2000 60 0000 C CNN F 3 "" H 4100 2000 60 0000 C CNN @@ -168,10 +168,10 @@ F 3 "" H 1650 3000 50 0000 C CNN 0 1 1 0 $EndComp $Comp -L GND #PWR301 +L GND #PWR59 U 1 1 56C718AB P 1450 3550 -F 0 "#PWR301" H 1450 3300 50 0001 C CNN +F 0 "#PWR59" H 1450 3300 50 0001 C CNN F 1 "GND" H 1458 3376 50 0000 C CNN F 2 "" H 1450 3550 50 0000 C CNN F 3 "" H 1450 3550 50 0000 C CNN @@ -190,10 +190,10 @@ F 3 "" H 5000 3200 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR308 +L GND #PWR66 U 1 1 56C74066 P 4750 3500 -F 0 "#PWR308" H 4750 3250 50 0001 C CNN +F 0 "#PWR66" H 4750 3250 50 0001 C CNN F 1 "GND" H 4758 3326 50 0000 C CNN F 2 "" H 4750 3500 50 0000 C CNN F 3 "" H 4750 3500 50 0000 C CNN @@ -285,10 +285,10 @@ Wire Wire Line Wire Wire Line 4750 3450 4800 3450 $Comp -L VFPGA33 #PWR303 +L VFPGA33 #PWR61 U 1 1 56CA6859 P 2500 900 -F 0 "#PWR303" H 2500 750 50 0001 C CNN +F 0 "#PWR61" H 2500 750 50 0001 C CNN F 1 "VFPGA33" H 2518 1074 50 0000 C CNN F 2 "" H 2500 900 50 0000 C CNN F 3 "" H 2500 900 50 0000 C CNN @@ -296,10 +296,10 @@ F 3 "" H 2500 900 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VFPGA33 #PWR306 +L VFPGA33 #PWR64 U 1 1 56CA6C73 P 4100 1500 -F 0 "#PWR306" H 4100 1350 50 0001 C CNN +F 0 "#PWR64" H 4100 1350 50 0001 C CNN F 1 "VFPGA33" H 4118 1674 50 0000 C CNN F 2 "" H 4100 1500 50 0000 C CNN F 3 "" H 4100 1500 50 0000 C CNN @@ -328,10 +328,10 @@ Wire Wire Line 2900 4750 2950 4750 Connection ~ 2950 4750 $Comp -L GND #PWR305 +L GND #PWR63 U 1 1 56CD0193 P 2950 4950 -F 0 "#PWR305" H 2950 4700 50 0001 C CNN +F 0 "#PWR63" H 2950 4700 50 0001 C CNN F 1 "GND" H 2958 4776 50 0000 C CNN F 2 "" H 2950 4950 50 0000 C CNN F 3 "" H 2950 4950 50 0000 C CNN @@ -414,10 +414,10 @@ Wire Wire Line 2200 4100 2200 4250 Connection ~ 2200 4200 $Comp -L VSTM33 #PWR302 +L VSTM33 #PWR60 U 1 1 56CD10CF P 2200 4100 -F 0 "#PWR302" H 2200 3950 50 0001 C CNN +F 0 "#PWR60" H 2200 3950 50 0001 C CNN F 1 "VSTM33" H 2218 4274 50 0000 C CNN F 2 "" H 2200 4100 50 0000 C CNN F 3 "" H 2200 4100 50 0000 C CNN diff --git a/display.sch b/display.sch index 3130826..9d96150 100644 --- a/display.sch +++ b/display.sch @@ -334,10 +334,10 @@ F 3 "" H 3250 7150 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR503 +L GND #PWR77 U 1 1 56C62B6C P 2700 7450 -F 0 "#PWR503" H 2700 7200 50 0001 C CNN +F 0 "#PWR77" H 2700 7200 50 0001 C CNN F 1 "GND" H 2708 7276 50 0000 C CNN F 2 "" H 2700 7450 50 0000 C CNN F 3 "" H 2700 7450 50 0000 C CNN @@ -345,10 +345,10 @@ F 3 "" H 2700 7450 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR504 +L GND #PWR78 U 1 1 56C62B72 P 2900 7450 -F 0 "#PWR504" H 2900 7200 50 0001 C CNN +F 0 "#PWR78" H 2900 7200 50 0001 C CNN F 1 "GND" H 2908 7276 50 0000 C CNN F 2 "" H 2900 7450 50 0000 C CNN F 3 "" H 2900 7450 50 0000 C CNN @@ -356,10 +356,10 @@ F 3 "" H 2900 7450 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR506 +L GND #PWR80 U 1 1 56C62B78 P 3150 7450 -F 0 "#PWR506" H 3150 7200 50 0001 C CNN +F 0 "#PWR80" H 3150 7200 50 0001 C CNN F 1 "GND" H 3158 7276 50 0000 C CNN F 2 "" H 3150 7450 50 0000 C CNN F 3 "" H 3150 7450 50 0000 C CNN @@ -378,10 +378,10 @@ Wire Wire Line 3150 7450 3150 7300 Connection ~ 3150 7300 $Comp -L VFPGA33 #PWR507 +L VFPGA33 #PWR81 U 1 1 56C62B84 P 3250 6900 -F 0 "#PWR507" H 3250 6750 50 0001 C CNN +F 0 "#PWR81" H 3250 6750 50 0001 C CNN F 1 "VFPGA33" H 3268 7074 50 0000 C CNN F 2 "" H 3250 6900 50 0000 C CNN F 3 "" H 3250 6900 50 0000 C CNN @@ -389,10 +389,10 @@ F 3 "" H 3250 6900 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VFPGA33 #PWR505 +L VFPGA33 #PWR79 U 1 1 56C62B8A P 3050 6800 -F 0 "#PWR505" H 3050 6650 50 0001 C CNN +F 0 "#PWR79" H 3050 6650 50 0001 C CNN F 1 "VFPGA33" H 3068 6974 50 0000 C CNN F 2 "" H 3050 6800 50 0000 C CNN F 3 "" H 3050 6800 50 0000 C CNN @@ -425,10 +425,10 @@ $EndComp Wire Wire Line 1150 7050 1350 7050 $Comp -L VFPGA33 #PWR501 +L VFPGA33 #PWR75 U 1 1 56C62DAA P 1150 7000 -F 0 "#PWR501" H 1150 6850 50 0001 C CNN +F 0 "#PWR75" H 1150 6850 50 0001 C CNN F 1 "VFPGA33" H 1168 7174 50 0000 C CNN F 2 "" H 1150 7000 50 0000 C CNN F 3 "" H 1150 7000 50 0000 C CNN @@ -447,10 +447,10 @@ Wire Wire Line 1250 7400 1250 7450 Connection ~ 1250 7400 $Comp -L GND #PWR502 +L GND #PWR76 U 1 1 56C62F03 P 1250 7450 -F 0 "#PWR502" H 1250 7200 50 0001 C CNN +F 0 "#PWR76" H 1250 7200 50 0001 C CNN F 1 "GND" H 1258 7276 50 0000 C CNN F 2 "" H 1250 7450 50 0000 C CNN F 3 "" H 1250 7450 50 0000 C CNN diff --git a/fpgna-cache.lib b/fpgna-cache.lib index f05ddfe..22ffba6 100644 --- a/fpgna-cache.lib +++ b/fpgna-cache.lib @@ -584,34 +584,34 @@ X PR2B 107 650 -1100 200 L 50 50 3 1 B X PR2A 108 650 -1200 200 L 50 50 3 1 B S 450 750 -450 -1900 4 1 0 f X PB7B 40 -650 200 200 R 50 50 4 1 B -X PB16A 50 -650 -500 200 R 50 50 4 1 I +X PB16A 50 -650 -500 200 R 50 50 4 1 B X PB28A 70 650 0 200 L 50 50 4 1 B X GNDIO51 41 -650 -1700 200 R 50 50 4 1 W X GNDIO52 51 -650 -1800 200 R 50 50 4 1 W X PB20A 61 650 500 200 L 50 50 4 1 B X PB27B 71 650 -100 200 L 50 50 4 1 B X VCCIO51 42 -650 -1500 200 R 50 50 4 1 W -X PB16B 52 -650 -600 200 R 50 50 4 1 I +X PB16B 52 -650 -600 200 R 50 50 4 1 B X PB20B 62 650 400 200 L 50 50 4 1 B X PB28B 72 650 -200 200 L 50 50 4 1 B -X PB13B 43 -650 100 200 R 50 50 4 1 I -X PB17A 53 -650 -700 200 R 50 50 4 1 I +X PB13B 43 -650 100 200 R 50 50 4 1 B +X PB17A 53 -650 -700 200 R 50 50 4 1 B X VCCIO4 63 650 -1700 200 L 50 50 4 1 W -X PB13A 44 -650 0 200 R 50 50 4 1 I -X PB17B 54 -650 -800 200 R 50 50 4 1 I +X PB13A 44 -650 0 200 R 50 50 4 1 B +X PB17B 54 -650 -800 200 R 50 50 4 1 B X GNDIO4 64 650 -1800 200 L 50 50 4 1 W -X PB15A 45 -650 -100 200 R 50 50 4 1 I -X PB18A 55 -650 -900 200 R 50 50 4 1 I +X PB15A 45 -650 -100 200 R 50 50 4 1 B +X PB18A 55 -650 -900 200 R 50 50 4 1 B X PB26A 65 650 300 200 L 50 50 4 1 B -X PB14A 46 -650 -200 200 R 50 50 4 1 I -X PB19A 56 -650 -1000 200 R 50 50 4 1 I +X PB14A 46 -650 -200 200 R 50 50 4 1 B +X PB19A 56 -650 -1000 200 R 50 50 4 1 B X PB26B 66 650 200 200 L 50 50 4 1 B X PB8A 37 -650 500 200 R 50 50 4 1 B -X PB15B 47 -650 -300 200 R 50 50 4 1 I -X PB18B 57 -650 -1100 200 R 50 50 4 1 I +X PB15B 47 -650 -300 200 R 50 50 4 1 B +X PB18B 57 -650 -1100 200 R 50 50 4 1 B X PB7A 38 -650 400 200 R 50 50 4 1 B -X PB14B 48 -650 -400 200 R 50 50 4 1 I -X PB19B 58 -650 -1200 200 R 50 50 4 1 I +X PB14B 48 -650 -400 200 R 50 50 4 1 B +X PB19B 58 -650 -1200 200 R 50 50 4 1 B X PB8B 39 -650 300 200 R 50 50 4 1 B X VCCIO52 49 -650 -1600 200 R 50 50 4 1 W X PB27A 69 650 100 200 L 50 50 4 1 B @@ -709,11 +709,11 @@ F3 "" 0 0 60 H V C CNN DRAW S -250 300 250 -300 0 1 0 N X SCK 1 -450 200 200 R 50 50 1 1 O C -X GND 2 450 200 200 L 50 50 1 1 w +X GND 2 450 200 200 L 50 50 1 1 W X TMS 3 -450 100 200 R 50 50 1 1 O -X GND 4 450 100 200 L 50 50 1 1 w +X GND 4 450 100 200 L 50 50 1 1 W X TDI 5 -450 0 200 R 50 50 1 1 O -X VCC 6 450 0 200 L 50 50 1 1 w +X VCC 6 450 0 200 L 50 50 1 1 W X TDO 7 -450 -100 200 R 50 50 1 1 I X INIT 8 450 -100 200 L 50 50 1 1 O X TRST 9 -450 -200 200 R 50 50 1 1 I @@ -1019,8 +1019,8 @@ X SYSCLK 6 -200 -100 200 R 50 50 2 1 I C X APPSEL 7 -200 -550 200 R 50 50 2 1 I S 0 0 500 -300 3 1 0 f X VREF 12 700 -100 200 L 50 50 3 1 I -X VOUTL 14 -200 -100 200 R 50 50 3 1 I -X VOUTR 16 -200 -200 200 R 50 50 3 1 I +X VOUTL 14 -200 -100 200 R 50 50 3 1 O +X VOUTR 16 -200 -200 200 R 50 50 3 1 O S 0 0 500 -500 4 1 0 f X APPL3 8 -200 -400 200 R 50 50 4 1 I X APPL2 9 -200 -300 200 R 50 50 4 1 I diff --git a/fpgna.kicad_pcb b/fpgna.kicad_pcb index 0675928..77814b2 100644 --- a/fpgna.kicad_pcb +++ b/fpgna.kicad_pcb @@ -1,15 +1,15 @@ (kicad_pcb (version 4) (host pcbnew "(2016-02-12 BZR 6554)-stable") (general - (links 251) - (no_connects 69) - (area 55.549999 31.549999 205.650001 107.050001) + (links 252) + (no_connects 73) + (area 55.549999 5.549373 205.650001 107.103) (thickness 1.6) (drawings 4) - (tracks 860) + (tracks 864) (zones 0) - (modules 27) - (nets 198) + (modules 26) + (nets 193) ) (page A4) @@ -103,190 +103,185 @@ (net 11 "Net-(U4-Pad7)") (net 12 "Net-(U4-Pad8)") (net 13 "Net-(U4-Pad9)") - (net 14 "Net-(U4-Pad14)") - (net 15 "Net-(U4-Pad26)") - (net 16 "Net-(U4-Pad29)") - (net 17 "Net-(U4-Pad30)") - (net 18 "Net-(U4-Pad31)") - (net 19 "Net-(U4-Pad32)") - (net 20 "Net-(U4-Pad33)") - (net 21 "Net-(U4-Pad34)") - (net 22 "Net-(U4-Pad35)") - (net 23 "Net-(U4-Pad36)") - (net 24 /FSMC/BOOT1) - (net 25 /FSMC/DA4) - (net 26 /FSMC/DA5) - (net 27 /FSMC/DA6) - (net 28 /FSMC/DA7) - (net 29 /FSMC/DA8) - (net 30 /FSMC/DA9) - (net 31 /FSMC/DA10) - (net 32 /FSMC/DA11) - (net 33 /FSMC/DA12) - (net 34 "Net-(U4-Pad47)") - (net 35 "Net-(U4-Pad48)") - (net 36 /FSMC/DA14) - (net 37 /FSMC/DA15) - (net 38 /FSMC/A16) - (net 39 /FSMC/A17) - (net 40 /FSMC/A18) - (net 41 /FSMC/DA0) - (net 42 /FSMC/DA1) - (net 43 "Net-(U4-Pad71)") - (net 44 /FSMC/DA2) - (net 45 /FSMC/DA3) - (net 46 /FSMC/CLK) - (net 47 /FSMC/OE_N) - (net 48 /FSMC/WE_N) - (net 49 /FSMC/WAIT_N) - (net 50 /FSMC/JTDO) - (net 51 /FSMC/JRST_N) - (net 52 "Net-(U4-Pad91)") - (net 53 "Net-(U4-Pad92)") - (net 54 /FSMC/ADV_N) - (net 55 "Net-(U4-Pad94)") - (net 56 "Net-(U4-Pad95)") - (net 57 "Net-(U4-Pad96)") - (net 58 /FSMC/BL0_N) - (net 59 /FSMC/BL1_N) - (net 60 VSTM33) - (net 61 GND) - (net 62 /powersupply/VCAP1) - (net 63 /powersupply/VCAP2) - (net 64 "Net-(U6-Pad5)") - (net 65 "Net-(U6-Pad31)") - (net 66 "Net-(U6-Pad35)") - (net 67 "Net-(R14-Pad1)") - (net 68 "Net-(U6-Pad38)") - (net 69 "Net-(U6-Pad39)") - (net 70 "Net-(U6-Pad40)") - (net 71 /display/DB0) - (net 72 /display/DB1) - (net 73 /display/DB2) - (net 74 /display/RS) - (net 75 /display/DB3) - (net 76 /display/WR) - (net 77 /display/DB4) - (net 78 /display/RD) - (net 79 /display/DB5) - (net 80 /display/DB8) - (net 81 /display/DB6) - (net 82 /display/DB9) - (net 83 /display/DB7) - (net 84 /display/DB10) - (net 85 /display/DB11) - (net 86 /display/DB12) - (net 87 /display/DB13) - (net 88 /display/DB14) - (net 89 /display/DB15) - (net 90 /display/CS) - (net 91 /display/RST) - (net 92 "Net-(U3-Pad73)") - (net 93 /display/T_BUSY) - (net 94 /display/T_IRQ) - (net 95 /sdram/DQ0) - (net 96 /sdram/DQ1) - (net 97 /sdram/DQ2) - (net 98 /sdram/DQ3) - (net 99 /sdram/DQ4) - (net 100 /sdram/DQ5) - (net 101 /sdram/DQ6) - (net 102 /sdram/DQ7) - (net 103 /sdram/DQML) - (net 104 /sdram/WE) - (net 105 /sdram/CAS) - (net 106 /sdram/RAS) - (net 107 /sdram/CS) - (net 108 /sdram/BA0) - (net 109 /sdram/BA1) - (net 110 /sdram/A10) - (net 111 /sdram/A0) - (net 112 /sdram/A1) - (net 113 /sdram/A2) - (net 114 /sdram/A3) - (net 115 /sdram/A4) - (net 116 /sdram/A5) - (net 117 /sdram/A6) - (net 118 /sdram/A7) - (net 119 /sdram/A8) - (net 120 /sdram/A9) - (net 121 /sdram/A11) - (net 122 "Net-(U7-Pad36)") - (net 123 /sdram/CKE) - (net 124 /sdram/CLK) - (net 125 /sdram/DQMH) - (net 126 "Net-(U7-Pad40)") - (net 127 /sdram/DQ8) - (net 128 /sdram/DQ9) - (net 129 /sdram/DQ10) - (net 130 /sdram/DQ11) - (net 131 /sdram/DQ12) - (net 132 /sdram/DQ13) - (net 133 /sdram/DQ14) - (net 134 /sdram/DQ15) - (net 135 "Net-(U3-Pad114)") - (net 136 "Net-(U3-Pad115)") - (net 137 /sdcard/SDIO_D3) - (net 138 /sdcard/SDIO_CLK) - (net 139 /sdcard/SDIO_D0) - (net 140 /sdcard/SDIO_D1) - (net 141 /sdcard/SDIO_D2) - (net 142 /debug/FTMS) - (net 143 /debug/FTDI) - (net 144 /debug/FTCK) - (net 145 /debug/FTDO) - (net 146 /debug/OSCIN) - (net 147 /debug/OSCOUT) - (net 148 /FSMC/SDIO_CMD) - (net 149 /userif/SW_LEFT) - (net 150 /userif/SW_UP) - (net 151 /userif/SW_DOWN) - (net 152 /userif/SW_RIGHT) - (net 153 /FSMC/T_CS) - (net 154 /FSMC/T_CLK) - (net 155 /FSMC/T_DOUT) - (net 156 /FSMC/T_DIN) - (net 157 "Net-(U6-Pad30)") - (net 158 "Net-(U6-Pad32)") - (net 159 "Net-(U6-Pad34)") - (net 160 "Net-(U6-Pad36)") - (net 161 /sdcard/SW_B) - (net 162 /sdcard/SW_A) - (net 163 /sdcard/SW_C) - (net 164 /sdcard/SW_D) - (net 165 "Net-(CON801-Pad9)") - (net 166 /userif/BTN_STBY) - (net 167 /powersupply/TOE) - (net 168 /powersupply/CFG0) - (net 169 /userif/RGBLED0) - (net 170 /userif/RGBLED1) - (net 171 /userif/RGBLED2) - (net 172 /debug/JTMS) - (net 173 /debug/JTCK) - (net 174 /debug/JTDI) - (net 175 /audio/ABCK) - (net 176 /audio/AWS) - (net 177 /audio/ADATA) - (net 178 /audio/ACLK) - (net 179 /audio/L3DATA) - (net 180 /audio/L3MODE) - (net 181 /audio/DACL) - (net 182 /audio/DACR) - (net 183 /audio/DACVREF) - (net 184 "Net-(D1-Pad1)") - (net 185 VSYS) - (net 186 /sdram/CLK_50M) - (net 187 VUSB) - (net 188 /powersupply/CHG_ACTIVE_N) - (net 189 "Net-(U5-Pad4)") - (net 190 "Net-(R8-Pad1)") - (net 191 /powersupply/USB_PRESENT_N) - (net 192 "Net-(P2-Pad1)") - (net 193 VBAT) - (net 194 /audio/ABCLK) - (net 195 "Net-(C903-Pad2)") - (net 196 "Net-(C904-Pad2)") - (net 197 "Net-(X601-Pad1)") + (net 14 "Net-(U4-Pad33)") + (net 15 "Net-(U4-Pad34)") + (net 16 "Net-(U4-Pad35)") + (net 17 "Net-(U4-Pad36)") + (net 18 /FSMC/BOOT1) + (net 19 /FSMC/DA4) + (net 20 /FSMC/DA5) + (net 21 /FSMC/DA6) + (net 22 /FSMC/DA7) + (net 23 /FSMC/DA8) + (net 24 /FSMC/DA9) + (net 25 /FSMC/DA10) + (net 26 /FSMC/DA11) + (net 27 /FSMC/DA12) + (net 28 "Net-(U4-Pad47)") + (net 29 "Net-(U4-Pad48)") + (net 30 /FSMC/DA14) + (net 31 /FSMC/DA15) + (net 32 /FSMC/A16) + (net 33 /FSMC/A17) + (net 34 /FSMC/A18) + (net 35 /FSMC/DA0) + (net 36 /FSMC/DA1) + (net 37 /FSMC/DA2) + (net 38 /FSMC/DA3) + (net 39 /FSMC/CLK) + (net 40 /FSMC/OE_N) + (net 41 /FSMC/WE_N) + (net 42 /FSMC/WAIT_N) + (net 43 /FSMC/JTDO) + (net 44 /FSMC/JRST_N) + (net 45 "Net-(U4-Pad91)") + (net 46 "Net-(U4-Pad92)") + (net 47 /FSMC/ADV_N) + (net 48 "Net-(U4-Pad95)") + (net 49 "Net-(U4-Pad96)") + (net 50 /FSMC/BL0_N) + (net 51 /FSMC/BL1_N) + (net 52 VSTM33) + (net 53 GND) + (net 54 /powersupply/VCAP1) + (net 55 /powersupply/VCAP2) + (net 56 "Net-(U6-Pad5)") + (net 57 "Net-(U6-Pad31)") + (net 58 "Net-(U6-Pad35)") + (net 59 "Net-(R14-Pad1)") + (net 60 "Net-(U6-Pad38)") + (net 61 "Net-(U6-Pad39)") + (net 62 "Net-(U6-Pad40)") + (net 63 /display/DB0) + (net 64 /display/DB1) + (net 65 /display/DB2) + (net 66 /display/RS) + (net 67 /display/DB3) + (net 68 /display/WR) + (net 69 /display/DB4) + (net 70 /display/RD) + (net 71 /display/DB5) + (net 72 /display/DB8) + (net 73 /display/DB6) + (net 74 /display/DB9) + (net 75 /display/DB7) + (net 76 /display/DB10) + (net 77 /display/DB11) + (net 78 /display/DB12) + (net 79 /display/DB13) + (net 80 /display/DB14) + (net 81 /display/DB15) + (net 82 /display/CS) + (net 83 /display/RST) + (net 84 "Net-(U3-Pad73)") + (net 85 /display/T_BUSY) + (net 86 /display/T_IRQ) + (net 87 /sdram/DQ0) + (net 88 /sdram/DQ1) + (net 89 /sdram/DQ2) + (net 90 /sdram/DQ3) + (net 91 /sdram/DQ4) + (net 92 /sdram/DQ5) + (net 93 /sdram/DQ6) + (net 94 /sdram/DQ7) + (net 95 /sdram/DQML) + (net 96 /sdram/WE) + (net 97 /sdram/CAS) + (net 98 /sdram/RAS) + (net 99 /sdram/CS) + (net 100 /sdram/BA0) + (net 101 /sdram/BA1) + (net 102 /sdram/A10) + (net 103 /sdram/A0) + (net 104 /sdram/A1) + (net 105 /sdram/A2) + (net 106 /sdram/A3) + (net 107 /sdram/A4) + (net 108 /sdram/A5) + (net 109 /sdram/A6) + (net 110 /sdram/A7) + (net 111 /sdram/A8) + (net 112 /sdram/A9) + (net 113 /sdram/A11) + (net 114 "Net-(U7-Pad36)") + (net 115 /sdram/CKE) + (net 116 /sdram/CLK) + (net 117 /sdram/DQMH) + (net 118 "Net-(U7-Pad40)") + (net 119 /sdram/DQ8) + (net 120 /sdram/DQ9) + (net 121 /sdram/DQ10) + (net 122 /sdram/DQ11) + (net 123 /sdram/DQ12) + (net 124 /sdram/DQ13) + (net 125 /sdram/DQ14) + (net 126 /sdram/DQ15) + (net 127 /sdcard/SDIO_D3) + (net 128 /sdcard/SDIO_CLK) + (net 129 /sdcard/SDIO_D0) + (net 130 /sdcard/SDIO_D1) + (net 131 /sdcard/SDIO_D2) + (net 132 /debug/FTMS) + (net 133 /debug/FTDI) + (net 134 /debug/FTCK) + (net 135 /debug/FTDO) + (net 136 /debug/OSCIN) + (net 137 /debug/OSCOUT) + (net 138 /FSMC/SDIO_CMD) + (net 139 /userif/SW_LEFT) + (net 140 /userif/SW_UP) + (net 141 /userif/SW_DOWN) + (net 142 /userif/SW_RIGHT) + (net 143 /FSMC/T_CS) + (net 144 /FSMC/T_CLK) + (net 145 /FSMC/T_DOUT) + (net 146 /FSMC/T_DIN) + (net 147 "Net-(U6-Pad30)") + (net 148 "Net-(U6-Pad32)") + (net 149 "Net-(U6-Pad34)") + (net 150 "Net-(U6-Pad36)") + (net 151 /sdcard/SW_B) + (net 152 /sdcard/SW_A) + (net 153 /sdcard/SW_C) + (net 154 /sdcard/SW_D) + (net 155 /powersupply/TOE) + (net 156 /powersupply/CFG0) + (net 157 /userif/RGBLED0) + (net 158 /userif/RGBLED1) + (net 159 /userif/RGBLED2) + (net 160 /debug/JTMS) + (net 161 /debug/JTCK) + (net 162 /debug/JTDI) + (net 163 /audio/ABCK) + (net 164 /audio/AWS) + (net 165 /audio/ADATA) + (net 166 /audio/ACLK) + (net 167 /audio/L3DATA) + (net 168 /audio/L3MODE) + (net 169 /audio/DACL) + (net 170 /audio/DACR) + (net 171 /audio/DACVREF) + (net 172 "Net-(D1-Pad1)") + (net 173 VSYS) + (net 174 /sdram/CLK_50M) + (net 175 VUSB) + (net 176 /powersupply/CHG_ACTIVE_N) + (net 177 "Net-(U5-Pad4)") + (net 178 "Net-(R8-Pad1)") + (net 179 /powersupply/USB_PRESENT_N) + (net 180 "Net-(P2-Pad1)") + (net 181 VBAT) + (net 182 "Net-(X601-Pad1)") + (net 183 /sdcard/SDCARD_DETECT) + (net 184 /FSMC/BACKLIGHT_EN_N) + (net 185 /debug/NRST) + (net 186 /powersupply/SYS_VOLTAGE) + (net 187 /powersupply/FPGA_ENABLE_N) + (net 188 /powersupply/CHARGE_ENABLE) + (net 189 /debug/BOOT0) + (net 190 "Net-(R9-Pad1)") + (net 191 /audio/FBL) + (net 192 /audio/FBR) (net_class Default "This is the default net class." (clearance 0.153) @@ -305,6 +300,7 @@ (add_net /FSMC/A22) (add_net /FSMC/A23) (add_net /FSMC/ADV_N) + (add_net /FSMC/BACKLIGHT_EN_N) (add_net /FSMC/BL0_N) (add_net /FSMC/BL1_N) (add_net /FSMC/BOOT1) @@ -337,15 +333,17 @@ (add_net /FSMC/WAIT_N) (add_net /FSMC/WE_N) (add_net /audio/ABCK) - (add_net /audio/ABCLK) (add_net /audio/ACLK) (add_net /audio/ADATA) (add_net /audio/AWS) (add_net /audio/DACL) (add_net /audio/DACR) (add_net /audio/DACVREF) + (add_net /audio/FBL) + (add_net /audio/FBR) (add_net /audio/L3DATA) (add_net /audio/L3MODE) + (add_net /debug/BOOT0) (add_net /debug/FTCK) (add_net /debug/FTDI) (add_net /debug/FTDO) @@ -353,6 +351,7 @@ (add_net /debug/JTCK) (add_net /debug/JTDI) (add_net /debug/JTMS) + (add_net /debug/NRST) (add_net /debug/OSCIN) (add_net /debug/OSCOUT) (add_net /display/CS) @@ -379,11 +378,15 @@ (add_net /display/T_IRQ) (add_net /display/WR) (add_net /powersupply/CFG0) + (add_net /powersupply/CHARGE_ENABLE) (add_net /powersupply/CHG_ACTIVE_N) + (add_net /powersupply/FPGA_ENABLE_N) + (add_net /powersupply/SYS_VOLTAGE) (add_net /powersupply/TOE) (add_net /powersupply/USB_PRESENT_N) (add_net /powersupply/VCAP1) (add_net /powersupply/VCAP2) + (add_net /sdcard/SDCARD_DETECT) (add_net /sdcard/SDIO_CLK) (add_net /sdcard/SDIO_D0) (add_net /sdcard/SDIO_D1) @@ -432,7 +435,6 @@ (add_net /sdram/DQML) (add_net /sdram/RAS) (add_net /sdram/WE) - (add_net /userif/BTN_STBY) (add_net /userif/RGBLED0) (add_net /userif/RGBLED1) (add_net /userif/RGBLED2) @@ -442,22 +444,12 @@ (add_net /userif/SW_UP) (add_net GND) (add_net "Net-(C4-Pad1)") - (add_net "Net-(C903-Pad2)") - (add_net "Net-(C904-Pad2)") - (add_net "Net-(CON801-Pad9)") (add_net "Net-(D1-Pad1)") (add_net "Net-(P2-Pad1)") (add_net "Net-(R14-Pad1)") (add_net "Net-(R8-Pad1)") - (add_net "Net-(U3-Pad114)") - (add_net "Net-(U3-Pad115)") + (add_net "Net-(R9-Pad1)") (add_net "Net-(U3-Pad73)") - (add_net "Net-(U4-Pad14)") - (add_net "Net-(U4-Pad26)") - (add_net "Net-(U4-Pad29)") - (add_net "Net-(U4-Pad30)") - (add_net "Net-(U4-Pad31)") - (add_net "Net-(U4-Pad32)") (add_net "Net-(U4-Pad33)") (add_net "Net-(U4-Pad34)") (add_net "Net-(U4-Pad35)") @@ -465,12 +457,10 @@ (add_net "Net-(U4-Pad47)") (add_net "Net-(U4-Pad48)") (add_net "Net-(U4-Pad7)") - (add_net "Net-(U4-Pad71)") (add_net "Net-(U4-Pad8)") (add_net "Net-(U4-Pad9)") (add_net "Net-(U4-Pad91)") (add_net "Net-(U4-Pad92)") - (add_net "Net-(U4-Pad94)") (add_net "Net-(U4-Pad95)") (add_net "Net-(U4-Pad96)") (add_net "Net-(U5-Pad4)") @@ -494,6 +484,326 @@ (add_net VUSB) ) + (module Housings_QFP:LQFP-144_20x20mm_Pitch0.5mm (layer F.Cu) (tedit 54130A77) (tstamp 56C45027) + (at 131.443728 62.795542 180) + (descr "144-Lead Plastic Low Profile Quad Flatpack (PL) - 20x20x1.40 mm Body [LQFP], 2.00 mm Footprint (see Microchip Packaging Specification 00000049BS.pdf)") + (tags "QFP 0.5") + (path /563244F7/56323459) + (attr smd) + (fp_text reference U3 (at 0 -12.475 180) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value LFXP2-5E-6TN144C (at 0 12.475 180) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -11.75 -11.75) (end -11.75 11.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start 11.75 -11.75) (end 11.75 11.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -11.75 -11.75) (end 11.75 -11.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -11.75 11.75) (end 11.75 11.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -10.175 -10.175) (end -10.175 -9.125) (layer F.SilkS) (width 0.15)) + (fp_line (start 10.175 -10.175) (end 10.175 -9.125) (layer F.SilkS) (width 0.15)) + (fp_line (start 10.175 10.175) (end 10.175 9.125) (layer F.SilkS) (width 0.15)) + (fp_line (start -10.175 10.175) (end -10.175 9.125) (layer F.SilkS) (width 0.15)) + (fp_line (start -10.175 -10.175) (end -9.125 -10.175) (layer F.SilkS) (width 0.15)) + (fp_line (start -10.175 10.175) (end -9.125 10.175) (layer F.SilkS) (width 0.15)) + (fp_line (start 10.175 10.175) (end 9.125 10.175) (layer F.SilkS) (width 0.15)) + (fp_line (start 10.175 -10.175) (end 9.125 -10.175) (layer F.SilkS) (width 0.15)) + (fp_line (start -10.175 -9.125) (end -11.475 -9.125) (layer F.SilkS) (width 0.15)) + (pad 1 smd rect (at -10.7 -8.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 50 /FSMC/BL0_N)) + (pad 2 smd rect (at -10.7 -8.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 51 /FSMC/BL1_N)) + (pad 3 smd rect (at -10.7 -7.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 53 GND)) + (pad 4 smd rect (at -10.7 -7.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 4 VFPGA33)) + (pad 5 smd rect (at -10.7 -6.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 6 /FSMC/A23)) + (pad 6 smd rect (at -10.7 -6.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 7 /FSMC/A19)) + (pad 7 smd rect (at -10.7 -5.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 8 /FSMC/A20)) + (pad 8 smd rect (at -10.7 -5.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 9 /FSMC/A21)) + (pad 9 smd rect (at -10.7 -4.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 10 /FSMC/A22)) + (pad 10 smd rect (at -10.7 -4.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 168 /audio/L3MODE)) + (pad 11 smd rect (at -10.7 -3.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 165 /audio/ADATA)) + (pad 12 smd rect (at -10.7 -3.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 53 GND)) + (pad 13 smd rect (at -10.7 -2.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 167 /audio/L3DATA)) + (pad 14 smd rect (at -10.7 -2.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 4 VFPGA33)) + (pad 15 smd rect (at -10.7 -1.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 166 /audio/ACLK)) + (pad 16 smd rect (at -10.7 -1.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 174 /sdram/CLK_50M)) + (pad 17 smd rect (at -10.7 -0.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 164 /audio/AWS)) + (pad 18 smd rect (at -10.7 -0.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 163 /audio/ABCK)) + (pad 19 smd rect (at -10.7 0.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 107 /sdram/A4)) + (pad 20 smd rect (at -10.7 0.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 108 /sdram/A5)) + (pad 21 smd rect (at -10.7 1.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 109 /sdram/A6)) + (pad 22 smd rect (at -10.7 1.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 110 /sdram/A7)) + (pad 23 smd rect (at -10.7 2.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 4 VFPGA33)) + (pad 24 smd rect (at -10.7 2.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 5 +1V2)) + (pad 25 smd rect (at -10.7 3.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 155 /powersupply/TOE)) + (pad 26 smd rect (at -10.7 3.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 156 /powersupply/CFG0)) + (pad 27 smd rect (at -10.7 4.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 111 /sdram/A8)) + (pad 28 smd rect (at -10.7 4.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 112 /sdram/A9)) + (pad 29 smd rect (at -10.7 5.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 113 /sdram/A11)) + (pad 30 smd rect (at -10.7 5.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 106 /sdram/A3)) + (pad 31 smd rect (at -10.7 6.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 105 /sdram/A2)) + (pad 32 smd rect (at -10.7 6.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 104 /sdram/A1)) + (pad 33 smd rect (at -10.7 7.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 4 VFPGA33)) + (pad 34 smd rect (at -10.7 7.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 53 GND)) + (pad 35 smd rect (at -10.7 8.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 102 /sdram/A10)) + (pad 36 smd rect (at -10.7 8.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 103 /sdram/A0)) + (pad 37 smd rect (at -8.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 101 /sdram/BA1)) + (pad 38 smd rect (at -8.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 100 /sdram/BA0)) + (pad 39 smd rect (at -7.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 99 /sdram/CS)) + (pad 40 smd rect (at -7.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 98 /sdram/RAS)) + (pad 41 smd rect (at -6.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 53 GND)) + (pad 42 smd rect (at -6.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 4 VFPGA33)) + (pad 43 smd rect (at -5.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 115 /sdram/CKE)) + (pad 44 smd rect (at -5.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 97 /sdram/CAS)) + (pad 45 smd rect (at -4.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 116 /sdram/CLK)) + (pad 46 smd rect (at -4.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 96 /sdram/WE)) + (pad 47 smd rect (at -3.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 117 /sdram/DQMH)) + (pad 48 smd rect (at -3.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 95 /sdram/DQML)) + (pad 49 smd rect (at -2.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 4 VFPGA33)) + (pad 50 smd rect (at -2.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 94 /sdram/DQ7)) + (pad 51 smd rect (at -1.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 53 GND)) + (pad 52 smd rect (at -1.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 119 /sdram/DQ8)) + (pad 53 smd rect (at -0.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 93 /sdram/DQ6)) + (pad 54 smd rect (at -0.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 120 /sdram/DQ9)) + (pad 55 smd rect (at 0.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 92 /sdram/DQ5)) + (pad 56 smd rect (at 0.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 121 /sdram/DQ10)) + (pad 57 smd rect (at 1.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 91 /sdram/DQ4)) + (pad 58 smd rect (at 1.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 122 /sdram/DQ11)) + (pad 59 smd rect (at 2.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 5 +1V2)) + (pad 60 smd rect (at 2.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 4 VFPGA33)) + (pad 61 smd rect (at 3.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 90 /sdram/DQ3)) + (pad 62 smd rect (at 3.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 123 /sdram/DQ12)) + (pad 63 smd rect (at 4.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 4 VFPGA33)) + (pad 64 smd rect (at 4.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 53 GND)) + (pad 65 smd rect (at 5.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 89 /sdram/DQ2)) + (pad 66 smd rect (at 5.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 124 /sdram/DQ13)) + (pad 67 smd rect (at 6.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 4 VFPGA33)) + (pad 68 smd rect (at 6.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 53 GND)) + (pad 69 smd rect (at 7.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 88 /sdram/DQ1)) + (pad 70 smd rect (at 7.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 125 /sdram/DQ14)) + (pad 71 smd rect (at 8.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 87 /sdram/DQ0)) + (pad 72 smd rect (at 8.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 126 /sdram/DQ15)) + (pad 73 smd rect (at 10.7 8.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 84 "Net-(U3-Pad73)")) + (pad 74 smd rect (at 10.7 8.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 63 /display/DB0)) + (pad 75 smd rect (at 10.7 7.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 53 GND)) + (pad 76 smd rect (at 10.7 7.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 4 VFPGA33)) + (pad 77 smd rect (at 10.7 6.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 64 /display/DB1)) + (pad 78 smd rect (at 10.7 6.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 65 /display/DB2)) + (pad 79 smd rect (at 10.7 5.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 132 /debug/FTMS)) + (pad 80 smd rect (at 10.7 5.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 133 /debug/FTDI)) + (pad 81 smd rect (at 10.7 4.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 134 /debug/FTCK)) + (pad 82 smd rect (at 10.7 4.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 135 /debug/FTDO)) + (pad 83 smd rect (at 10.7 3.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 4 VFPGA33)) + (pad 84 smd rect (at 10.7 3.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 5 +1V2)) + (pad 85 smd rect (at 10.7 2.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 4 VFPGA33)) + (pad 86 smd rect (at 10.7 2.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 53 GND)) + (pad 87 smd rect (at 10.7 1.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 66 /display/RS)) + (pad 88 smd rect (at 10.7 1.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 67 /display/DB3)) + (pad 89 smd rect (at 10.7 0.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 68 /display/WR)) + (pad 90 smd rect (at 10.7 0.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 69 /display/DB4)) + (pad 91 smd rect (at 10.7 -0.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 70 /display/RD)) + (pad 92 smd rect (at 10.7 -0.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 71 /display/DB5)) + (pad 93 smd rect (at 10.7 -1.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 72 /display/DB8)) + (pad 94 smd rect (at 10.7 -1.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 73 /display/DB6)) + (pad 95 smd rect (at 10.7 -2.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 4 VFPGA33)) + (pad 96 smd rect (at 10.7 -2.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 74 /display/DB9)) + (pad 97 smd rect (at 10.7 -3.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 53 GND)) + (pad 98 smd rect (at 10.7 -3.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 75 /display/DB7)) + (pad 99 smd rect (at 10.7 -4.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 76 /display/DB10)) + (pad 100 smd rect (at 10.7 -4.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 77 /display/DB11)) + (pad 101 smd rect (at 10.7 -5.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 78 /display/DB12)) + (pad 102 smd rect (at 10.7 -5.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 79 /display/DB13)) + (pad 103 smd rect (at 10.7 -6.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 80 /display/DB14)) + (pad 104 smd rect (at 10.7 -6.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 81 /display/DB15)) + (pad 105 smd rect (at 10.7 -7.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 4 VFPGA33)) + (pad 106 smd rect (at 10.7 -7.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 53 GND)) + (pad 107 smd rect (at 10.7 -8.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 82 /display/CS)) + (pad 108 smd rect (at 10.7 -8.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 83 /display/RST)) + (pad 109 smd rect (at 8.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 34 /FSMC/A18)) + (pad 110 smd rect (at 8.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 33 /FSMC/A17)) + (pad 111 smd rect (at 7.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 53 GND)) + (pad 112 smd rect (at 7.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 4 VFPGA33)) + (pad 113 smd rect (at 6.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 32 /FSMC/A16)) + (pad 114 smd rect (at 6.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 184 /FSMC/BACKLIGHT_EN_N)) + (pad 115 smd rect (at 5.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 40 /FSMC/OE_N)) + (pad 116 smd rect (at 5.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 39 /FSMC/CLK)) + (pad 117 smd rect (at 4.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 4 VFPGA33)) + (pad 118 smd rect (at 4.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 5 +1V2)) + (pad 119 smd rect (at 3.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 31 /FSMC/DA15)) + (pad 120 smd rect (at 3.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 30 /FSMC/DA14)) + (pad 121 smd rect (at 2.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 1 /FSMC/DA13)) + (pad 122 smd rect (at 2.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 35 /FSMC/DA0)) + (pad 123 smd rect (at 1.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 36 /FSMC/DA1)) + (pad 124 smd rect (at 1.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 37 /FSMC/DA2)) + (pad 125 smd rect (at 0.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 38 /FSMC/DA3)) + (pad 126 smd rect (at 0.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 53 GND)) + (pad 127 smd rect (at -0.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 27 /FSMC/DA12)) + (pad 128 smd rect (at -0.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 4 VFPGA33)) + (pad 129 smd rect (at -1.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 26 /FSMC/DA11)) + (pad 130 smd rect (at -1.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 25 /FSMC/DA10)) + (pad 131 smd rect (at -2.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 24 /FSMC/DA9)) + (pad 132 smd rect (at -2.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 23 /FSMC/DA8)) + (pad 133 smd rect (at -3.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 22 /FSMC/DA7)) + (pad 134 smd rect (at -3.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 21 /FSMC/DA6)) + (pad 135 smd rect (at -4.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 53 GND)) + (pad 136 smd rect (at -4.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 4 VFPGA33)) + (pad 137 smd rect (at -5.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 20 /FSMC/DA5)) + (pad 138 smd rect (at -5.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 19 /FSMC/DA4)) + (pad 139 smd rect (at -6.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 53 GND)) + (pad 140 smd rect (at -6.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 4 VFPGA33)) + (pad 141 smd rect (at -7.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 41 /FSMC/WE_N)) + (pad 142 smd rect (at -7.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 42 /FSMC/WAIT_N)) + (pad 143 smd rect (at -8.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 2 /FSMC/E1_N)) + (pad 144 smd rect (at -8.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 47 /FSMC/ADV_N)) + (model Housings_QFP.3dshapes/LQFP-144_20x20mm_Pitch0.5mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + (module itead-display:ITDB02-3.2WD (layer F.Cu) (tedit 56C6AB88) (tstamp 56C69EE3) (at 86.9 51.879) (path /563244F7/56C57ED6) @@ -534,85 +844,85 @@ (fp_line (start 1.27 1.2696) (end -1.27 1.2696) (layer F.SilkS) (width 0.15)) (fp_line (start -1.55 -1.5504) (end -1.55 -0.0004) (layer F.SilkS) (width 0.15)) (pad 1 thru_hole rect (at 0 -0.0004) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 61 GND)) + (net 53 GND)) (pad 2 thru_hole oval (at 2.54 -0.0004) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 71 /display/DB0)) + (net 63 /display/DB0)) (pad 3 thru_hole oval (at 0 2.5396) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) (net 4 VFPGA33)) (pad 4 thru_hole oval (at 2.54 2.5396) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 72 /display/DB1)) + (net 64 /display/DB1)) (pad 5 thru_hole oval (at 0 5.0796) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 64 "Net-(U6-Pad5)")) + (net 56 "Net-(U6-Pad5)")) (pad 6 thru_hole oval (at 2.54 5.0796) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 73 /display/DB2)) + (net 65 /display/DB2)) (pad 7 thru_hole oval (at 0 7.6196) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 74 /display/RS)) + (net 66 /display/RS)) (pad 8 thru_hole oval (at 2.54 7.6196) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 75 /display/DB3)) + (net 67 /display/DB3)) (pad 9 thru_hole oval (at 0 10.1596) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 76 /display/WR)) + (net 68 /display/WR)) (pad 10 thru_hole oval (at 2.54 10.1596) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 77 /display/DB4)) + (net 69 /display/DB4)) (pad 11 thru_hole oval (at 0 12.6996) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 78 /display/RD)) + (net 70 /display/RD)) (pad 12 thru_hole oval (at 2.54 12.6996) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 79 /display/DB5)) + (net 71 /display/DB5)) (pad 13 thru_hole oval (at 0 15.2396) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 80 /display/DB8)) + (net 72 /display/DB8)) (pad 14 thru_hole oval (at 2.54 15.2396) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 81 /display/DB6)) + (net 73 /display/DB6)) (pad 15 thru_hole oval (at 0 17.7796) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 82 /display/DB9)) + (net 74 /display/DB9)) (pad 16 thru_hole oval (at 2.54 17.7796) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 83 /display/DB7)) + (net 75 /display/DB7)) (pad 17 thru_hole oval (at 0 20.3196) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 84 /display/DB10)) + (net 76 /display/DB10)) (pad 18 thru_hole oval (at 2.54 20.3196) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 154 /FSMC/T_CLK)) + (net 144 /FSMC/T_CLK)) (pad 19 thru_hole oval (at 0 22.8596) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 85 /display/DB11)) + (net 77 /display/DB11)) (pad 20 thru_hole oval (at 2.54 22.8596) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 153 /FSMC/T_CS)) + (net 143 /FSMC/T_CS)) (pad 21 thru_hole oval (at 0 25.3996) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 86 /display/DB12)) + (net 78 /display/DB12)) (pad 22 thru_hole oval (at 2.54 25.3996) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 156 /FSMC/T_DIN)) + (net 146 /FSMC/T_DIN)) (pad 23 thru_hole oval (at 0 27.9396) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 87 /display/DB13)) + (net 79 /display/DB13)) (pad 24 thru_hole oval (at 2.54 27.9396) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 93 /display/T_BUSY)) + (net 85 /display/T_BUSY)) (pad 25 thru_hole oval (at 0 30.4796) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 88 /display/DB14)) + (net 80 /display/DB14)) (pad 26 thru_hole oval (at 2.54 30.4796) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 155 /FSMC/T_DOUT)) + (net 145 /FSMC/T_DOUT)) (pad 27 thru_hole oval (at 0 33.0196) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 89 /display/DB15)) + (net 81 /display/DB15)) (pad 28 thru_hole oval (at 2.54 33.0196) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 94 /display/T_IRQ)) + (net 86 /display/T_IRQ)) (pad 29 thru_hole oval (at 0 35.5596) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 90 /display/CS)) + (net 82 /display/CS)) (pad 30 thru_hole oval (at 2.54 35.5596) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 157 "Net-(U6-Pad30)")) + (net 147 "Net-(U6-Pad30)")) (pad 31 thru_hole oval (at 0 38.0996) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 65 "Net-(U6-Pad31)")) + (net 57 "Net-(U6-Pad31)")) (pad 32 thru_hole oval (at 2.54 38.0996) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 158 "Net-(U6-Pad32)")) + (net 148 "Net-(U6-Pad32)")) (pad 33 thru_hole oval (at 0 40.6396) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 91 /display/RST)) + (net 83 /display/RST)) (pad 34 thru_hole oval (at 2.54 40.6396) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 159 "Net-(U6-Pad34)")) + (net 149 "Net-(U6-Pad34)")) (pad 35 thru_hole oval (at 0 43.1796) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 66 "Net-(U6-Pad35)")) + (net 58 "Net-(U6-Pad35)")) (pad 36 thru_hole oval (at 2.54 43.1796) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 160 "Net-(U6-Pad36)")) + (net 150 "Net-(U6-Pad36)")) (pad 37 thru_hole oval (at 0 45.7196) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 67 "Net-(R14-Pad1)")) + (net 59 "Net-(R14-Pad1)")) (pad 38 thru_hole oval (at 2.54 45.7196) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 68 "Net-(U6-Pad38)")) + (net 60 "Net-(U6-Pad38)")) (pad 39 thru_hole oval (at 0 48.2596) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 69 "Net-(U6-Pad39)")) + (net 61 "Net-(U6-Pad39)")) (pad 40 thru_hole oval (at 2.54 48.2596) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) - (net 70 "Net-(U6-Pad40)")) + (net 62 "Net-(U6-Pad40)")) (pad "" np_thru_hole circle (at 9.1 -2.775) (size 7 7) (drill 3) (layers *.Cu *.Mask F.SilkS)) (pad "" np_thru_hole circle (at 9.1 51.025) (size 7 7) (drill 3) (layers *.Cu *.Mask F.SilkS)) (pad "" np_thru_hole circle (at 80.1 -2.775) (size 7 7) (drill 3) (layers *.Cu *.Mask F.SilkS)) @@ -641,433 +951,113 @@ (pad 1 smd rect (at 0 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) (net 4 VFPGA33)) (pad 2 smd rect (at 0.8 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 95 /sdram/DQ0)) + (net 87 /sdram/DQ0)) (pad 3 smd rect (at 1.6 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (pad 4 smd rect (at 2.4 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 96 /sdram/DQ1)) + (net 88 /sdram/DQ1)) (pad 5 smd rect (at 3.2 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 97 /sdram/DQ2)) + (net 89 /sdram/DQ2)) (pad 6 smd rect (at 4 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (pad 7 smd rect (at 4.8 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 98 /sdram/DQ3)) + (net 90 /sdram/DQ3)) (pad 8 smd rect (at 5.6 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 99 /sdram/DQ4)) + (net 91 /sdram/DQ4)) (pad 9 smd rect (at 6.4 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (pad 10 smd rect (at 7.2 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 100 /sdram/DQ5)) + (net 92 /sdram/DQ5)) (pad 11 smd rect (at 8 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 101 /sdram/DQ6)) + (net 93 /sdram/DQ6)) (pad 12 smd rect (at 8.8 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (pad 13 smd rect (at 9.6 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 102 /sdram/DQ7)) + (net 94 /sdram/DQ7)) (pad 14 smd rect (at 10.4 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) (net 4 VFPGA33)) (pad 15 smd rect (at 11.2 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 103 /sdram/DQML)) + (net 95 /sdram/DQML)) (pad 16 smd rect (at 12 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 104 /sdram/WE)) + (net 96 /sdram/WE)) (pad 17 smd rect (at 12.8 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 105 /sdram/CAS)) + (net 97 /sdram/CAS)) (pad 18 smd rect (at 13.6 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 106 /sdram/RAS)) + (net 98 /sdram/RAS)) (pad 19 smd rect (at 14.4 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 107 /sdram/CS)) + (net 99 /sdram/CS)) (pad 20 smd rect (at 15.2 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 108 /sdram/BA0)) + (net 100 /sdram/BA0)) (pad 21 smd rect (at 16 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 109 /sdram/BA1)) + (net 101 /sdram/BA1)) (pad 22 smd rect (at 16.8 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 110 /sdram/A10)) + (net 102 /sdram/A10)) (pad 23 smd rect (at 17.6 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 111 /sdram/A0)) + (net 103 /sdram/A0)) (pad 24 smd rect (at 18.4 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 112 /sdram/A1)) + (net 104 /sdram/A1)) (pad 25 smd rect (at 19.2 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 113 /sdram/A2)) + (net 105 /sdram/A2)) (pad 26 smd rect (at 20 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 114 /sdram/A3)) + (net 106 /sdram/A3)) (pad 27 smd rect (at 20.8 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) (net 4 VFPGA33)) (pad 28 smd rect (at 20.8 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) (net 4 VFPGA33)) (pad 29 smd rect (at 20 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 115 /sdram/A4)) + (net 107 /sdram/A4)) (pad 30 smd rect (at 19.2 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 116 /sdram/A5)) + (net 108 /sdram/A5)) (pad 31 smd rect (at 18.4 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 117 /sdram/A6)) + (net 109 /sdram/A6)) (pad 32 smd rect (at 17.6 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 118 /sdram/A7)) + (net 110 /sdram/A7)) (pad 33 smd rect (at 16.8 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 119 /sdram/A8)) + (net 111 /sdram/A8)) (pad 34 smd rect (at 16 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 120 /sdram/A9)) + (net 112 /sdram/A9)) (pad 35 smd rect (at 15.2 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 121 /sdram/A11)) + (net 113 /sdram/A11)) (pad 36 smd rect (at 14.4 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 122 "Net-(U7-Pad36)")) + (net 114 "Net-(U7-Pad36)")) (pad 37 smd rect (at 13.6 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 123 /sdram/CKE)) + (net 115 /sdram/CKE)) (pad 38 smd rect (at 12.8 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 124 /sdram/CLK)) + (net 116 /sdram/CLK)) (pad 39 smd rect (at 12 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 125 /sdram/DQMH)) + (net 117 /sdram/DQMH)) (pad 40 smd rect (at 11.2 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 126 "Net-(U7-Pad40)")) + (net 118 "Net-(U7-Pad40)")) (pad 41 smd rect (at 10.4 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) (net 4 VFPGA33)) (pad 42 smd rect (at 9.6 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 127 /sdram/DQ8)) + (net 119 /sdram/DQ8)) (pad 43 smd rect (at 8.8 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (pad 44 smd rect (at 8 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 128 /sdram/DQ9)) + (net 120 /sdram/DQ9)) (pad 45 smd rect (at 7.2 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 129 /sdram/DQ10)) + (net 121 /sdram/DQ10)) (pad 46 smd rect (at 6.4 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (pad 47 smd rect (at 5.6 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 130 /sdram/DQ11)) + (net 122 /sdram/DQ11)) (pad 48 smd rect (at 4.8 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 131 /sdram/DQ12)) + (net 123 /sdram/DQ12)) (pad 49 smd rect (at 4 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (pad 50 smd rect (at 3.2 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 132 /sdram/DQ13)) + (net 124 /sdram/DQ13)) (pad 51 smd rect (at 2.4 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 133 /sdram/DQ14)) + (net 125 /sdram/DQ14)) (pad 52 smd rect (at 1.6 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (pad 53 smd rect (at 0.8 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) - (net 134 /sdram/DQ15)) + (net 126 /sdram/DQ15)) (pad 54 smd rect (at 0 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask) (net 4 VFPGA33)) ) - (module Housings_QFP:LQFP-144_20x20mm_Pitch0.5mm (layer F.Cu) (tedit 54130A77) (tstamp 56C45027) - (at 131.443728 62.795542 180) - (descr "144-Lead Plastic Low Profile Quad Flatpack (PL) - 20x20x1.40 mm Body [LQFP], 2.00 mm Footprint (see Microchip Packaging Specification 00000049BS.pdf)") - (tags "QFP 0.5") - (path /563244F7/56323459) - (attr smd) - (fp_text reference U3 (at 0 -12.475 180) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value LFXP2-5E-6TN144C (at 0 12.475 180) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start -11.75 -11.75) (end -11.75 11.75) (layer F.CrtYd) (width 0.05)) - (fp_line (start 11.75 -11.75) (end 11.75 11.75) (layer F.CrtYd) (width 0.05)) - (fp_line (start -11.75 -11.75) (end 11.75 -11.75) (layer F.CrtYd) (width 0.05)) - (fp_line (start -11.75 11.75) (end 11.75 11.75) (layer F.CrtYd) (width 0.05)) - (fp_line (start -10.175 -10.175) (end -10.175 -9.125) (layer F.SilkS) (width 0.15)) - (fp_line (start 10.175 -10.175) (end 10.175 -9.125) (layer F.SilkS) (width 0.15)) - (fp_line (start 10.175 10.175) (end 10.175 9.125) (layer F.SilkS) (width 0.15)) - (fp_line (start -10.175 10.175) (end -10.175 9.125) (layer F.SilkS) (width 0.15)) - (fp_line (start -10.175 -10.175) (end -9.125 -10.175) (layer F.SilkS) (width 0.15)) - (fp_line (start -10.175 10.175) (end -9.125 10.175) (layer F.SilkS) (width 0.15)) - (fp_line (start 10.175 10.175) (end 9.125 10.175) (layer F.SilkS) (width 0.15)) - (fp_line (start 10.175 -10.175) (end 9.125 -10.175) (layer F.SilkS) (width 0.15)) - (fp_line (start -10.175 -9.125) (end -11.475 -9.125) (layer F.SilkS) (width 0.15)) - (pad 1 smd rect (at -10.7 -8.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 58 /FSMC/BL0_N)) - (pad 2 smd rect (at -10.7 -8.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 59 /FSMC/BL1_N)) - (pad 3 smd rect (at -10.7 -7.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) - (pad 4 smd rect (at -10.7 -7.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 4 VFPGA33)) - (pad 5 smd rect (at -10.7 -6.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - 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(at -10.7 -1.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 178 /audio/ACLK)) - (pad 16 smd rect (at -10.7 -1.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 186 /sdram/CLK_50M)) - (pad 17 smd rect (at -10.7 -0.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 176 /audio/AWS)) - (pad 18 smd rect (at -10.7 -0.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 175 /audio/ABCK)) - (pad 19 smd rect (at -10.7 0.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 115 /sdram/A4)) - (pad 20 smd rect (at -10.7 0.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 116 /sdram/A5)) - (pad 21 smd rect (at -10.7 1.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 117 /sdram/A6)) - (pad 22 smd rect (at -10.7 1.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 118 /sdram/A7)) - (pad 23 smd rect (at -10.7 2.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 4 VFPGA33)) - (pad 24 smd rect (at -10.7 2.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 5 +1V2)) - (pad 25 smd rect (at -10.7 3.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 167 /powersupply/TOE)) - (pad 26 smd rect (at -10.7 3.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 168 /powersupply/CFG0)) - (pad 27 smd rect (at -10.7 4.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 119 /sdram/A8)) - (pad 28 smd rect (at -10.7 4.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 120 /sdram/A9)) - (pad 29 smd rect (at -10.7 5.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 121 /sdram/A11)) - (pad 30 smd rect (at -10.7 5.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 114 /sdram/A3)) - (pad 31 smd rect (at -10.7 6.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 113 /sdram/A2)) - (pad 32 smd rect (at -10.7 6.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 112 /sdram/A1)) - (pad 33 smd rect (at -10.7 7.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 4 VFPGA33)) - (pad 34 smd rect (at -10.7 7.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) - (pad 35 smd rect (at -10.7 8.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 110 /sdram/A10)) - (pad 36 smd rect (at -10.7 8.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 111 /sdram/A0)) - (pad 37 smd rect (at -8.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 109 /sdram/BA1)) - (pad 38 smd rect (at -8.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 108 /sdram/BA0)) - (pad 39 smd rect (at -7.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 107 /sdram/CS)) - (pad 40 smd rect (at -7.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 106 /sdram/RAS)) - (pad 41 smd rect (at -6.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) - (pad 42 smd rect (at -6.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 4 VFPGA33)) - (pad 43 smd rect (at -5.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 123 /sdram/CKE)) - (pad 44 smd rect (at -5.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 105 /sdram/CAS)) - (pad 45 smd rect (at -4.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 124 /sdram/CLK)) - (pad 46 smd rect (at -4.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 104 /sdram/WE)) - (pad 47 smd rect (at -3.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 125 /sdram/DQMH)) - (pad 48 smd rect (at -3.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 103 /sdram/DQML)) - (pad 49 smd rect (at -2.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 4 VFPGA33)) - (pad 50 smd rect (at -2.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 102 /sdram/DQ7)) - (pad 51 smd rect (at -1.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) - (pad 52 smd rect (at -1.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 127 /sdram/DQ8)) - (pad 53 smd rect (at -0.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 101 /sdram/DQ6)) - (pad 54 smd rect (at -0.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 128 /sdram/DQ9)) - (pad 55 smd rect (at 0.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 100 /sdram/DQ5)) - (pad 56 smd rect (at 0.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 129 /sdram/DQ10)) - (pad 57 smd rect (at 1.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 99 /sdram/DQ4)) - (pad 58 smd rect (at 1.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 130 /sdram/DQ11)) - (pad 59 smd rect (at 2.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 5 +1V2)) - (pad 60 smd rect (at 2.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 4 VFPGA33)) - (pad 61 smd rect (at 3.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 98 /sdram/DQ3)) - (pad 62 smd rect (at 3.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 131 /sdram/DQ12)) - (pad 63 smd rect (at 4.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 4 VFPGA33)) - (pad 64 smd rect (at 4.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) - (pad 65 smd rect (at 5.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 97 /sdram/DQ2)) - (pad 66 smd rect (at 5.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 132 /sdram/DQ13)) - (pad 67 smd rect (at 6.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 4 VFPGA33)) - (pad 68 smd rect (at 6.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) - (pad 69 smd rect (at 7.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 96 /sdram/DQ1)) - (pad 70 smd rect (at 7.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 133 /sdram/DQ14)) - (pad 71 smd rect (at 8.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 95 /sdram/DQ0)) - (pad 72 smd rect (at 8.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 134 /sdram/DQ15)) - (pad 73 smd rect (at 10.7 8.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 92 "Net-(U3-Pad73)")) - (pad 74 smd rect (at 10.7 8.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 71 /display/DB0)) - (pad 75 smd rect (at 10.7 7.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) - (pad 76 smd rect (at 10.7 7.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 4 VFPGA33)) - (pad 77 smd rect (at 10.7 6.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 72 /display/DB1)) - (pad 78 smd rect (at 10.7 6.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 73 /display/DB2)) - (pad 79 smd rect (at 10.7 5.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 142 /debug/FTMS)) - (pad 80 smd rect (at 10.7 5.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 143 /debug/FTDI)) - (pad 81 smd rect (at 10.7 4.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 144 /debug/FTCK)) - (pad 82 smd rect (at 10.7 4.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 145 /debug/FTDO)) - (pad 83 smd rect (at 10.7 3.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 4 VFPGA33)) - (pad 84 smd rect (at 10.7 3.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 5 +1V2)) - (pad 85 smd rect (at 10.7 2.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 4 VFPGA33)) - (pad 86 smd rect (at 10.7 2.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) - (pad 87 smd rect (at 10.7 1.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 74 /display/RS)) - (pad 88 smd rect (at 10.7 1.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 75 /display/DB3)) - (pad 89 smd rect (at 10.7 0.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 76 /display/WR)) - (pad 90 smd rect (at 10.7 0.25 180) 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F.Paste F.Mask) - (net 84 /display/DB10)) - (pad 100 smd rect (at 10.7 -4.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 85 /display/DB11)) - (pad 101 smd rect (at 10.7 -5.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 86 /display/DB12)) - (pad 102 smd rect (at 10.7 -5.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 87 /display/DB13)) - (pad 103 smd rect (at 10.7 -6.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 88 /display/DB14)) - (pad 104 smd rect (at 10.7 -6.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 89 /display/DB15)) - (pad 105 smd rect (at 10.7 -7.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 4 VFPGA33)) - (pad 106 smd rect (at 10.7 -7.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) - (pad 107 smd rect (at 10.7 -8.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 90 /display/CS)) - (pad 108 smd rect (at 10.7 -8.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 91 /display/RST)) - (pad 109 smd rect (at 8.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 40 /FSMC/A18)) - (pad 110 smd rect (at 8.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 39 /FSMC/A17)) - (pad 111 smd rect (at 7.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) - (pad 112 smd rect (at 7.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 4 VFPGA33)) - (pad 113 smd rect (at 6.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 38 /FSMC/A16)) - (pad 114 smd rect (at 6.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 135 "Net-(U3-Pad114)")) - (pad 115 smd rect (at 5.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 136 "Net-(U3-Pad115)")) - (pad 116 smd rect (at 5.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 46 /FSMC/CLK)) - (pad 117 smd rect (at 4.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 4 VFPGA33)) - (pad 118 smd rect (at 4.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 5 +1V2)) - (pad 119 smd rect (at 3.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 37 /FSMC/DA15)) - (pad 120 smd rect (at 3.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 36 /FSMC/DA14)) - (pad 121 smd rect (at 2.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 1 /FSMC/DA13)) - (pad 122 smd rect (at 2.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 41 /FSMC/DA0)) - (pad 123 smd rect (at 1.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 42 /FSMC/DA1)) - (pad 124 smd rect (at 1.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 44 /FSMC/DA2)) - (pad 125 smd rect (at 0.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 45 /FSMC/DA3)) - (pad 126 smd rect (at 0.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) - (pad 127 smd rect (at -0.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 33 /FSMC/DA12)) - (pad 128 smd rect (at -0.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 4 VFPGA33)) - (pad 129 smd rect (at -1.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 32 /FSMC/DA11)) - (pad 130 smd rect (at -1.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 31 /FSMC/DA10)) - (pad 131 smd rect (at -2.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 30 /FSMC/DA9)) - (pad 132 smd rect (at -2.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 29 /FSMC/DA8)) - (pad 133 smd rect (at -3.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 28 /FSMC/DA7)) - (pad 134 smd rect (at -3.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 27 /FSMC/DA6)) - (pad 135 smd rect (at -4.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) - (pad 136 smd rect (at -4.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 4 VFPGA33)) - (pad 137 smd rect (at -5.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 26 /FSMC/DA5)) - (pad 138 smd rect (at -5.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 25 /FSMC/DA4)) - (pad 139 smd rect (at -6.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) - (pad 140 smd rect (at -6.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 4 VFPGA33)) - (pad 141 smd rect (at -7.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 47 /FSMC/OE_N)) - (pad 142 smd rect (at -7.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 48 /FSMC/WE_N)) - (pad 143 smd rect (at -8.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 49 /FSMC/WAIT_N)) - (pad 144 smd rect (at -8.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 2 /FSMC/E1_N)) - (model Housings_QFP.3dshapes/LQFP-144_20x20mm_Pitch0.5mm.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) - ) - ) - (module TO_SOT_Packages_SMD:SOT-223 (layer F.Cu) (tedit 0) (tstamp 56C44F93) (at 156.198 70.4 270) (descr "module CMS SOT223 4 pins") @@ -1094,7 +1084,7 @@ (pad 3 smd rect (at 2.286 3.302 270) (size 1.016 2.032) (layers F.Cu F.Paste F.Mask) (net 4 VFPGA33)) (pad 1 smd rect (at -2.286 3.302 270) (size 1.016 2.032) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (model TO_SOT_Packages_SMD.3dshapes/SOT-223.wrl (at (xyz 0 0 0)) (scale (xyz 0.4 0.4 0.4)) @@ -1123,7 +1113,7 @@ (pad 1 smd rect (at -0.75 0 90) (size 0.8 0.75) (layers B.Cu B.Paste B.Mask) (net 4 VFPGA33)) (pad 2 smd rect (at 0.75 0 90) (size 0.8 0.75) (layers B.Cu B.Paste B.Mask) - (net 61 GND)) + (net 53 GND)) (model Capacitors_SMD.3dshapes/C_0603.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -1152,7 +1142,7 @@ (pad 1 smd rect (at -0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask) (net 4 VFPGA33)) (pad 2 smd rect (at 0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -1196,7 +1186,7 @@ (pad 5 smd rect (at -7.9 -4 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) (net 10 /FSMC/A22)) (pad 6 smd rect (at -7.9 -3.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 60 VSTM33)) + (net 52 VSTM33)) (pad 7 smd rect (at -7.9 -3 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) (net 11 "Net-(U4-Pad7)")) (pad 8 smd rect (at -7.9 -2.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) @@ -1204,187 +1194,187 @@ (pad 9 smd rect (at -7.9 -2 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) (net 13 "Net-(U4-Pad9)")) (pad 10 smd rect (at -7.9 -1.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (pad 11 smd rect (at -7.9 -1 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 60 VSTM33)) + (net 52 VSTM33)) (pad 12 smd rect (at -7.9 -0.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 146 /debug/OSCIN)) + (net 136 /debug/OSCIN)) (pad 13 smd rect (at -7.9 0 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 147 /debug/OSCOUT)) + (net 137 /debug/OSCOUT)) (pad 14 smd rect (at -7.9 0.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 14 "Net-(U4-Pad14)")) + (net 185 /debug/NRST)) (pad 15 smd rect (at -7.9 1 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 163 /sdcard/SW_C)) + (net 153 /sdcard/SW_C)) (pad 16 smd rect (at -7.9 1.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 164 /sdcard/SW_D)) + (net 154 /sdcard/SW_D)) (pad 17 smd rect (at -7.9 2 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 162 /sdcard/SW_A)) + (net 152 /sdcard/SW_A)) (pad 18 smd rect (at -7.9 2.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 161 /sdcard/SW_B)) + (net 151 /sdcard/SW_B)) (pad 19 smd rect (at -7.9 3 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 60 VSTM33)) + (net 52 VSTM33)) (pad 20 smd rect (at -7.9 3.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (pad 21 smd rect (at -7.9 4 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 60 VSTM33)) + (net 52 VSTM33)) (pad 22 smd rect (at -7.9 4.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 60 VSTM33)) + (net 52 VSTM33)) (pad 23 smd rect (at -7.9 5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 169 /userif/RGBLED0)) + (net 157 /userif/RGBLED0)) (pad 24 smd rect (at -7.9 5.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 170 /userif/RGBLED1)) + (net 158 /userif/RGBLED1)) (pad 25 smd rect (at -7.95 6 180) (size 1.4 0.28) (layers F.Cu F.Paste F.Mask) - (net 171 /userif/RGBLED2)) + (net 159 /userif/RGBLED2)) (pad 26 smd rect (at -6 7.95 270) (size 1.4 0.28) (layers F.Cu F.Paste F.Mask) - (net 15 "Net-(U4-Pad26)")) + (net 186 /powersupply/SYS_VOLTAGE)) (pad 27 smd rect (at -5.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (pad 28 smd rect (at -5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 60 VSTM33)) + (net 52 VSTM33)) (pad 29 smd rect (at -4.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 16 "Net-(U4-Pad29)")) + (net 179 /powersupply/USB_PRESENT_N)) (pad 30 smd rect (at -4 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 17 "Net-(U4-Pad30)")) + (net 176 /powersupply/CHG_ACTIVE_N)) (pad 31 smd rect (at -3.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 18 "Net-(U4-Pad31)")) + (net 187 /powersupply/FPGA_ENABLE_N)) (pad 32 smd rect (at -3 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 19 "Net-(U4-Pad32)")) + (net 188 /powersupply/CHARGE_ENABLE)) (pad 33 smd rect (at -2.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 20 "Net-(U4-Pad33)")) + (net 14 "Net-(U4-Pad33)")) (pad 34 smd rect (at -2 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 21 "Net-(U4-Pad34)")) + (net 15 "Net-(U4-Pad34)")) (pad 35 smd rect (at -1.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 22 "Net-(U4-Pad35)")) + (net 16 "Net-(U4-Pad35)")) (pad 36 smd rect (at -1 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 23 "Net-(U4-Pad36)")) + (net 17 "Net-(U4-Pad36)")) (pad 37 smd rect (at -0.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 24 /FSMC/BOOT1)) + (net 18 /FSMC/BOOT1)) (pad 38 smd rect (at 0 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 25 /FSMC/DA4)) + (net 19 /FSMC/DA4)) (pad 39 smd rect (at 0.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 26 /FSMC/DA5)) + (net 20 /FSMC/DA5)) (pad 40 smd rect (at 1 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 27 /FSMC/DA6)) + (net 21 /FSMC/DA6)) (pad 41 smd rect (at 1.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 28 /FSMC/DA7)) + (net 22 /FSMC/DA7)) (pad 42 smd rect (at 2 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 29 /FSMC/DA8)) + (net 23 /FSMC/DA8)) (pad 43 smd rect (at 2.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 30 /FSMC/DA9)) + (net 24 /FSMC/DA9)) (pad 44 smd rect (at 3 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 31 /FSMC/DA10)) + (net 25 /FSMC/DA10)) (pad 45 smd rect (at 3.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 32 /FSMC/DA11)) + (net 26 /FSMC/DA11)) (pad 46 smd rect (at 4 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 33 /FSMC/DA12)) + (net 27 /FSMC/DA12)) (pad 47 smd rect (at 4.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 34 "Net-(U4-Pad47)")) + (net 28 "Net-(U4-Pad47)")) (pad 48 smd rect (at 5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 35 "Net-(U4-Pad48)")) + (net 29 "Net-(U4-Pad48)")) (pad 49 smd rect (at 5.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 62 /powersupply/VCAP1)) + (net 54 /powersupply/VCAP1)) (pad 50 smd rect (at 6 7.95 270) (size 1.4 0.28) (layers F.Cu F.Paste F.Mask) - (net 60 VSTM33)) + (net 52 VSTM33)) (pad 51 smd rect (at 7.95 6 180) (size 1.4 0.28) (layers F.Cu F.Paste F.Mask) - (net 153 /FSMC/T_CS)) + (net 143 /FSMC/T_CS)) (pad 52 smd rect (at 7.9 5.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 154 /FSMC/T_CLK)) + (net 144 /FSMC/T_CLK)) (pad 53 smd rect (at 7.9 5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 155 /FSMC/T_DOUT)) + (net 145 /FSMC/T_DOUT)) (pad 54 smd rect (at 7.9 4.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 156 /FSMC/T_DIN)) + (net 146 /FSMC/T_DIN)) (pad 55 smd rect (at 7.9 4 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) (net 1 /FSMC/DA13)) (pad 56 smd rect (at 7.9 3.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 36 /FSMC/DA14)) + (net 30 /FSMC/DA14)) (pad 57 smd rect (at 7.9 3 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 37 /FSMC/DA15)) + (net 31 /FSMC/DA15)) (pad 58 smd rect (at 7.9 2.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 38 /FSMC/A16)) + (net 32 /FSMC/A16)) (pad 59 smd rect (at 7.9 2 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 39 /FSMC/A17)) + (net 33 /FSMC/A17)) (pad 60 smd rect (at 7.9 1.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 40 /FSMC/A18)) + (net 34 /FSMC/A18)) (pad 61 smd rect (at 7.9 1 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 41 /FSMC/DA0)) + (net 35 /FSMC/DA0)) (pad 62 smd rect (at 7.9 0.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 42 /FSMC/DA1)) + (net 36 /FSMC/DA1)) (pad 63 smd rect (at 7.9 0 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 93 /display/T_BUSY)) + (net 85 /display/T_BUSY)) (pad 64 smd rect (at 7.9 -0.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 94 /display/T_IRQ)) + (net 86 /display/T_IRQ)) (pad 65 smd rect (at 7.9 -1 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 139 /sdcard/SDIO_D0)) + (net 129 /sdcard/SDIO_D0)) (pad 66 smd rect (at 7.9 -1.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 140 /sdcard/SDIO_D1)) + (net 130 /sdcard/SDIO_D1)) (pad 67 smd rect (at 7.9 -2 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 150 /userif/SW_UP)) + (net 140 /userif/SW_UP)) (pad 68 smd rect (at 7.9 -2.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 152 /userif/SW_RIGHT)) + (net 142 /userif/SW_RIGHT)) (pad 69 smd rect (at 7.9 -3 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 149 /userif/SW_LEFT)) + (net 139 /userif/SW_LEFT)) (pad 70 smd rect (at 7.9 -3.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 151 /userif/SW_DOWN)) + (net 141 /userif/SW_DOWN)) (pad 71 smd rect (at 7.9 -4 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 43 "Net-(U4-Pad71)")) + (net 183 /sdcard/SDCARD_DETECT)) (pad 72 smd rect (at 7.9 -4.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 172 /debug/JTMS)) + (net 160 /debug/JTMS)) (pad 73 smd rect (at 7.9 -5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 63 /powersupply/VCAP2)) + (net 55 /powersupply/VCAP2)) (pad 74 smd rect (at 7.9 -5.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (pad 75 smd rect (at 7.95 -6 180) (size 1.4 0.28) (layers F.Cu F.Paste F.Mask) - (net 60 VSTM33)) + (net 52 VSTM33)) (pad 76 smd rect (at 6 -7.95 270) (size 1.4 0.28) (layers F.Cu F.Paste F.Mask) - (net 173 /debug/JTCK)) + (net 161 /debug/JTCK)) (pad 77 smd rect (at 5.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 174 /debug/JTDI)) + (net 162 /debug/JTDI)) (pad 78 smd rect (at 5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 141 /sdcard/SDIO_D2)) + (net 131 /sdcard/SDIO_D2)) (pad 79 smd rect (at 4.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 137 /sdcard/SDIO_D3)) + (net 127 /sdcard/SDIO_D3)) (pad 80 smd rect (at 4 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 138 /sdcard/SDIO_CLK)) + (net 128 /sdcard/SDIO_CLK)) (pad 81 smd rect (at 3.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 44 /FSMC/DA2)) + (net 37 /FSMC/DA2)) (pad 82 smd rect (at 3 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 45 /FSMC/DA3)) + (net 38 /FSMC/DA3)) (pad 83 smd rect (at 2.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 148 /FSMC/SDIO_CMD)) + (net 138 /FSMC/SDIO_CMD)) (pad 84 smd rect (at 2 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 46 /FSMC/CLK)) + (net 39 /FSMC/CLK)) (pad 85 smd rect (at 1.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 47 /FSMC/OE_N)) + (net 40 /FSMC/OE_N)) (pad 86 smd rect (at 1 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 48 /FSMC/WE_N)) + (net 41 /FSMC/WE_N)) (pad 87 smd rect (at 0.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 49 /FSMC/WAIT_N)) + (net 42 /FSMC/WAIT_N)) (pad 88 smd rect (at 0 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) (net 2 /FSMC/E1_N)) (pad 89 smd rect (at -0.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 50 /FSMC/JTDO)) + (net 43 /FSMC/JTDO)) (pad 90 smd rect (at -1 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 51 /FSMC/JRST_N)) + (net 44 /FSMC/JRST_N)) (pad 91 smd rect (at -1.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 52 "Net-(U4-Pad91)")) + (net 45 "Net-(U4-Pad91)")) (pad 92 smd rect (at -2 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 53 "Net-(U4-Pad92)")) + (net 46 "Net-(U4-Pad92)")) (pad 93 smd rect (at -2.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 54 /FSMC/ADV_N)) + (net 47 /FSMC/ADV_N)) (pad 94 smd rect (at -3 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 55 "Net-(U4-Pad94)")) + (net 189 /debug/BOOT0)) (pad 95 smd rect (at -3.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 56 "Net-(U4-Pad95)")) + (net 48 "Net-(U4-Pad95)")) (pad 96 smd rect (at -4 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 57 "Net-(U4-Pad96)")) + (net 49 "Net-(U4-Pad96)")) (pad 97 smd rect (at -4.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 58 /FSMC/BL0_N)) + (net 50 /FSMC/BL0_N)) (pad 98 smd rect (at -5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 59 /FSMC/BL1_N)) + (net 51 /FSMC/BL1_N)) (pad 99 smd rect (at -5.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (pad 100 smd rect (at -6 -7.95 270) (size 1.4 0.28) (layers F.Cu F.Paste F.Mask) - (net 60 VSTM33)) + (net 52 VSTM33)) (model Housings_QFP.3dshapes/LQFP-100_14x14mm_Pitch0.5mm.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -1407,13 +1397,13 @@ (fp_line (start -3.1 3.1) (end 3.1 3.1) (layer F.SilkS) (width 0.15)) (fp_line (start -3.1 -3.1) (end -3.1 3.1) (layer F.SilkS) (width 0.15)) (pad 1 smd rect (at -3.975 -2.25 90) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 149 /userif/SW_LEFT)) + (net 139 /userif/SW_LEFT)) (pad 1 smd rect (at 3.975 -2.25 90) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 149 /userif/SW_LEFT)) + (net 139 /userif/SW_LEFT)) (pad 2 smd rect (at -3.975 2.25 90) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (pad 2 smd rect (at 3.975 2.25 90) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) ) (module smd:Tactile_Switch (layer F.Cu) (tedit 56A7EE42) (tstamp 56C768F6) @@ -1431,13 +1421,13 @@ (fp_line (start -3.1 3.1) (end 3.1 3.1) (layer F.SilkS) (width 0.15)) (fp_line (start -3.1 -3.1) (end -3.1 3.1) (layer F.SilkS) (width 0.15)) (pad 1 smd rect (at -3.975 -2.25 270) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 150 /userif/SW_UP)) + (net 140 /userif/SW_UP)) (pad 1 smd rect (at 3.975 -2.25 270) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 150 /userif/SW_UP)) + (net 140 /userif/SW_UP)) (pad 2 smd rect (at -3.975 2.25 270) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (pad 2 smd rect (at 3.975 2.25 270) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) ) (module smd:Tactile_Switch (layer F.Cu) (tedit 56A7EE42) (tstamp 56C768FE) @@ -1455,13 +1445,13 @@ (fp_line (start -3.1 3.1) (end 3.1 3.1) (layer F.SilkS) (width 0.15)) (fp_line (start -3.1 -3.1) (end -3.1 3.1) (layer F.SilkS) (width 0.15)) (pad 1 smd rect (at -3.975 -2.25 270) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 151 /userif/SW_DOWN)) + (net 141 /userif/SW_DOWN)) (pad 1 smd rect (at 3.975 -2.25 270) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 151 /userif/SW_DOWN)) + (net 141 /userif/SW_DOWN)) (pad 2 smd rect (at -3.975 2.25 270) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (pad 2 smd rect (at 3.975 2.25 270) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) ) (module smd:Tactile_Switch (layer F.Cu) (tedit 56A7EE42) (tstamp 56C76906) @@ -1479,13 +1469,13 @@ (fp_line (start -3.1 3.1) (end 3.1 3.1) (layer F.SilkS) (width 0.15)) (fp_line (start -3.1 -3.1) (end -3.1 3.1) (layer F.SilkS) (width 0.15)) (pad 1 smd rect (at -3.975 -2.25 90) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 152 /userif/SW_RIGHT)) + (net 142 /userif/SW_RIGHT)) (pad 1 smd rect (at 3.975 -2.25 90) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 152 /userif/SW_RIGHT)) + (net 142 /userif/SW_RIGHT)) (pad 2 smd rect (at -3.975 2.25 90) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (pad 2 smd rect (at 3.975 2.25 90) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) ) (module smd:Tactile_Switch (layer F.Cu) (tedit 56A7EE42) (tstamp 56C7690E) @@ -1503,13 +1493,13 @@ (fp_line (start -3.1 3.1) (end 3.1 3.1) (layer F.SilkS) (width 0.15)) (fp_line (start -3.1 -3.1) (end -3.1 3.1) (layer F.SilkS) (width 0.15)) (pad 1 smd rect (at -3.975 -2.25 270) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 161 /sdcard/SW_B)) + (net 151 /sdcard/SW_B)) (pad 1 smd rect (at 3.975 -2.25 270) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 161 /sdcard/SW_B)) + (net 151 /sdcard/SW_B)) (pad 2 smd rect (at -3.975 2.25 270) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (pad 2 smd rect (at 3.975 2.25 270) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) ) (module smd:Tactile_Switch (layer F.Cu) (tedit 56A7EE42) (tstamp 56C76916) @@ -1527,13 +1517,13 @@ (fp_line (start -3.1 3.1) (end 3.1 3.1) (layer F.SilkS) (width 0.15)) (fp_line (start -3.1 -3.1) (end -3.1 3.1) (layer F.SilkS) (width 0.15)) (pad 1 smd rect (at -3.975 -2.25 90) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 162 /sdcard/SW_A)) + (net 152 /sdcard/SW_A)) (pad 1 smd rect (at 3.975 -2.25 90) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 162 /sdcard/SW_A)) + (net 152 /sdcard/SW_A)) (pad 2 smd rect (at -3.975 2.25 90) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (pad 2 smd rect (at 3.975 2.25 90) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) ) (module smd:Tactile_Switch (layer F.Cu) (tedit 56A7EE42) (tstamp 56C7691E) @@ -1551,13 +1541,13 @@ (fp_line (start -3.1 3.1) (end 3.1 3.1) (layer F.SilkS) (width 0.15)) (fp_line (start -3.1 -3.1) (end -3.1 3.1) (layer F.SilkS) (width 0.15)) (pad 1 smd rect (at -3.975 -2.25 90) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 163 /sdcard/SW_C)) + (net 153 /sdcard/SW_C)) (pad 1 smd rect (at 3.975 -2.25 90) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 163 /sdcard/SW_C)) + (net 153 /sdcard/SW_C)) (pad 2 smd rect (at -3.975 2.25 90) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (pad 2 smd rect (at 3.975 2.25 90) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) ) (module smd:Tactile_Switch (layer F.Cu) (tedit 56A7EE42) (tstamp 56C76926) @@ -1575,13 +1565,13 @@ (fp_line (start -3.1 3.1) (end 3.1 3.1) (layer F.SilkS) (width 0.15)) (fp_line (start -3.1 -3.1) (end -3.1 3.1) (layer F.SilkS) (width 0.15)) (pad 1 smd rect (at -3.975 -2.25 90) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 164 /sdcard/SW_D)) + (net 154 /sdcard/SW_D)) (pad 1 smd rect (at 3.975 -2.25 90) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 164 /sdcard/SW_D)) + (net 154 /sdcard/SW_D)) (pad 2 smd rect (at -3.975 2.25 90) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (pad 2 smd rect (at 3.975 2.25 90) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) ) (module Capacitors_SMD:C_0603 (layer B.Cu) (tedit 5415D631) (tstamp 56C786CF) @@ -1605,7 +1595,7 @@ (pad 1 smd rect (at -0.75 0) (size 0.8 0.75) (layers B.Cu B.Paste B.Mask) (net 5 +1V2)) (pad 2 smd rect (at 0.75 0) (size 0.8 0.75) (layers B.Cu B.Paste B.Mask) - (net 61 GND)) + (net 53 GND)) (model Capacitors_SMD.3dshapes/C_0603.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -1634,7 +1624,7 @@ (pad 1 smd rect (at -0.75 0 270) (size 0.8 0.75) (layers B.Cu B.Paste B.Mask) (net 4 VFPGA33)) (pad 2 smd rect (at 0.75 0 270) (size 0.8 0.75) (layers B.Cu B.Paste B.Mask) - (net 61 GND)) + (net 53 GND)) (model Capacitors_SMD.3dshapes/C_0603.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -1663,7 +1653,7 @@ (pad 1 smd rect (at -0.75 0 270) (size 0.8 0.75) (layers B.Cu B.Paste B.Mask) (net 5 +1V2)) (pad 2 smd rect (at 0.75 0 270) (size 0.8 0.75) (layers B.Cu B.Paste B.Mask) - (net 61 GND)) + (net 53 GND)) (model Capacitors_SMD.3dshapes/C_0603.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -1692,7 +1682,7 @@ (pad 1 smd rect (at -0.75 0 270) (size 0.8 0.75) (layers B.Cu B.Paste B.Mask) (net 4 VFPGA33)) (pad 2 smd rect (at 0.75 0 270) (size 0.8 0.75) (layers B.Cu B.Paste B.Mask) - (net 61 GND)) + (net 53 GND)) (model Capacitors_SMD.3dshapes/C_0603.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -1721,7 +1711,7 @@ (pad 1 smd rect (at -0.75 0 180) (size 0.8 0.75) (layers B.Cu B.Paste B.Mask) (net 5 +1V2)) (pad 2 smd rect (at 0.75 0 180) (size 0.8 0.75) (layers B.Cu B.Paste B.Mask) - (net 61 GND)) + (net 53 GND)) (model Capacitors_SMD.3dshapes/C_0603.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -1749,55 +1739,31 @@ (pad "" np_thru_hole circle (at 4.65 12.35 90) (size 0.9 0.9) (drill 0.762) (layers *.Cu *.Mask B.SilkS)) (pad "" np_thru_hole circle (at 4.65 4.35 90) (size 0.9 0.9) (drill 0.762) (layers *.Cu *.Mask B.SilkS)) (pad 3 smd rect (at 15.2 7.4 90) (size 2.2 0.75) (layers B.Cu B.Paste B.Mask) - (net 148 /FSMC/SDIO_CMD)) + (net 138 /FSMC/SDIO_CMD)) (pad 2 smd rect (at 15.2 6.3 90) (size 2.2 0.75) (layers B.Cu B.Paste B.Mask) - (net 137 /sdcard/SDIO_D3)) + (net 127 /sdcard/SDIO_D3)) (pad 1 smd rect (at 15.2 5.2 90) (size 2.2 0.75) (layers B.Cu B.Paste B.Mask) - (net 141 /sdcard/SDIO_D2)) + (net 131 /sdcard/SDIO_D2)) (pad 4 smd rect (at 15.2 8.5 90) (size 2.2 0.75) (layers B.Cu B.Paste B.Mask) - (net 60 VSTM33)) + (net 52 VSTM33)) (pad 5 smd rect (at 15.2 9.6 90) (size 2.2 0.75) (layers B.Cu B.Paste B.Mask) - (net 138 /sdcard/SDIO_CLK)) + (net 128 /sdcard/SDIO_CLK)) (pad 6 smd rect (at 15.2 10.7 90) (size 2.2 0.75) (layers B.Cu B.Paste B.Mask) - (net 61 GND)) + (net 53 GND)) (pad 7 smd rect (at 15.2 11.8 90) (size 2.2 0.75) (layers B.Cu B.Paste B.Mask) - (net 139 /sdcard/SDIO_D0)) + (net 129 /sdcard/SDIO_D0)) (pad 8 smd rect (at 15.2 12.9 90) (size 2.2 0.75) (layers B.Cu B.Paste B.Mask) - (net 140 /sdcard/SDIO_D1)) + (net 130 /sdcard/SDIO_D1)) (pad 9 smd rect (at 15.2 14 90) (size 2.2 0.6) (layers B.Cu B.Paste B.Mask) - (net 165 "Net-(CON801-Pad9)")) + (net 183 /sdcard/SDCARD_DETECT)) (pad 11 smd rect (at 4.4 -0.5 90) (size 3 2) (layers B.Cu B.Paste B.Mask) - (net 61 GND)) + (net 53 GND)) (pad 10 smd rect (at 14.5 0.25 90) (size 2 2) (layers B.Cu B.Paste B.Mask) - (net 61 GND)) + (net 53 GND)) (pad 12 smd rect (at 4.4 15.2 90) (size 3 2) (layers B.Cu B.Paste B.Mask) - (net 61 GND)) + (net 53 GND)) (pad 13 smd rect (at 14.5 15.55 90) (size 1.5 1.5) (layers B.Cu B.Paste B.Mask) - (net 61 GND)) - ) - - (module smd:Tactile_Switch (layer F.Cu) (tedit 56A7EE42) (tstamp 56C8E543) - (at 39.300981 97.339897) - (path /56C86141/56C90B91) - (fp_text reference SW701 (at 0.1 8.7) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value DOWN (at -8.2 7.8) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_circle (center 0 0) (end 1.4 0.7) (layer F.SilkS) (width 0.15)) - (fp_line (start 3.1 -3.1) (end -3.1 -3.1) (layer F.SilkS) (width 0.15)) - (fp_line (start 3.1 3.1) (end 3.1 -3.1) (layer F.SilkS) (width 0.15)) - (fp_line (start -3.1 3.1) (end 3.1 3.1) (layer F.SilkS) (width 0.15)) - (fp_line (start -3.1 -3.1) (end -3.1 3.1) (layer F.SilkS) (width 0.15)) - (pad 1 smd rect (at -3.975 -2.25) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 166 /userif/BTN_STBY)) - (pad 1 smd rect (at 3.975 -2.25) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 166 /userif/BTN_STBY)) - (pad 2 smd rect (at -3.975 2.25) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) - (pad 2 smd rect (at 3.975 2.25) (size 1.55 1.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) ) (module Housings_SSOP:SSOP-16_5.3x6.2mm_Pitch0.65mm (layer F.Cu) (tedit 54130A77) (tstamp 56C8E557) @@ -1824,37 +1790,37 @@ (fp_line (start -2.775 3.275) (end 2.775 3.275) (layer F.SilkS) (width 0.15)) (fp_line (start -2.775 -2.7) (end -4.05 -2.7) (layer F.SilkS) (width 0.15)) (pad 1 smd rect (at -3.45 -2.275 90) (size 1.2 0.4) (layers F.Cu F.Paste F.Mask) - (net 175 /audio/ABCK)) + (net 163 /audio/ABCK)) (pad 2 smd rect (at -3.45 -1.625 90) (size 1.2 0.4) (layers F.Cu F.Paste F.Mask) - (net 176 /audio/AWS)) + (net 164 /audio/AWS)) (pad 3 smd rect (at -3.45 -0.975 90) (size 1.2 0.4) (layers F.Cu F.Paste F.Mask) - (net 177 /audio/ADATA)) + (net 165 /audio/ADATA)) (pad 4 smd rect (at -3.45 -0.325 90) (size 1.2 0.4) (layers F.Cu F.Paste F.Mask) (net 4 VFPGA33)) (pad 5 smd rect (at -3.45 0.325 90) (size 1.2 0.4) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (pad 6 smd rect (at -3.45 0.975 90) (size 1.2 0.4) (layers F.Cu F.Paste F.Mask) - (net 178 /audio/ACLK)) + (net 166 /audio/ACLK)) (pad 7 smd rect (at -3.45 1.625 90) (size 1.2 0.4) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 190 "Net-(R9-Pad1)")) (pad 8 smd rect (at -3.45 2.275 90) (size 1.2 0.4) (layers F.Cu F.Paste F.Mask) - (net 179 /audio/L3DATA)) + (net 167 /audio/L3DATA)) (pad 9 smd rect (at 3.45 2.275 90) (size 1.2 0.4) (layers F.Cu F.Paste F.Mask) - (net 180 /audio/L3MODE)) + (net 168 /audio/L3MODE)) (pad 10 smd rect (at 3.45 1.625 90) (size 1.2 0.4) (layers F.Cu F.Paste F.Mask) - (net 194 /audio/ABCLK)) + (net 163 /audio/ABCK)) (pad 11 smd rect (at 3.45 0.975 90) (size 1.2 0.4) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (pad 12 smd rect (at 3.45 0.325 90) (size 1.2 0.4) (layers F.Cu F.Paste F.Mask) - (net 183 /audio/DACVREF)) + (net 171 /audio/DACVREF)) (pad 13 smd rect (at 3.45 -0.325 90) (size 1.2 0.4) (layers F.Cu F.Paste F.Mask) (net 4 VFPGA33)) (pad 14 smd rect (at 3.45 -0.975 90) (size 1.2 0.4) (layers F.Cu F.Paste F.Mask) - (net 181 /audio/DACL)) + (net 169 /audio/DACL)) (pad 15 smd rect (at 3.45 -1.625 90) (size 1.2 0.4) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (pad 16 smd rect (at 3.45 -2.275 90) (size 1.2 0.4) (layers F.Cu F.Paste F.Mask) - (net 182 /audio/DACR)) + (net 170 /audio/DACR)) (model Housings_SSOP.3dshapes/SSOP-16_5.3x6.2mm_Pitch0.65mm.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -1883,17 +1849,17 @@ (fp_line (start 2.5 -5) (end 4 -5) (layer F.SilkS) (width 0.15)) (fp_line (start 2.5 -5) (end 2.5 -3.75) (layer F.SilkS) (width 0.15)) (pad 5 smd rect (at 0 3.4) (size 4.6 1.1) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (pad 4 smd rect (at 0 1.7) (size 4.6 1.1) (layers F.Cu F.Paste F.Mask) - (net 60 VSTM33)) + (net 52 VSTM33)) (pad 2 smd rect (at 0 -1.7) (size 4.6 1.1) (layers F.Cu F.Paste F.Mask) - (net 184 "Net-(D1-Pad1)")) + (net 172 "Net-(D1-Pad1)")) (pad 3 smd rect (at 9.15 0) (size 9.4 10.8) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (pad 3 smd rect (at 0 0) (size 4.6 1.1) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (pad 1 smd rect (at 0 -3.4) (size 4.6 1.1) (layers F.Cu F.Paste F.Mask) - (net 185 VSYS)) + (net 173 VSYS)) (model TO_SOT_Packages_SMD.3dshapes/TO-263-5Lead.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -1925,25 +1891,25 @@ (fp_line (start -1.675 1.675) (end 1.675 1.675) (layer F.SilkS) (width 0.15)) (fp_line (start -1.675 -1.375) (end -2.9 -1.375) (layer F.SilkS) (width 0.15)) (pad 1 smd rect (at -2.2 -1) (size 1.4 0.3) (layers F.Cu F.Paste F.Mask) - (net 187 VUSB)) + (net 175 VUSB)) (pad 2 smd rect (at -2.2 -0.5) (size 1.4 0.3) (layers F.Cu F.Paste F.Mask) - (net 187 VUSB)) + (net 175 VUSB)) (pad 3 smd rect (at -2.2 0) (size 1.4 0.3) (layers F.Cu F.Paste F.Mask) - (net 188 /powersupply/CHG_ACTIVE_N)) + (net 176 /powersupply/CHG_ACTIVE_N)) (pad 4 smd rect (at -2.2 0.5) (size 1.4 0.3) (layers F.Cu F.Paste F.Mask) - (net 189 "Net-(U5-Pad4)")) + (net 177 "Net-(U5-Pad4)")) (pad 5 smd rect (at -2.2 1) (size 1.4 0.3) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (pad 6 smd rect (at 2.2 1) (size 1.4 0.3) (layers F.Cu F.Paste F.Mask) - (net 190 "Net-(R8-Pad1)")) + (net 178 "Net-(R8-Pad1)")) (pad 7 smd rect (at 2.2 0.5) (size 1.4 0.3) (layers F.Cu F.Paste F.Mask) - (net 191 /powersupply/USB_PRESENT_N)) + (net 179 /powersupply/USB_PRESENT_N)) (pad 8 smd rect (at 2.2 0) (size 1.4 0.3) (layers F.Cu F.Paste F.Mask) - (net 192 "Net-(P2-Pad1)")) + (net 180 "Net-(P2-Pad1)")) (pad 9 smd rect (at 2.2 -0.5) (size 1.4 0.3) (layers F.Cu F.Paste F.Mask) - (net 193 VBAT)) + (net 181 VBAT)) (pad 10 smd rect (at 2.2 -1) (size 1.4 0.3) (layers F.Cu F.Paste F.Mask) - (net 193 VBAT)) + (net 181 VBAT)) (model Housings_SSOP.3dshapes/MSOP-10_3x3mm_Pitch0.5mm.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -1951,52 +1917,6 @@ ) ) - (module Housings_SOIC:SOIC-8_3.9x4.9mm_Pitch1.27mm (layer F.Cu) (tedit 54130A77) (tstamp 56C9C886) - (at 154.4 43.95 270) - (descr "8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)") - (tags "SOIC 1.27") - (path /56CA5D53/56CB06E0) - (attr smd) - (fp_text reference U901 (at 0 -3.5 270) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value LM358N (at 0 3.5 270) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start -3.75 -2.75) (end -3.75 2.75) (layer F.CrtYd) (width 0.05)) - (fp_line (start 3.75 -2.75) (end 3.75 2.75) (layer F.CrtYd) (width 0.05)) - (fp_line (start -3.75 -2.75) (end 3.75 -2.75) (layer F.CrtYd) (width 0.05)) - (fp_line (start -3.75 2.75) (end 3.75 2.75) (layer F.CrtYd) (width 0.05)) - (fp_line (start -2.075 -2.575) (end -2.075 -2.43) (layer F.SilkS) (width 0.15)) - (fp_line (start 2.075 -2.575) (end 2.075 -2.43) (layer F.SilkS) (width 0.15)) - (fp_line (start 2.075 2.575) (end 2.075 2.43) (layer F.SilkS) (width 0.15)) - (fp_line (start -2.075 2.575) (end -2.075 2.43) (layer F.SilkS) (width 0.15)) - (fp_line (start -2.075 -2.575) (end 2.075 -2.575) (layer F.SilkS) (width 0.15)) - (fp_line (start -2.075 2.575) (end 2.075 2.575) (layer F.SilkS) (width 0.15)) - (fp_line (start -2.075 -2.43) (end -3.475 -2.43) (layer F.SilkS) (width 0.15)) - (pad 1 smd rect (at -2.7 -1.905 270) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) - (net 195 "Net-(C903-Pad2)")) - (pad 2 smd rect (at -2.7 -0.635 270) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) - (net 181 /audio/DACL)) - (pad 3 smd rect (at -2.7 0.635 270) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) - (net 195 "Net-(C903-Pad2)")) - (pad 4 smd rect (at -2.7 1.905 270) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) - (pad 5 smd rect (at 2.7 1.905 270) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) - (net 196 "Net-(C904-Pad2)")) - (pad 6 smd rect (at 2.7 0.635 270) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) - (net 182 /audio/DACR)) - (pad 7 smd rect (at 2.7 -0.635 270) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) - (net 196 "Net-(C904-Pad2)")) - (pad 8 smd rect (at 2.7 -1.905 270) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) - (net 4 VFPGA33)) - (model Housings_SOIC.3dshapes/SOIC-8_3.9x4.9mm_Pitch1.27mm.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) - ) - ) - (module Crystals:Crystal_SMD_0603_4Pads (layer F.Cu) (tedit 0) (tstamp 56C9C88E) (at 187.612712 10.437373) (descr "Crystal, Quarz, SMD, 0603, 4 Pads,") @@ -2015,15 +1935,61 @@ (fp_line (start 0.70104 1.84912) (end -0.70104 1.84912) (layer F.SilkS) (width 0.15)) (fp_line (start -0.70104 -1.84912) (end 0.70104 -1.84912) (layer F.SilkS) (width 0.15)) (pad 1 smd rect (at -2.19964 1.19888) (size 1.80086 1.39954) (layers F.Cu F.Paste F.Mask) - (net 197 "Net-(X601-Pad1)")) + (net 182 "Net-(X601-Pad1)")) (pad 2 smd rect (at 2.19964 1.19888) (size 1.80086 1.39954) (layers F.Cu F.Paste F.Mask) - (net 61 GND)) + (net 53 GND)) (pad 3 smd rect (at 2.19964 -1.19888) (size 1.80086 1.39954) (layers F.Cu F.Paste F.Mask) - (net 186 /sdram/CLK_50M)) + (net 174 /sdram/CLK_50M)) (pad 4 smd rect (at -2.19964 -1.19888) (size 1.80086 1.39954) (layers F.Cu F.Paste F.Mask) (net 4 VFPGA33)) ) + (module Housings_SOIC:SOIC-8_3.9x4.9mm_Pitch1.27mm (layer F.Cu) (tedit 54130A77) (tstamp 56CAC8DC) + (at 154.405 43.2 90) + (descr "8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)") + (tags "SOIC 1.27") + (path /56CA5D53/56CB06E0) + (attr smd) + (fp_text reference U901 (at 0 -3.5 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value LM358N (at 0 3.5 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -3.75 -2.75) (end -3.75 2.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start 3.75 -2.75) (end 3.75 2.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.75 -2.75) (end 3.75 -2.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.75 2.75) (end 3.75 2.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.075 -2.575) (end -2.075 -2.43) (layer F.SilkS) (width 0.15)) + (fp_line (start 2.075 -2.575) (end 2.075 -2.43) (layer F.SilkS) (width 0.15)) + (fp_line (start 2.075 2.575) (end 2.075 2.43) (layer F.SilkS) (width 0.15)) + (fp_line (start -2.075 2.575) (end -2.075 2.43) (layer F.SilkS) (width 0.15)) + (fp_line (start -2.075 -2.575) (end 2.075 -2.575) (layer F.SilkS) (width 0.15)) + (fp_line (start -2.075 2.575) (end 2.075 2.575) (layer F.SilkS) (width 0.15)) + (fp_line (start -2.075 -2.43) (end -3.475 -2.43) (layer F.SilkS) (width 0.15)) + (pad 1 smd rect (at -2.7 -1.905 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 191 /audio/FBL)) + (pad 2 smd rect (at -2.7 -0.635 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 191 /audio/FBL)) + (pad 3 smd rect (at -2.7 0.635 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 169 /audio/DACL)) + (pad 4 smd rect (at -2.7 1.905 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 53 GND)) + (pad 5 smd rect (at 2.7 1.905 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 170 /audio/DACR)) + (pad 6 smd rect (at 2.7 0.635 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 192 /audio/FBR)) + (pad 7 smd rect (at 2.7 -0.635 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 192 /audio/FBR)) + (pad 8 smd rect (at 2.7 -1.905 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 52 VSTM33)) + (model Housings_SOIC.3dshapes/SOIC-8_3.9x4.9mm_Pitch1.27mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + (gr_line (start 55.6 31.6) (end 205.6 31.6) (layer Edge.Cuts) (width 0.1)) (gr_line (start 55.6 107) (end 55.6 31.6) (layer Edge.Cuts) (width 0.1)) (gr_line (start 205.6 107) (end 205.6 31.6) (layer Edge.Cuts) (width 0.1)) @@ -2034,18 +2000,18 @@ (segment (start 126.4 81.5) (end 126.4 76.71727) (width 0.153) (layer F.Cu) (net 1)) (segment (start 126.4 76.71727) (end 128.693728 74.423542) (width 0.153) (layer F.Cu) (net 1)) (segment (start 128.693728 74.423542) (end 128.693728 73.495542) (width 0.153) (layer F.Cu) (net 1)) - (segment (start 140.2 79.709662) (end 138.509662 81.4) (width 0.153) (layer F.Cu) (net 2)) - (segment (start 140.2 79) (end 140.2 79.709662) (width 0.153) (layer F.Cu) (net 2)) - (segment (start 140.2 76.1) (end 140.2 79) (width 0.153) (layer B.Cu) (net 2)) - (via (at 140.2 79) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 2)) - (segment (start 138.509662 81.4) (end 138.409662 81.5) (width 0.153) (layer F.Cu) (net 2)) - (segment (start 136.2 93.6) (end 136.2 83.709662) (width 0.153) (layer F.Cu) (net 2)) - (segment (start 136.2 83.709662) (end 138.509662 81.4) (width 0.153) (layer F.Cu) (net 2)) - (segment (start 140.193728 73.495542) (end 140.193728 76.093728) (width 0.153) (layer F.Cu) (net 2)) - (via (at 140.2 76.1) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 2)) - (segment (start 140.193728 76.093728) (end 140.2 76.1) (width 0.153) (layer F.Cu) (net 2)) - (segment (start 120.75 64.85) (end 121.65 64.85) (width 0.153) (layer B.Cu) (net 4)) - (segment (start 121.65 64.85) (end 121.8 65) (width 0.153) (layer B.Cu) (net 4)) + (segment (start 136.2 90.468664) (end 135.793989 90.062653) (width 0.153) (layer F.Cu) (net 2)) + (segment (start 139.7 79.667236) (end 139.7 79.353553) (width 0.153) (layer F.Cu) (net 2)) + (segment (start 135.793989 90.062653) (end 135.793989 83.573247) (width 0.153) (layer F.Cu) (net 2)) + (segment (start 139.7 79.353553) (end 139.7 79) (width 0.153) (layer F.Cu) (net 2)) + (segment (start 136.2 93.6) (end 136.2 90.468664) (width 0.153) (layer F.Cu) (net 2)) + (segment (start 135.793989 83.573247) (end 139.7 79.667236) (width 0.153) (layer F.Cu) (net 2)) + (segment (start 139.8 76.5) (end 139.8 73.601814) (width 0.153) (layer F.Cu) (net 2)) + (segment (start 139.8 73.601814) (end 139.693728 73.495542) (width 0.153) (layer F.Cu) (net 2)) + (segment (start 139.7 79) (end 139.7 76.6) (width 0.153) (layer B.Cu) (net 2)) + (segment (start 139.7 76.6) (end 139.8 76.5) (width 0.153) (layer B.Cu) (net 2)) + (via (at 139.8 76.5) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 2)) + (via (at 139.7 79) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 2)) (segment (start 137.693728 52.095542) (end 137.693728 53.193728) (width 0.153) (layer F.Cu) (net 4)) (segment (start 137.693728 53.193728) (end 137.7 53.2) (width 0.153) (layer F.Cu) (net 4)) (via (at 137.7 53.2) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 4)) @@ -2073,6 +2039,8 @@ (segment (start 126.693728 73.495542) (end 126.693728 71.99571) (width 0.153) (layer F.Cu) (net 4)) (segment (start 126.693728 71.99571) (end 126.690091 71.992073) (width 0.153) (layer F.Cu) (net 4)) (via (at 126.690091 71.992073) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 4)) + (segment (start 120.75 64.85) (end 121.65 64.85) (width 0.153) (layer B.Cu) (net 4)) + (segment (start 121.65 64.85) (end 121.8 65) (width 0.153) (layer B.Cu) (net 4)) (segment (start 120.75 58.8) (end 121.55 58.8) (width 0.153) (layer B.Cu) (net 4)) (segment (start 121.55 58.8) (end 121.8 59.05) (width 0.153) (layer B.Cu) (net 4)) (segment (start 121.8 60.05) (end 120.75 60.05) (width 0.153) (layer B.Cu) (net 4)) @@ -2167,730 +2135,732 @@ (segment (start 143.296898 89.7) (end 142.903551 89.306653) (width 0.153) (layer F.Cu) (net 10)) (segment (start 142.903551 89.306653) (end 142.903551 82.3) (width 0.153) (layer F.Cu) (net 10)) (via (at 142.903551 82.3) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 10)) - (segment (start 136.2 77.8) (end 136.2 76.829761) (width 0.153) (layer F.Cu) (net 25)) - (segment (start 136.2 76.829761) (end 137.193728 75.836033) (width 0.153) (layer F.Cu) (net 25)) - (segment (start 137.193728 75.836033) (end 137.193728 74.423542) (width 0.153) (layer F.Cu) (net 25)) - (segment (start 137.193728 74.423542) (end 137.193728 73.495542) (width 0.153) (layer F.Cu) (net 25)) - (segment (start 135.7 77.8) (end 135.7 76.897) (width 0.153) (layer F.Cu) (net 26)) - (segment (start 135.7 76.897) (end 136.693728 75.903272) (width 0.153) (layer F.Cu) (net 26)) - (segment (start 136.693728 75.903272) (end 136.693728 74.423542) (width 0.153) (layer F.Cu) (net 26)) - (segment (start 136.693728 74.423542) (end 136.693728 73.495542) (width 0.153) (layer F.Cu) (net 26)) - (segment (start 135.2 77.8) (end 135.2 73.501814) (width 0.153) (layer F.Cu) (net 27)) - (segment (start 135.2 73.501814) (end 135.193728 73.495542) (width 0.153) (layer F.Cu) (net 27)) - (segment (start 134.7 77.8) (end 134.7 73.501814) (width 0.153) (layer F.Cu) (net 28)) - (segment (start 134.7 73.501814) (end 134.693728 73.495542) (width 0.153) (layer F.Cu) (net 28)) - (segment (start 134.193728 73.495542) (end 134.193728 77.793728) (width 0.153) (layer F.Cu) (net 29)) - (segment (start 134.193728 77.793728) (end 134.2 77.8) (width 0.153) (layer F.Cu) (net 29)) - (segment (start 133.7 77.8) (end 133.7 73.501814) (width 0.153) (layer F.Cu) (net 30)) - (segment (start 133.7 73.501814) (end 133.693728 73.495542) (width 0.153) (layer F.Cu) (net 30)) - (segment (start 133.193728 73.495542) (end 133.193728 77.793728) (width 0.153) (layer F.Cu) (net 31)) - (segment (start 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) ) ) @@ -4154,7 +4134,7 @@ ) ) ) - (zone (net 61) (net_name GND) (layer F.Cu) (tstamp 56C8E637) (hatch edge 0.508) + (zone (net 53) (net_name GND) (layer F.Cu) (tstamp 56C8E637) (hatch edge 0.508) (priority 2) (connect_pads (clearance 0.2)) (min_thickness 0.254) diff --git a/fpgna.net b/fpgna.net index 647a3a7..351560b 100644 --- a/fpgna.net +++ b/fpgna.net @@ -1,7 +1,7 @@ (export (version D) (design - (source /home/markus/projects/kicad/fpgna/fpgna.sch) - (date "So 21 Feb 2016 15:22:06 CET") + (source /home/kurisu/projects/kicad/fpgna/fpgna.sch) + (date "Mon 22 Feb 2016 08:46:46 AM CET") (tool "Eeschema (2016-02-12 BZR 6554)-stable") (sheet (number 1) (name /) (tstamps /) (title_block @@ -69,18 +69,7 @@ (comment (number 2) (value "")) (comment (number 3) (value "")) (comment (number 4) (value "")))) - (sheet (number 7) (name /userif/) (tstamps /56C86141/) - (title_block - (title) - (company) - (rev) - (date) - (source userif.sch) - (comment (number 1) (value "")) - (comment (number 2) (value "")) - (comment (number 3) (value "")) - (comment (number 4) (value "")))) - (sheet (number 8) (name /sdcard/) (tstamps /56C7DD81/) + (sheet (number 7) (name /sdcard/) (tstamps /56C7DD81/) (title_block (title) (company) @@ -91,7 +80,7 @@ (comment (number 2) (value "")) (comment (number 3) (value "")) (comment (number 4) (value "")))) - (sheet (number 9) (name /audio/) (tstamps /56CA5D53/) + (sheet (number 8) (name /audio/) (tstamps /56CA5D53/) (title_block (title) (company) @@ -101,6 +90,17 @@ (comment (number 1) (value "")) (comment (number 2) (value "")) (comment (number 3) (value "")) + (comment (number 4) (value "")))) + (sheet (number 9) (name /userif/) (tstamps /56C86141/) + (title_block + (title) + (company) + (rev) + (date) + (source userif.sch) + (comment (number 1) (value "")) + (comment (number 2) (value "")) + (comment (number 3) (value "")) (comment (number 4) (value ""))))) (components (comp (ref U3) @@ -265,6 +265,8 @@ (tstamp 56C22F77)) (comp (ref R8) (value 2.2k) + (fields + (field (name TODO) "TODO: Check value")) (libsource (lib device) (part R)) (sheetpath (names /powersupply/) (tstamps /563244F7/)) (tstamp 56C24FD6)) @@ -288,21 +290,11 @@ (libsource (lib device) (part R)) (sheetpath (names /powersupply/) (tstamps /563244F7/)) (tstamp 56C403C0)) - (comp (ref R9) - (value 10k) - (libsource (lib device) (part R)) - (sheetpath (names /powersupply/) (tstamps /563244F7/)) - (tstamp 56C4F34C)) (comp (ref R12) - (value 500) + (value 10k) (libsource (lib device) (part R)) (sheetpath (names /powersupply/) (tstamps /563244F7/)) (tstamp 56C590A7)) - (comp (ref R11) - (value 10k) - (libsource (lib device) (part R)) - (sheetpath (names /powersupply/) (tstamps /563244F7/)) - (tstamp 56C592CD)) (comp (ref R5) (value 10k) (libsource (lib device) (part R)) @@ -365,11 +357,6 @@ (libsource (lib device) (part Q_NMOS_DGS)) (sheetpath (names /powersupply/) (tstamps /563244F7/)) (tstamp 56C543A2)) - (comp (ref Q4) - (value NMOS-LPLL) - (libsource (lib device) (part Q_NMOS_DGS)) - (sheetpath (names /powersupply/) (tstamps /563244F7/)) - (tstamp 56C56373)) (comp (ref U4) (value STM32F407VGT) (footprint footprints:LQFP-100_14x14mm_Pitch0.5mm-SMALLCORNER) @@ -551,6 +538,26 @@ (libsource (lib conn) (part CONN_01X06)) (sheetpath (names /debug/) (tstamps /56337D98/)) (tstamp 56C73EAE)) + (comp (ref P301) + (value CONN_02X03) + (libsource (lib conn) (part CONN_02X03)) + (sheetpath (names /debug/) (tstamps /56337D98/)) + (tstamp 56CD008F)) + (comp (ref R301) + (value 10k) + (libsource (lib device) (part R)) + (sheetpath (names /debug/) (tstamps /56337D98/)) + (tstamp 56CD0D17)) + (comp (ref R302) + (value 10k) + (libsource (lib device) (part R)) + (sheetpath (names /debug/) (tstamps /56337D98/)) + (tstamp 56CD0F59)) + (comp (ref R303) + (value 10k) + (libsource (lib device) (part R)) + (sheetpath (names /debug/) (tstamps /56337D98/)) + (tstamp 56CD0F97)) (comp (ref C28) (value 100n) (libsource (lib device) (part C)) @@ -622,6 +629,68 @@ (libsource (lib device) (part C)) (sheetpath (names /sdram/) (tstamps /56C6F777/)) (tstamp 56CA32A6)) + (comp (ref C101) + (value 10n) + (libsource (lib device) (part C)) + (sheetpath (names /sdcard/) (tstamps /56C7DD81/)) + (tstamp 56C7E710)) + (comp (ref C102) + (value 100n) + (libsource (lib device) (part C)) + (sheetpath (names /sdcard/) (tstamps /56C7DD81/)) + (tstamp 56C7E737)) + (comp (ref CON801) + (value Micro_SD) + (footprint smd:Micro_SD) + (libsource (lib connectors) (part Micro_SD)) + (sheetpath (names /sdcard/) (tstamps /56C7DD81/)) + (tstamp 56C8C648)) + (comp (ref C902) + (value 47u) + (libsource (lib device) (part CP_Small)) + (sheetpath (names /audio/) (tstamps /56CA5D53/)) + (tstamp 56CAE8FF)) + (comp (ref C901) + (value 100n) + (libsource (lib device) (part C_Small)) + (sheetpath (names /audio/) (tstamps /56CA5D53/)) + (tstamp 56CAE9B0)) + (comp (ref U901) + (value LM358N) + (footprint Housings_SOIC:SOIC-8_3.9x4.9mm_Pitch1.27mm) + (libsource (lib linear) (part LM358N)) + (sheetpath (names /audio/) (tstamps /56CA5D53/)) + (tstamp 56CB06E0)) + (comp (ref C904) + (value 10u) + (libsource (lib device) (part C_Small)) + (sheetpath (names /audio/) (tstamps /56CA5D53/)) + (tstamp 56CB12BD)) + (comp (ref C903) + (value 10u) + (libsource (lib device) (part C_Small)) + (sheetpath (names /audio/) (tstamps /56CA5D53/)) + (tstamp 56CB13B6)) + (comp (ref R901) + (value 10k) + (libsource (lib device) (part R)) + (sheetpath (names /audio/) (tstamps /56CA5D53/)) + (tstamp 56CB1669)) + (comp (ref R902) + (value 10k) + (libsource (lib device) (part R)) + (sheetpath (names /audio/) (tstamps /56CA5D53/)) + (tstamp 56CB16B1)) + (comp (ref J901) + (value JACK_TRS_3PINS) + (libsource (lib connectors) (part JACK_TRS_3PINS)) + (sheetpath (names /audio/) (tstamps /56CA5D53/)) + (tstamp 56CB18AA)) + (comp (ref R9) + (value 0) + (libsource (lib device) (part R)) + (sheetpath (names /audio/) (tstamps /56CA5D53/)) + (tstamp 56CC26E6)) (comp (ref SW802) (value UP) (footprint smd:Tactile_Switch) @@ -689,70 +758,7 @@ (value 220) (libsource (lib device) (part R)) (sheetpath (names /userif/) (tstamps /56C86141/)) - (tstamp 56C90098)) - (comp (ref SW701) - (value DOWN) - (footprint smd:Tactile_Switch) - (libsource (lib device) (part SW_PUSH)) - (sheetpath (names /userif/) (tstamps /56C86141/)) - (tstamp 56C90B91)) - (comp (ref C101) - (value 10n) - (libsource (lib device) (part C)) - (sheetpath (names /sdcard/) (tstamps /56C7DD81/)) - (tstamp 56C7E710)) - (comp (ref C102) - (value 100n) - (libsource (lib device) (part C)) - (sheetpath (names /sdcard/) (tstamps /56C7DD81/)) - (tstamp 56C7E737)) - (comp (ref CON801) - (value Micro_SD) - (footprint smd:Micro_SD) - (libsource (lib connectors) (part Micro_SD)) - (sheetpath (names /sdcard/) (tstamps /56C7DD81/)) - (tstamp 56C8C648)) - (comp (ref C902) - (value 47u) - (libsource (lib device) (part CP_Small)) - (sheetpath (names /audio/) (tstamps /56CA5D53/)) - (tstamp 56CAE8FF)) - (comp (ref C901) - (value 100n) - (libsource (lib device) (part C_Small)) - (sheetpath (names /audio/) (tstamps /56CA5D53/)) - (tstamp 56CAE9B0)) - (comp (ref U901) - (value LM358N) - (footprint Housings_SOIC:SOIC-8_3.9x4.9mm_Pitch1.27mm) - (libsource (lib linear) (part LM358N)) - (sheetpath (names /audio/) (tstamps /56CA5D53/)) - (tstamp 56CB06E0)) - (comp (ref C904) - (value 10u) - (libsource (lib device) (part C_Small)) - (sheetpath (names /audio/) (tstamps /56CA5D53/)) - (tstamp 56CB12BD)) - (comp (ref C903) - (value 10u) - (libsource (lib device) (part C_Small)) - (sheetpath (names /audio/) (tstamps /56CA5D53/)) - (tstamp 56CB13B6)) - (comp (ref R901) - (value 10k) - (libsource (lib device) (part R)) - (sheetpath (names /audio/) (tstamps /56CA5D53/)) - (tstamp 56CB1669)) - (comp (ref R902) - (value 10k) - (libsource (lib device) (part R)) - (sheetpath (names /audio/) (tstamps /56CA5D53/)) - (tstamp 56CB16B1)) - (comp (ref J901) - (value JACK_TRS_3PINS) - (libsource (lib connectors) (part JACK_TRS_3PINS)) - (sheetpath (names /audio/) (tstamps /56CA5D53/)) - (tstamp 56CB18AA))) + (tstamp 56C90098))) (libparts (libpart (lib device) (part C) (description "Unpolarized capacitor") @@ -799,6 +805,23 @@ (pin (num 4) (name P4) (type passive)) (pin (num 5) (name P5) (type passive)) (pin (num 6) (name P6) (type passive)))) + (libpart (lib conn) (part CONN_02X03) + (description "Connector 02x03") + (footprints + (fp Pin_Header_Straight_2X03) + (fp Pin_Header_Angled_2X03) + (fp Socket_Strip_Straight_2X03) + (fp Socket_Strip_Angled_2X03)) + (fields + (field (name Reference) P) + (field (name Value) CONN_02X03)) + (pins + (pin (num 1) (name P1) (type passive)) + (pin (num 2) (name P2) (type passive)) + (pin (num 3) (name P3) (type passive)) + (pin (num 4) (name P4) (type passive)) + (pin (num 5) (name P5) (type passive)) + (pin (num 6) (name P6) (type passive)))) (libpart (lib device) (part CP) (description "Polarised capacitor") (footprints @@ -1075,22 +1098,22 @@ (pin (num 40) (name PB7B) (type BiDi)) (pin (num 41) (name GNDIO51) (type power_in)) (pin (num 42) (name VCCIO51) (type power_in)) - (pin (num 43) (name PB13B) (type input)) - (pin (num 44) (name PB13A) (type input)) - (pin (num 45) (name PB15A) (type input)) - (pin (num 46) (name PB14A) (type input)) - (pin (num 47) (name PB15B) (type input)) - (pin (num 48) (name PB14B) (type input)) + (pin (num 43) (name PB13B) (type BiDi)) + (pin (num 44) (name PB13A) (type BiDi)) + (pin (num 45) (name PB15A) (type BiDi)) + (pin (num 46) (name PB14A) (type BiDi)) + (pin (num 47) (name PB15B) (type BiDi)) + (pin (num 48) (name PB14B) (type BiDi)) (pin (num 49) (name VCCIO52) (type power_in)) - (pin (num 50) (name PB16A) (type input)) + (pin (num 50) (name PB16A) (type BiDi)) (pin (num 51) (name GNDIO52) (type power_in)) - (pin (num 52) (name PB16B) (type input)) - (pin (num 53) (name PB17A) (type input)) - (pin (num 54) (name PB17B) (type input)) - (pin (num 55) (name PB18A) (type input)) - (pin (num 56) (name PB19A) (type input)) - (pin (num 57) (name PB18B) (type input)) - (pin (num 58) (name PB19B) (type input)) + (pin (num 52) (name PB16B) (type BiDi)) + (pin (num 53) (name PB17A) (type BiDi)) + (pin (num 54) (name PB17B) (type BiDi)) + (pin (num 55) (name PB18A) (type BiDi)) + (pin (num 56) (name PB19A) (type BiDi)) + (pin (num 57) (name PB18B) (type BiDi)) + (pin (num 58) (name PB19B) (type BiDi)) (pin (num 59) (name VCC2) (type power_in)) (pin (num 60) (name VCCAUX2) (type power_in)) (pin (num 61) (name PB20A) (type BiDi)) @@ -1219,11 +1242,11 @@ (field (name Value) Lattice-JTAG)) (pins (pin (num 1) (name SCK) (type output)) - (pin (num 2) (name GND) (type power_out)) + (pin (num 2) (name GND) (type power_in)) (pin (num 3) (name TMS) (type output)) - (pin (num 4) (name GND) (type power_out)) + (pin (num 4) (name GND) (type power_in)) (pin (num 5) (name TDI) (type output)) - (pin (num 6) (name VCC) (type power_out)) + (pin (num 6) (name VCC) (type power_in)) (pin (num 7) (name TDO) (type input)) (pin (num 8) (name INIT) (type output)) (pin (num 9) (name TRST) (type input)) @@ -1435,9 +1458,9 @@ (pin (num 11) (name APPL0) (type input)) (pin (num 12) (name VREF) (type input)) (pin (num 13) (name VDDA) (type power_in)) - (pin (num 14) (name VOUTL) (type input)) + (pin (num 14) (name VOUTL) (type output)) (pin (num 15) (name VSSA) (type power_in)) - (pin (num 16) (name VOUTR) (type input)))) + (pin (num 16) (name VOUTR) (type output)))) (libpart (lib conn) (part USB_OTG) (description "micro/mini connector") (footprints @@ -1464,895 +1487,890 @@ (pin (num 1) (name K) (type passive)) (pin (num 2) (name A) (type passive))))) (libraries - (library (logical device) - (uri /usr/share/kicad/library/device.lib)) (library (logical fpgna-rescue) - (uri /home/markus/projects/kicad/fpgna/fpgna-rescue.lib)) - (library (logical linear) - (uri /usr/share/kicad/library/linear.lib)) - (library (logical conn) - (uri /usr/share/kicad/library/conn.lib)) + (uri /home/kurisu/projects/kicad/fpgna/fpgna-rescue.lib)) (library (logical regul) (uri /usr/share/kicad/library/regul.lib)) + (library (logical conn) + (uri /usr/share/kicad/library/conn.lib)) + (library (logical linear) + (uri /usr/share/kicad/library/linear.lib)) + (library (logical device) + (uri /usr/share/kicad/library/device.lib)) (library (logical Oscillators) (uri /usr/share/kicad/library/Oscillators.lib)) (library (logical lattice) - (uri /home/markus/projects/kicad/ShimattaPCBLibs/schematics/lattice/lattice.lib)) + (uri /home/kurisu/projects/kicad/ShimattaPCBLibs/schematics/lattice/lattice.lib)) (library (logical pmic) - (uri /home/markus/projects/kicad/ShimattaPCBLibs/schematics/power/pmic.lib)) + (uri /home/kurisu/projects/kicad/ShimattaPCBLibs/schematics/power/pmic.lib)) (library (logical regulators) - (uri /home/markus/projects/kicad/ShimattaPCBLibs/schematics/power/regulators.lib)) + (uri /home/kurisu/projects/kicad/ShimattaPCBLibs/schematics/power/regulators.lib)) (library (logical stm32f4) - (uri /home/markus/projects/kicad/ShimattaPCBLibs/schematics/stm/stm32f4.lib)) + (uri /home/kurisu/projects/kicad/ShimattaPCBLibs/schematics/stm/stm32f4.lib)) (library (logical itead-displays) - (uri /home/markus/projects/kicad/ShimattaPCBLibs/schematics/shields/itead-displays.lib)) + (uri /home/kurisu/projects/kicad/ShimattaPCBLibs/schematics/shields/itead-displays.lib)) (library (logical connectors) - (uri /home/markus/projects/kicad/ShimattaPCBLibs/schematics/connectors/connectors.lib)) + (uri /home/kurisu/projects/kicad/ShimattaPCBLibs/schematics/connectors/connectors.lib)) (library (logical analog) - (uri /home/markus/projects/kicad/ShimattaPCBLibs/schematics/analog/analog.lib))) + (uri /home/kurisu/projects/kicad/ShimattaPCBLibs/schematics/analog/analog.lib))) (nets - (net (code 1) (name /FSMC/T_CLK) - (node (ref U4) (pin 52)) - (node (ref U6) (pin 18))) - (net (code 2) (name /sdcard/SW_C) - (node (ref SW807) (pin 1)) - (node (ref U4) (pin 15))) - (net (code 3) (name /sdcard/SW_B) - (node (ref SW805) (pin 1)) - (node (ref U4) (pin 18))) - (net (code 4) (name /sdcard/SW_A) + (net (code 1) (name /FSMC/JRST_N) + (node (ref P4) (pin 5)) + (node (ref U4) (pin 90))) + (net (code 2) (name /sdcard/SW_A) (node (ref U4) (pin 17)) (node (ref SW806) (pin 1))) - (net (code 5) (name /display/T_BUSY) - (node (ref U4) (pin 63)) - (node (ref U6) (pin 24))) - (net (code 6) (name /FSMC/T_DOUT) - (node (ref U4) (pin 53)) - (node (ref U6) (pin 26))) - (net (code 7) (name /FSMC/T_DIN) - (node (ref U4) (pin 54)) - (node (ref U6) (pin 22))) - (net (code 8) (name /FSMC/T_CS) - (node (ref U4) (pin 51)) - (node (ref U6) (pin 20))) - (net (code 9) (name /sdcard/SW_D) - (node (ref U4) (pin 16)) - (node (ref SW808) (pin 1))) - (net (code 10) (name /display/T_IRQ) - (node (ref U4) (pin 64)) - (node (ref U6) (pin 28))) - (net (code 11) (name /FSMC/SDIO_CMD) - (node (ref CON801) (pin 3)) - (node (ref U4) (pin 83))) - (net (code 12) (name /debug/JTDI) - (node (ref U4) (pin 77)) - (node (ref P4) (pin 3))) - (net (code 13) (name /debug/JTCK) - (node (ref U4) (pin 76)) - (node (ref P4) (pin 1))) - (net (code 14) (name /debug/JTMS) - (node (ref U4) (pin 72)) - (node (ref P4) (pin 2))) - (net (code 15) (name /audio/ACLK) - (node (ref U3) (pin 15)) - (node (ref U201) (pin 6))) - (net (code 16) (name /powersupply/CHG_ACTIVE_N) - (node (ref U5) (pin 3)) - (node (ref R4) (pin 2))) - (net (code 17) (name /audio/L3MODE) - (node (ref U201) (pin 9)) - (node (ref U3) (pin 10))) - (net (code 18) (name /audio/L3DATA) + (net (code 3) (name /audio/L3MODE) + (node (ref U3) (pin 10)) + (node (ref U201) (pin 9))) + (net (code 4) (name /audio/L3DATA) (node (ref U3) (pin 13)) (node (ref U201) (pin 8))) - (net (code 19) (name /audio/ADATA) + (net (code 5) (name /audio/ADATA) (node (ref U201) (pin 3)) (node (ref U3) (pin 11))) - (net (code 20) (name /audio/ABCK) - (node (ref U201) (pin 1)) - (node (ref U3) (pin 18))) - (net (code 21) (name /audio/AWS) - (node (ref U3) (pin 17)) - (node (ref U201) (pin 2))) - (net (code 22) (name /powersupply/USB_PRESENT_N) - (node (ref U5) (pin 7)) - (node (ref R7) (pin 2))) - (net (code 23) (name /FSMC/JTDO) - (node (ref P4) (pin 4)) - (node (ref U4) (pin 89))) - (net (code 24) (name /FSMC/JRST_N) - (node (ref U4) (pin 90)) - (node (ref P4) (pin 5))) - (net (code 25) (name /FSMC/BOOT1) + (net (code 6) (name /audio/ACLK) + (node (ref U201) (pin 6)) + (node (ref U3) (pin 15))) + (net (code 7) (name /audio/ABCK) + (node (ref U201) (pin 10)) + (node (ref U3) (pin 18)) + (node (ref U201) (pin 1))) + (net (code 8) (name /audio/AWS) + (node (ref U201) (pin 2)) + (node (ref U3) (pin 17))) + (net (code 9) (name /FSMC/JTDO) + (node (ref U4) (pin 89)) + (node (ref P4) (pin 4))) + (net (code 10) (name /sdcard/SW_D) + (node (ref U4) (pin 16)) + (node (ref SW808) (pin 1))) + (net (code 11) (name /FSMC/BOOT1) + (node (ref P301) (pin 5)) + (node (ref R301) (pin 2)) (node (ref U4) (pin 37))) - (net (code 26) (name /FSMC/BL1_N) - (node (ref U4) (pin 98)) - (node (ref U3) (pin 2))) - (net (code 27) (name /FSMC/BL0_N) + (net (code 12) (name /display/T_IRQ) + (node (ref U4) (pin 64)) + (node (ref U6) (pin 28))) + (net (code 13) (name /FSMC/SDIO_CMD) + (node (ref CON801) (pin 3)) + (node (ref U4) (pin 83))) + (net (code 14) (name /display/T_BUSY) + (node (ref U6) (pin 24)) + (node (ref U4) (pin 63))) + (net (code 15) (name /FSMC/T_DOUT) + (node (ref U6) (pin 26)) + (node (ref U4) (pin 53))) + (net (code 16) (name /FSMC/T_DIN) + (node (ref U4) (pin 54)) + (node (ref U6) (pin 22))) + (net (code 17) (name /powersupply/CHARGE_ENABLE) + (node (ref U4) (pin 32)) + (node (ref Q2) (pin 2)) + (node (ref R12) (pin 2))) + (net (code 18) (name /powersupply/CHG_ACTIVE_N) + (node (ref U5) (pin 3)) + (node (ref R4) (pin 2)) + (node (ref U4) (pin 30))) + (net (code 19) (name /FSMC/BACKLIGHT_EN_N) + (node (ref Q5) (pin 2)) + (node (ref R13) (pin 1)) + (node (ref U3) (pin 114))) + (net (code 20) (name /sdcard/SDCARD_DETECT) + (node (ref CON801) (pin 9)) + (node (ref U4) (pin 71))) + (net (code 21) (name /debug/JTDI) + (node (ref U4) (pin 77)) + (node (ref P4) (pin 3))) + (net (code 22) (name /debug/JTCK) + (node (ref U4) (pin 76)) + (node (ref P4) (pin 1))) + (net (code 23) (name /debug/JTMS) + (node (ref P4) (pin 2)) + (node (ref U4) (pin 72))) + (net (code 24) (name /sdcard/SW_C) + (node (ref SW807) (pin 1)) + (node (ref U4) (pin 15))) + (net (code 25) (name /sdcard/SW_B) + (node (ref U4) (pin 18)) + (node (ref SW805) (pin 1))) + (net (code 26) (name /powersupply/USB_PRESENT_N) + (node (ref U5) (pin 7)) + (node (ref R7) (pin 2)) + (node (ref U4) (pin 29))) + (net (code 27) (name /powersupply/FPGA_ENABLE_N) + (node (ref Q1) (pin 2)) + (node (ref R1) (pin 2)) + (node (ref U4) (pin 31))) + (net (code 28) (name /powersupply/SYS_VOLTAGE) + (node (ref D2) (pin 1)) + (node (ref U4) (pin 26)) + (node (ref R6) (pin 1)) + (node (ref R5) (pin 2))) + (net (code 29) (name /FSMC/BL0_N) (node (ref U4) (pin 97)) (node (ref U3) (pin 1))) - (net (code 28) (name /powersupply/FPGA_ENABLE_N) - (node (ref R1) (pin 2)) - (node (ref Q1) (pin 2))) - (net (code 29) (name /powersupply/SYS_VOLTAGE) - (node (ref R5) (pin 2)) - (node (ref R6) (pin 1)) - (node (ref D2) (pin 1))) - (net (code 30) (name /powersupply/CHARGE_ENABLE) - (node (ref R12) (pin 1))) - (net (code 31) (name VUSB) - (node (ref C7) (pin 1)) - (node (ref U5) (pin 1)) - (node (ref U5) (pin 2)) - (node (ref Q3) (pin 2)) - (node (ref D3) (pin 2)) - (node (ref R9) (pin 1)) - (node (ref L3) (pin 1)) - (node (ref R10) (pin 1))) - (net (code 32) (name VBAT) - (node (ref U5) (pin 9)) - (node (ref U5) (pin 10)) - (node (ref P2) (pin 2)) - (node (ref Q3) (pin 1))) - (net (code 33) (name "Net-(R8-Pad1)") + (net (code 30) (name /FSMC/T_CLK) + (node (ref U6) (pin 18)) + (node (ref U4) (pin 52))) + (net (code 31) (name /FSMC/T_CS) + (node (ref U6) (pin 20)) + (node (ref U4) (pin 51))) + (net (code 32) (name /FSMC/BL1_N) + (node (ref U4) (pin 98)) + (node (ref U3) (pin 2))) + (net (code 33) (name "Net-(Q2-Pad1)") + (node (ref Q2) (pin 1)) + (node (ref R8) (pin 2))) + (net (code 34) (name "Net-(R8-Pad1)") (node (ref U5) (pin 6)) (node (ref R8) (pin 1))) - (net (code 34) (name "Net-(C7-Pad2)") + (net (code 35) (name "Net-(L3-Pad2)") (node (ref P1) (pin 1)) - (node (ref C7) (pin 2)) (node (ref L3) (pin 2))) - (net (code 35) (name "Net-(Q4-Pad2)") - (node (ref R12) (pin 2)) - (node (ref Q4) (pin 2)) - (node (ref R11) (pin 2))) - (net (code 36) (name "Net-(P2-Pad1)") + (net (code 36) (name VUSB) + (node (ref L3) (pin 1)) + (node (ref D3) (pin 2)) + (node (ref R10) (pin 1)) + (node (ref Q3) (pin 2)) + (node (ref C7) (pin 1)) + (node (ref U5) (pin 2)) + (node (ref U5) (pin 1))) + (net (code 37) (name VBAT) + (node (ref U5) (pin 10)) + (node (ref Q3) (pin 1)) + (node (ref U5) (pin 9)) + (node (ref P2) (pin 2))) + (net (code 38) (name "Net-(D1-Pad1)") + (node (ref U2) (pin 2)) + (node (ref D1) (pin 1)) + (node (ref L1) (pin 1))) + (net (code 39) (name "Net-(P2-Pad1)") (node (ref P2) (pin 1)) - (node (ref Q2) (pin 1)) (node (ref U5) (pin 8))) - (net (code 37) (name VSYS) - (node (ref U2) (pin 1)) - (node (ref C1) (pin 1)) + (net (code 40) (name VSYS) (node (ref R5) (pin 1)) - (node (ref D3) (pin 1)) + (node (ref C1) (pin 1)) (node (ref C3) (pin 1)) - (node (ref Q3) (pin 3))) - (net (code 38) (name "Net-(Q2-Pad2)") - (node (ref R9) (pin 2)) - (node (ref Q2) (pin 2)) - (node (ref Q4) (pin 1))) - (net (code 39) (name "Net-(C4-Pad1)") + (node (ref D3) (pin 1)) + (node (ref Q3) (pin 3)) + (node (ref U2) (pin 1))) + (net (code 41) (name "Net-(C4-Pad1)") + (node (ref C5) (pin 1)) (node (ref C4) (pin 1)) - (node (ref L2) (pin 1)) (node (ref U1) (pin 2)) - (node (ref C5) (pin 1))) - (net (code 40) (name +1V2) - (node (ref C21) (pin 1)) - (node (ref C19) (pin 1)) + (node (ref L2) (pin 1))) + (net (code 42) (name +1V2) + (node (ref L2) (pin 2)) + (node (ref U3) (pin 24)) + (node (ref U3) (pin 84)) + (node (ref U3) (pin 59)) + (node (ref U3) (pin 118)) + (node (ref C9) (pin 1)) (node (ref C17) (pin 1)) (node (ref C15) (pin 1)) (node (ref C13) (pin 1)) (node (ref C11) (pin 1)) - (node (ref U3) (pin 118)) - (node (ref U3) (pin 84)) - (node (ref U3) (pin 24)) - (node (ref U3) (pin 59)) - (node (ref C9) (pin 1)) - (node (ref L2) (pin 2))) - (net (code 41) (name "Net-(Q5-Pad1)") - (node (ref R14) (pin 2)) - (node (ref Q5) (pin 1))) - (net (code 42) (name /powersupply/BACKLIGHT_EN_N) - (node (ref R13) (pin 1)) - (node (ref Q5) (pin 2))) - (net (code 43) (name "Net-(R14-Pad1)") - (node (ref U6) (pin 37)) - (node (ref R14) (pin 1))) - (net (code 44) (name /powersupply/TOE) - (node (ref U3) (pin 25)) - (node (ref R2) (pin 2))) - (net (code 45) (name /powersupply/CFG0) - (node (ref R3) (pin 2)) - (node (ref U3) (pin 26))) - (net (code 46) (name "Net-(D1-Pad1)") - (node (ref U2) (pin 2)) - (node (ref D1) (pin 1)) - (node (ref L1) (pin 1))) - (net (code 47) (name "Net-(P1-Pad6)") - (node (ref R15) (pin 1)) - (node (ref P1) (pin 6))) - (net (code 48) (name /powersupply/VCAP2) - (node (ref U4) (pin 73)) - (node (ref C26) (pin 1))) - (net (code 49) (name /powersupply/VCAP1) - (node (ref C25) (pin 1)) - (node (ref U4) (pin 49))) - (net (code 50) (name "Net-(U5-Pad4)") - (node (ref U5) (pin 4))) - (net (code 51) (name "Net-(P1-Pad2)") - (node (ref P1) (pin 2))) - (net (code 52) (name "Net-(P1-Pad3)") - (node (ref P1) (pin 3))) - (net (code 53) (name "Net-(P1-Pad4)") - (node (ref P1) (pin 4))) - (net (code 54) (name VSTM33) - (node (ref C33) (pin 1)) - (node (ref C36) (pin 1)) - (node (ref C37) (pin 1)) - (node (ref C39) (pin 1)) - (node (ref C32) (pin 1)) - (node (ref C35) (pin 1)) - (node (ref C34) (pin 1)) - (node (ref C38) (pin 1)) - (node (ref C31) (pin 1)) - (node (ref CON801) (pin 4)) - (node (ref U4) (pin 11)) - (node (ref U4) (pin 6)) - (node (ref U4) (pin 50)) - (node (ref U4) (pin 21)) - (node (ref U4) (pin 22)) - (node (ref U4) (pin 100)) - (node (ref U4) (pin 75)) - (node (ref U4) (pin 28)) - (node (ref C6) (pin 1)) - (node (ref L1) (pin 2)) - (node (ref U4) (pin 19)) - (node (ref U2) (pin 4)) - (node (ref R1) (pin 1)) - (node (ref Q1) (pin 3)) - (node (ref R7) (pin 1)) - (node (ref C101) (pin 1)) - (node (ref R4) (pin 1)) - (node (ref C102) (pin 1))) - (net (code 55) (name VFPGA33) - (node (ref U201) (pin 13)) + (node (ref C19) (pin 1)) + (node (ref C21) (pin 1))) + (net (code 43) (name VFPGA33) + (node (ref C42) (pin 1)) + (node (ref U7) (pin 1)) + (node (ref U7) (pin 41)) (node (ref C55) (pin 1)) - (node (ref C53) (pin 1)) - (node (ref C50) (pin 1)) - (node (ref C202) (pin 1)) - (node (ref C51) (pin 1)) - (node (ref C203) (pin 1)) - (node (ref U3) (pin 63)) - (node (ref C201) (pin 1)) - (node (ref C54) (pin 1)) - (node (ref U3) (pin 49)) - (node (ref X601) (pin 4)) - (node (ref U201) (pin 4)) - (node (ref C27) (pin 1)) - (node (ref U3) (pin 76)) - (node (ref C29) (pin 1)) - (node (ref U901) (pin 8)) - (node (ref U3) (pin 95)) - (node (ref C28) (pin 1)) (node (ref U3) (pin 83)) - (node (ref C24) (pin 1)) - (node (ref U3) (pin 128)) - (node (ref U3) (pin 4)) - (node (ref U3) (pin 136)) - (node (ref U3) (pin 112)) - (node (ref P3) (pin 6)) - (node (ref 100n601) (pin 1)) - (node (ref U3) (pin 23)) - (node (ref C44) (pin 1)) - (node (ref U3) (pin 60)) - (node (ref U7) (pin 27)) - (node (ref U7) (pin 28)) - (node (ref C52) (pin 1)) - (node (ref U7) (pin 54)) - (node (ref C46) (pin 1)) (node (ref C47) (pin 1)) (node (ref C48) (pin 1)) (node (ref C49) (pin 1)) - (node (ref U6) (pin 3)) - (node (ref U3) (pin 117)) - (node (ref C30) (pin 1)) - (node (ref C10) (pin 1)) - (node (ref U3) (pin 140)) - (node (ref Q5) (pin 3)) - (node (ref U3) (pin 67)) - (node (ref C8) (pin 1)) - (node (ref U3) (pin 85)) + (node (ref C46) (pin 1)) + (node (ref C28) (pin 1)) + (node (ref U3) (pin 4)) + (node (ref U3) (pin 112)) + (node (ref C27) (pin 1)) + (node (ref U3) (pin 49)) + (node (ref U3) (pin 136)) + (node (ref C29) (pin 1)) + (node (ref U3) (pin 128)) + (node (ref C24) (pin 1)) + (node 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(code 195) (name /audio/AOUTR) + (node (ref C904) (pin 1)) + (node (ref R902) (pin 2)) + (node (ref J901) (pin 3))) + (net (code 196) (name /audio/AOUTL) + (node (ref C903) (pin 1)) + (node (ref R901) (pin 1)) + (node (ref J901) (pin 2))) + (net (code 197) (name /audio/DACR) (node (ref U201) (pin 16)) - (node (ref U901) (pin 6))) - (net (code 206) (name /audio/DACL) - (node (ref U901) (pin 2)) - (node (ref U201) (pin 14))) - (net (code 207) (name "Net-(C904-Pad2)") + (node (ref U901) (pin 5))) + (net (code 198) (name "Net-(R9-Pad1)") + (node (ref R9) (pin 1)) + (node (ref U201) (pin 7))) + (net (code 199) (name /audio/FBR) (node (ref C904) (pin 2)) (node (ref U901) (pin 7)) - (node (ref U901) (pin 5))) - (net (code 208) (name "Net-(C903-Pad2)") - (node (ref U901) (pin 3)) - (node (ref U901) (pin 1)) - (node (ref C903) (pin 2))) - (net (code 209) (name /audio/DACVREF) + (node (ref U901) (pin 6))) + (net (code 200) (name /audio/DACL) + (node (ref U201) (pin 14)) + (node (ref U901) (pin 3))) + (net (code 201) (name /audio/DACVREF) (node (ref C902) (pin 1)) (node (ref C901) (pin 1)) (node (ref U201) (pin 12))) - (net (code 210) (name /audio/ABCLK) - (node (ref U201) (pin 10))) - (net (code 211) (name /audio/AOUTR) - (node (ref J901) (pin 3)) - (node (ref R902) (pin 2)) - (node (ref C904) (pin 1))) - (net (code 212) (name /audio/AOUTL) - (node (ref J901) (pin 2)) - (node (ref R901) (pin 1)) - (node (ref C903) (pin 1))) - (net (code 213) (name /FSMC/A23) - (node (ref U3) (pin 5)) - (node (ref U4) (pin 1))) - (net (code 214) (name /FSMC/A22) - (node (ref U4) (pin 5)) - (node (ref U3) (pin 9))) - (net (code 215) (name /FSMC/A21) - (node (ref U3) (pin 8)) - (node (ref U4) (pin 4))) - (net (code 216) (name /FSMC/A20) + (net (code 202) (name /audio/FBL) + (node (ref C903) (pin 2)) + (node (ref U901) (pin 2)) + (node (ref U901) (pin 1))) + (net (code 203) (name /FSMC/A23) + (node (ref U4) (pin 1)) + (node (ref U3) (pin 5))) + (net (code 204) (name /FSMC/A22) + (node (ref U3) (pin 9)) + (node (ref U4) (pin 5))) + (net (code 205) (name /FSMC/A21) + (node (ref U4) (pin 4)) + (node (ref U3) (pin 8))) + (net (code 206) (name /FSMC/A20) (node (ref U4) (pin 3)) (node (ref U3) (pin 7))) - (net (code 217) (name /FSMC/A19) - (node (ref U4) (pin 2)) - (node (ref U3) (pin 6))))) \ No newline at end of file + (net (code 207) (name /FSMC/A19) + (node (ref U3) (pin 6)) + (node (ref U4) (pin 2))))) \ No newline at end of file diff --git a/fpgna.sch b/fpgna.sch index e8beb62..4c46502 100644 --- a/fpgna.sch +++ b/fpgna.sch @@ -64,6 +64,7 @@ F3 "USB_PRESENT_N" O R 2750 2600 60 F4 "CHARGE_ENABLE" I R 2750 2400 60 F5 "SYS_VOLTAGE" O R 2750 2200 60 F6 "FPGA_ENABLE_N" I R 2750 2500 60 +F7 "BACKLIGHT_EN_N" I L 1750 2850 60 $EndSheet $Sheet S 1750 3400 1000 1100 @@ -93,6 +94,7 @@ F9 "T_CS" O R 7950 3300 60 F10 "T_CLK" O R 7950 3200 60 F11 "T_DOUT" I R 7950 3500 60 F12 "T_DIN" O R 7950 3400 60 +F13 "BACKLIGHT_EN_N" O L 5900 4700 60 $EndSheet $Sheet S 8100 3050 1750 800 @@ -246,4 +248,10 @@ Wire Wire Line 2900 3750 2750 3750 Wire Wire Line 4350 3400 4100 3400 +Wire Wire Line + 5900 4700 1650 4700 +Wire Wire Line + 1650 4700 1650 2850 +Wire Wire Line + 1650 2850 1750 2850 $EndSCHEMATC diff --git a/power.sch b/power.sch index 91ed6dc..b53331d 100644 --- a/power.sch +++ b/power.sch @@ -68,10 +68,10 @@ F 5 "Makise Kurisu " H 1800 6600 60 0001 C CNN "Author" 1 0 0 -1 $EndComp $Comp -L +1V2 #PWR226 +L +1V2 #PWR26 U 1 1 56323D6C P 3950 4850 -F 0 "#PWR226" H 3950 4700 50 0001 C CNN +F 0 "#PWR26" H 3950 4700 50 0001 C CNN F 1 "+1V2" H 3950 4990 50 0000 C CNN F 2 "" H 3950 4850 60 0000 C CNN F 3 "" H 3950 4850 60 0000 C CNN @@ -79,10 +79,10 @@ F 3 "" H 3950 4850 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR225 +L GND #PWR25 U 1 1 56323EF3 P 3900 6250 -F 0 "#PWR225" H 3900 6000 50 0001 C CNN +F 0 "#PWR25" H 3900 6000 50 0001 C CNN F 1 "GND" H 3900 6100 50 0000 C CNN F 2 "" H 3900 6250 60 0000 C CNN F 3 "" H 3900 6250 60 0000 C CNN @@ -90,10 +90,10 @@ F 3 "" H 3900 6250 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR233 +L GND #PWR33 U 1 1 56323F5A P 5350 4950 -F 0 "#PWR233" H 5350 4700 50 0001 C CNN +F 0 "#PWR33" H 5350 4700 50 0001 C CNN F 1 "GND" H 5350 4800 50 0000 C CNN F 2 "" H 5350 4950 60 0000 C CNN F 3 "" H 5350 4950 60 0000 C CNN @@ -156,10 +156,10 @@ F 3 "" H 3700 2050 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR227 +L GND #PWR27 U 1 1 56325A76 P 4250 2300 -F 0 "#PWR227" H 4250 2050 50 0001 C CNN +F 0 "#PWR27" H 4250 2050 50 0001 C CNN F 1 "GND" H 4250 2150 50 0000 C CNN F 2 "" H 4250 2300 60 0000 C CNN F 3 "" H 4250 2300 60 0000 C CNN @@ -189,10 +189,10 @@ F 3 "" H 5400 1850 60 0000 C CNN 0 -1 -1 0 $EndComp $Comp -L +1V2 #PWR235 +L +1V2 #PWR35 U 1 1 56325E26 P 5800 1750 -F 0 "#PWR235" H 5800 1600 50 0001 C CNN +F 0 "#PWR35" H 5800 1600 50 0001 C CNN F 1 "+1V2" H 5800 1890 50 0000 C CNN F 2 "" H 5800 1750 60 0000 C CNN F 3 "" H 5800 1750 60 0000 C CNN @@ -277,10 +277,10 @@ F 3 "" H 5500 4050 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L +1V2 #PWR231 +L +1V2 #PWR31 U 1 1 56326FC5 P 4750 3800 -F 0 "#PWR231" H 4750 3650 50 0001 C CNN +F 0 "#PWR31" H 4750 3650 50 0001 C CNN F 1 "+1V2" H 4750 3940 50 0000 C CNN F 2 "" H 4750 3800 60 0000 C CNN F 3 "" H 4750 3800 60 0000 C CNN @@ -288,10 +288,10 @@ F 3 "" H 4750 3800 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR232 +L GND #PWR32 U 1 1 5632709B P 4750 4300 -F 0 "#PWR232" H 4750 4050 50 0001 C CNN +F 0 "#PWR32" H 4750 4050 50 0001 C CNN F 1 "GND" H 4750 4150 50 0000 C CNN F 2 "" H 4750 4300 60 0000 C CNN F 3 "" H 4750 4300 60 0000 C CNN @@ -376,10 +376,10 @@ F 3 "" H 5250 3050 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR230 +L GND #PWR30 U 1 1 5632751F P 4750 3300 -F 0 "#PWR230" H 4750 3050 50 0001 C CNN +F 0 "#PWR30" H 4750 3050 50 0001 C CNN F 1 "GND" H 4750 3150 50 0000 C CNN F 2 "" H 4750 3300 60 0000 C CNN F 3 "" H 4750 3300 60 0000 C CNN @@ -420,10 +420,10 @@ F 3 "" V 7450 1050 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR243 +L GND #PWR43 U 1 1 56330682 P 7700 1500 -F 0 "#PWR243" H 7700 1250 50 0001 C CNN +F 0 "#PWR43" H 7700 1250 50 0001 C CNN F 1 "GND" H 7700 1350 50 0000 C CNN F 2 "" H 7700 1500 60 0000 C CNN F 3 "" H 7700 1500 60 0000 C CNN @@ -464,10 +464,10 @@ F 3 "" H 7750 3050 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VUSB #PWR239 +L VUSB #PWR39 U 1 1 56C1E573 P 7050 1200 -F 0 "#PWR239" H 7050 1050 50 0001 C CNN +F 0 "#PWR39" H 7050 1050 50 0001 C CNN F 1 "VUSB" H 7068 1374 50 0000 C CNN F 2 "" H 7050 1200 50 0000 C CNN F 3 "" H 7050 1200 50 0000 C CNN @@ -475,10 +475,10 @@ F 3 "" H 7050 1200 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VBAT #PWR250 +L VBAT #PWR50 U 1 1 56C1ED5D P 8600 2750 -F 0 "#PWR250" H 8600 2600 50 0001 C CNN +F 0 "#PWR50" H 8600 2600 50 0001 C CNN F 1 "VBAT" H 8600 2890 50 0000 C CNN F 2 "" H 8600 2750 50 0000 C CNN F 3 "" H 8600 2750 50 0000 C CNN @@ -486,10 +486,10 @@ F 3 "" H 8600 2750 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VUSB #PWR241 +L VUSB #PWR41 U 1 1 56C1F811 P 7500 2750 -F 0 "#PWR241" H 7500 2600 50 0001 C CNN +F 0 "#PWR41" H 7500 2600 50 0001 C CNN F 1 "VUSB" H 7500 2890 50 0000 C CNN F 2 "" H 7500 2750 50 0000 C CNN F 3 "" H 7500 2750 50 0000 C CNN @@ -503,31 +503,31 @@ USB_PRESENT_N $Comp L CONN_01X03 P2 U 1 1 56C22F77 -P 10050 3250 -F 0 "P2" H 10127 3341 50 0000 L CNN -F 1 "BAT" H 10127 3249 50 0000 L CNN -F 2 "" H 10050 3250 50 0001 C CNN -F 3 "" H 10050 3250 50 0000 C CNN -F 4 "TODO: Verify pinout" H 10127 3150 60 0000 L CNN "TODO" - 1 10050 3250 +P 9100 3250 +F 0 "P2" H 9177 3341 50 0000 L CNN +F 1 "BAT" H 9177 3249 50 0000 L CNN +F 2 "" H 9100 3250 50 0001 C CNN +F 3 "" H 9100 3250 50 0000 C CNN +F 4 "TODO: Verify pinout" H 9177 3150 60 0000 L CNN "TODO" + 1 9100 3250 1 0 0 -1 $EndComp $Comp -L VBAT #PWR260 +L VBAT #PWR52 U 1 1 56C23113 -P 9800 2750 -F 0 "#PWR260" H 9800 2600 50 0001 C CNN -F 1 "VBAT" H 9800 2890 50 0000 C CNN -F 2 "" H 9800 2750 50 0000 C CNN -F 3 "" H 9800 2750 50 0000 C CNN - 1 9800 2750 +P 8850 2750 +F 0 "#PWR52" H 8850 2600 50 0001 C CNN +F 1 "VBAT" H 8850 2890 50 0000 C CNN +F 2 "" H 8850 2750 50 0000 C CNN +F 3 "" H 8850 2750 50 0000 C CNN + 1 8850 2750 1 0 0 -1 $EndComp $Comp -L GND #PWR242 +L GND #PWR42 U 1 1 56C23816 P 7500 3950 -F 0 "#PWR242" H 7500 3700 50 0001 C CNN +F 0 "#PWR42" H 7500 3700 50 0001 C CNN F 1 "GND" H 7500 3800 50 0000 C CNN F 2 "" H 7500 3950 60 0000 C CNN F 3 "" H 7500 3950 60 0000 C CNN @@ -535,14 +535,14 @@ F 3 "" H 7500 3950 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR261 +L GND #PWR53 U 1 1 56C23E07 -P 9800 3950 -F 0 "#PWR261" H 9800 3700 50 0001 C CNN -F 1 "GND" H 9800 3800 50 0000 C CNN -F 2 "" H 9800 3950 60 0000 C CNN -F 3 "" H 9800 3950 60 0000 C CNN - 1 9800 3950 +P 8850 3400 +F 0 "#PWR53" H 8850 3150 50 0001 C CNN +F 1 "GND" H 8850 3250 50 0000 C CNN +F 2 "" H 8850 3400 60 0000 C CNN +F 3 "" H 8850 3400 60 0000 C CNN + 1 8850 3400 1 0 0 -1 $EndComp $Comp @@ -553,25 +553,26 @@ F 0 "R8" V 8680 3700 50 0000 C CNN F 1 "2.2k" V 8600 3700 50 0000 C CNN F 2 "" V 8530 3700 30 0001 C CNN F 3 "" H 8600 3700 30 0000 C CNN +F 4 "TODO: Check value" H 9150 3700 60 0000 C CNN "TODO" 1 8600 3700 1 0 0 -1 $EndComp $Comp -L GND #PWR251 +L GND #PWR51 U 1 1 56C253CE -P 8600 3950 -F 0 "#PWR251" H 8600 3700 50 0001 C CNN -F 1 "GND" H 8600 3800 50 0000 C CNN -F 2 "" H 8600 3950 60 0000 C CNN -F 3 "" H 8600 3950 60 0000 C CNN - 1 8600 3950 +P 8600 4500 +F 0 "#PWR51" H 8600 4250 50 0001 C CNN +F 1 "GND" H 8600 4350 50 0000 C CNN +F 2 "" H 8600 4500 60 0000 C CNN +F 3 "" H 8600 4500 60 0000 C CNN + 1 8600 4500 1 0 0 -1 $EndComp $Comp -L VUSB #PWR249 +L VUSB #PWR49 U 1 1 56C2BB98 P 8600 950 -F 0 "#PWR249" H 8600 800 50 0001 C CNN +F 0 "#PWR49" H 8600 800 50 0001 C CNN F 1 "VUSB" H 8600 1090 50 0000 C CNN F 2 "" H 8600 950 50 0000 C CNN F 3 "" H 8600 950 50 0000 C CNN @@ -579,10 +580,10 @@ F 3 "" H 8600 950 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VBAT #PWR248 +L VBAT #PWR48 U 1 1 56C2D4CD P 8400 950 -F 0 "#PWR248" H 8400 800 50 0001 C CNN +F 0 "#PWR48" H 8400 800 50 0001 C CNN F 1 "VBAT" H 8400 1090 50 0000 C CNN F 2 "" H 8400 950 50 0000 C CNN F 3 "" H 8400 950 50 0000 C CNN @@ -612,10 +613,10 @@ F 3 "" H 8900 1950 30 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR253 +L GND #PWR54 U 1 1 56C307A1 P 8900 2150 -F 0 "#PWR253" H 8900 1900 50 0001 C CNN +F 0 "#PWR54" H 8900 1900 50 0001 C CNN F 1 "GND" H 8900 2000 50 0000 C CNN F 2 "" H 8900 2150 60 0000 C CNN F 3 "" H 8900 2150 60 0000 C CNN @@ -634,10 +635,10 @@ F 3 "" V 8900 1050 50 0000 C CNN -1 0 0 1 $EndComp $Comp -L VSYS #PWR205 +L VSYS #PWR5 U 1 1 56C39868 P 1000 1000 -F 0 "#PWR205" H 1000 850 50 0001 C CNN +F 0 "#PWR5" H 1000 850 50 0001 C CNN F 1 "VSYS" H 1000 1140 50 0000 C CNN F 2 "" H 1000 1000 50 0000 C CNN F 3 "" H 1000 1000 50 0000 C CNN @@ -645,10 +646,10 @@ F 3 "" H 1000 1000 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VSYS #PWR256 +L VSYS #PWR56 U 1 1 56C39AFF P 9350 950 -F 0 "#PWR256" H 9350 800 50 0001 C CNN +F 0 "#PWR56" H 9350 800 50 0001 C CNN F 1 "VSYS" H 9350 1090 50 0000 C CNN F 2 "" H 9350 950 50 0000 C CNN F 3 "" H 9350 950 50 0000 C CNN @@ -667,83 +668,17 @@ F 3 "" H 7250 2950 30 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR252 -U 1 1 56C4E595 -P 8850 3950 -F 0 "#PWR252" H 8850 3700 50 0001 C CNN -F 1 "GND" H 8850 3800 50 0000 C CNN -F 2 "" H 8850 3950 60 0000 C CNN -F 3 "" H 8850 3950 60 0000 C CNN - 1 8850 3950 - 1 0 0 -1 -$EndComp -$Comp -L VUSB #PWR254 -U 1 1 56C4F548 -P 9200 2750 -F 0 "#PWR254" H 9200 2600 50 0001 C CNN -F 1 "VUSB" H 9200 2890 50 0000 C CNN -F 2 "" H 9200 2750 50 0000 C CNN -F 3 "" H 9200 2750 50 0000 C CNN - 1 9200 2750 - 1 0 0 -1 -$EndComp -$Comp -L GND #PWR255 -U 1 1 56C4FA15 -P 9200 3950 -F 0 "#PWR255" H 9200 3700 50 0001 C CNN -F 1 "GND" H 9200 3800 50 0000 C CNN -F 2 "" H 9200 3950 60 0000 C CNN -F 3 "" H 9200 3950 60 0000 C CNN - 1 9200 3950 - 1 0 0 -1 -$EndComp -$Comp -L R R9 -U 1 1 56C4F34C -P 9200 3150 -F 0 "R9" V 9280 3150 50 0000 C CNN -F 1 "10k" V 9200 3150 50 0000 C CNN -F 2 "" V 9130 3150 30 0001 C CNN -F 3 "" H 9200 3150 30 0000 C CNN - 1 9200 3150 - 1 0 0 -1 -$EndComp -$Comp L R R12 U 1 1 56C590A7 -P 10000 3550 -F 0 "R12" V 10080 3550 50 0000 C CNN -F 1 "500" V 10000 3550 50 0000 C CNN -F 2 "" V 9930 3550 30 0001 C CNN -F 3 "" H 10000 3550 30 0000 C CNN - 1 10000 3550 - 0 1 1 0 -$EndComp -$Comp -L R R11 -U 1 1 56C592CD -P 9550 3750 -F 0 "R11" V 9630 3750 50 0000 C CNN -F 1 "10k" V 9550 3750 50 0000 C CNN -F 2 "" V 9480 3750 30 0001 C CNN -F 3 "" H 9550 3750 30 0000 C CNN - 1 9550 3750 +P 8950 4300 +F 0 "R12" V 9030 4300 50 0000 C CNN +F 1 "10k" V 8950 4300 50 0000 C CNN +F 2 "" V 8880 4300 30 0001 C CNN +F 3 "" H 8950 4300 30 0000 C CNN + 1 8950 4300 -1 0 0 1 $EndComp -$Comp -L GND #PWR257 -U 1 1 56C59A2E -P 9550 3950 -F 0 "#PWR257" H 9550 3700 50 0001 C CNN -F 1 "GND" H 9550 3800 50 0000 C CNN -F 2 "" H 9550 3950 60 0000 C CNN -F 3 "" H 9550 3950 60 0000 C CNN - 1 9550 3950 - 1 0 0 -1 -$EndComp -Text HLabel 10200 3550 2 60 Input ~ 0 +Text HLabel 9100 4100 2 60 Input ~ 0 CHARGE_ENABLE $Comp L R R5 @@ -768,10 +703,10 @@ F 3 "" H 9700 1550 30 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VSYS #PWR258 +L VSYS #PWR57 U 1 1 56C208D6 P 9700 950 -F 0 "#PWR258" H 9700 800 50 0001 C CNN +F 0 "#PWR57" H 9700 800 50 0001 C CNN F 1 "VSYS" H 9700 1090 50 0000 C CNN F 2 "" H 9700 950 50 0000 C CNN F 3 "" H 9700 950 50 0000 C CNN @@ -779,10 +714,10 @@ F 3 "" H 9700 950 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR259 +L GND #PWR58 U 1 1 56C20CEB P 9700 1800 -F 0 "#PWR259" H 9700 1550 50 0001 C CNN +F 0 "#PWR58" H 9700 1550 50 0001 C CNN F 1 "GND" H 9700 1650 50 0000 C CNN F 2 "" H 9700 1800 60 0000 C CNN F 3 "" H 9700 1800 60 0000 C CNN @@ -825,10 +760,10 @@ F 3 "" H 1500 1500 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR206 +L GND #PWR6 U 1 1 56C35DE1 P 1000 1850 -F 0 "#PWR206" H 1000 1600 50 0001 C CNN +F 0 "#PWR6" H 1000 1600 50 0001 C CNN F 1 "GND" H 1000 1700 50 0000 C CNN F 2 "" H 1000 1850 60 0000 C CNN F 3 "" H 1000 1850 60 0000 C CNN @@ -836,10 +771,10 @@ F 3 "" H 1000 1850 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR209 +L GND #PWR9 U 1 1 56C35F4F P 1750 1850 -F 0 "#PWR209" H 1750 1600 50 0001 C CNN +F 0 "#PWR9" H 1750 1600 50 0001 C CNN F 1 "GND" H 1750 1700 50 0000 C CNN F 2 "" H 1750 1850 60 0000 C CNN F 3 "" H 1750 1850 60 0000 C CNN @@ -847,10 +782,10 @@ F 3 "" H 1750 1850 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR208 +L GND #PWR8 U 1 1 56C360EB P 1400 1850 -F 0 "#PWR208" H 1400 1600 50 0001 C CNN +F 0 "#PWR8" H 1400 1600 50 0001 C CNN F 1 "GND" H 1400 1700 50 0000 C CNN F 2 "" H 1400 1850 60 0000 C CNN F 3 "" H 1400 1850 60 0000 C CNN @@ -869,10 +804,10 @@ F 3 "" V 2100 1450 50 0000 C CNN 0 1 1 0 $EndComp $Comp -L GND #PWR214 +L GND #PWR14 U 1 1 56C2CFDF P 2100 1850 -F 0 "#PWR214" H 2100 1600 50 0001 C CNN +F 0 "#PWR14" H 2100 1600 50 0001 C CNN F 1 "GND" H 2100 1700 50 0000 C CNN F 2 "" H 2100 1850 60 0000 C CNN F 3 "" H 2100 1850 60 0000 C CNN @@ -902,10 +837,10 @@ F 3 "" H 2850 1500 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR218 +L GND #PWR18 U 1 1 56C2E498 P 2850 1850 -F 0 "#PWR218" H 2850 1600 50 0001 C CNN +F 0 "#PWR18" H 2850 1600 50 0001 C CNN F 1 "GND" H 2850 1700 50 0000 C CNN F 2 "" H 2850 1850 60 0000 C CNN F 3 "" H 2850 1850 60 0000 C CNN @@ -924,10 +859,10 @@ F 3 "" H 750 1400 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR201 +L GND #PWR1 U 1 1 56C2F49B P 750 1850 -F 0 "#PWR201" H 750 1600 50 0001 C CNN +F 0 "#PWR1" H 750 1600 50 0001 C CNN F 1 "GND" H 750 1700 50 0000 C CNN F 2 "" H 750 1850 60 0000 C CNN F 3 "" H 750 1850 60 0000 C CNN @@ -935,10 +870,10 @@ F 3 "" H 750 1850 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VSTM33 #PWR219 +L VSTM33 #PWR19 U 1 1 56C326BF P 2950 1050 -F 0 "#PWR219" H 2950 900 50 0001 C CNN +F 0 "#PWR19" H 2950 900 50 0001 C CNN F 1 "VSTM33" H 2950 1190 50 0000 C CNN F 2 "" H 2950 1050 50 0000 C CNN F 3 "" H 2950 1050 50 0000 C CNN @@ -946,10 +881,10 @@ F 3 "" H 2950 1050 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VFPGA33 #PWR222 +L VFPGA33 #PWR22 U 1 1 56C350CF P 3700 1750 -F 0 "#PWR222" H 3700 1600 50 0001 C CNN +F 0 "#PWR22" H 3700 1600 50 0001 C CNN F 1 "VFPGA33" H 3700 1890 50 0000 C CNN F 2 "" H 3700 1750 50 0000 C CNN F 3 "" H 3700 1750 50 0000 C CNN @@ -968,10 +903,10 @@ F 3 "http://www.digikey.com/product-search/en/discrete-semiconductor-products/fe 0 1 -1 0 $EndComp $Comp -L VSTM33 #PWR221 +L VSTM33 #PWR21 U 1 1 56C36219 P 3700 950 -F 0 "#PWR221" H 3700 800 50 0001 C CNN +F 0 "#PWR21" H 3700 800 50 0001 C CNN F 1 "VSTM33" H 3700 1090 50 0000 C CNN F 2 "" H 3700 950 50 0000 C CNN F 3 "" H 3700 950 50 0000 C CNN @@ -979,10 +914,10 @@ F 3 "" H 3700 950 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VFPGA33 #PWR228 +L VFPGA33 #PWR28 U 1 1 56C36471 P 4400 950 -F 0 "#PWR228" H 4400 800 50 0001 C CNN +F 0 "#PWR28" H 4400 800 50 0001 C CNN F 1 "VFPGA33" H 4400 1090 50 0000 C CNN F 2 "" H 4400 950 50 0000 C CNN F 3 "" H 4400 950 50 0000 C CNN @@ -1005,23 +940,12 @@ FPGA_ENABLE_N $Comp L Q_NMOS_DGS Q2 U 1 1 56C543A2 -P 8950 3350 -F 0 "Q2" H 9144 3396 50 0000 L CNN -F 1 "NMOS-LPLL" H 9144 3304 50 0000 L CNN -F 2 "" H 9150 3450 50 0001 C CNN -F 3 "" H 8950 3350 50 0000 C CNN - 1 8950 3350 - -1 0 0 -1 -$EndComp -$Comp -L Q_NMOS_DGS Q4 -U 1 1 56C56373 -P 9300 3550 -F 0 "Q4" H 9494 3596 50 0000 L CNN -F 1 "NMOS-LPLL" H 9494 3504 50 0000 L CNN -F 2 "" H 9500 3650 50 0001 C CNN -F 3 "" H 9300 3550 50 0000 C CNN - 1 9300 3550 +P 8700 4100 +F 0 "Q2" H 8894 4146 50 0000 L CNN +F 1 "NMOS-LPLL" H 8894 4054 50 0000 L CNN +F 2 "" H 8900 4200 50 0001 C CNN +F 3 "" H 8700 4100 50 0000 C CNN + 1 8700 4100 -1 0 0 -1 $EndComp $Comp @@ -1037,10 +961,10 @@ F 3 "" H 1000 4200 60 0000 C CNN $EndComp NoConn ~ 7550 3250 $Comp -L GND #PWR215 +L GND #PWR15 U 1 1 56C4E388 P 2200 5200 -F 0 "#PWR215" H 2200 4950 50 0001 C CNN +F 0 "#PWR15" H 2200 4950 50 0001 C CNN F 1 "GND" H 2200 5050 50 0000 C CNN F 2 "" H 2200 5200 50 0000 C CNN F 3 "" H 2200 5200 50 0000 C CNN @@ -1048,10 +972,10 @@ F 3 "" H 2200 5200 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VSTM33 #PWR240 +L VSTM33 #PWR40 U 1 1 56C54669 P 7250 2750 -F 0 "#PWR240" H 7250 2600 50 0001 C CNN +F 0 "#PWR40" H 7250 2600 50 0001 C CNN F 1 "VSTM33" H 7250 2890 50 0000 C CNN F 2 "" H 7250 2750 50 0000 C CNN F 3 "" H 7250 2750 50 0000 C CNN @@ -1059,10 +983,10 @@ F 3 "" H 7250 2750 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VSTM33 #PWR207 +L VSTM33 #PWR7 U 1 1 56C58A5C P 1250 3450 -F 0 "#PWR207" H 1250 3300 50 0001 C CNN +F 0 "#PWR7" H 1250 3300 50 0001 C CNN F 1 "VSTM33" H 1250 3590 50 0000 C CNN F 2 "" H 1250 3450 50 0000 C CNN F 3 "" H 1250 3450 50 0000 C CNN @@ -1092,10 +1016,10 @@ F 3 "" H 800 5000 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR204 +L GND #PWR4 U 1 1 56C5D446 P 900 5200 -F 0 "#PWR204" H 900 4950 50 0001 C CNN +F 0 "#PWR4" H 900 4950 50 0001 C CNN F 1 "GND" H 900 5050 50 0000 C CNN F 2 "" H 900 5200 50 0000 C CNN F 3 "" H 900 5200 50 0000 C CNN @@ -1118,10 +1042,10 @@ VCAP1 Text Label 1000 4800 0 60 ~ 0 VCAP2 $Comp -L VFPGA33 #PWR229 +L VFPGA33 #PWR29 U 1 1 56C4A0C6 P 4750 2800 -F 0 "#PWR229" H 4750 2650 50 0001 C CNN +F 0 "#PWR29" H 4750 2650 50 0001 C CNN F 1 "VFPGA33" H 4750 2940 50 0000 C CNN F 2 "" H 4750 2800 50 0000 C CNN F 3 "" H 4750 2800 50 0000 C CNN @@ -1206,10 +1130,10 @@ F 3 "" H 2750 2700 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR211 +L GND #PWR11 U 1 1 56C506AD P 1750 2950 -F 0 "#PWR211" H 1750 2700 50 0001 C CNN +F 0 "#PWR11" H 1750 2700 50 0001 C CNN F 1 "GND" H 1750 2800 50 0000 C CNN F 2 "" H 1750 2950 60 0000 C CNN F 3 "" H 1750 2950 60 0000 C CNN @@ -1217,10 +1141,10 @@ F 3 "" H 1750 2950 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VSTM33 #PWR210 +L VSTM33 #PWR10 U 1 1 56C509AA P 1750 2450 -F 0 "#PWR210" H 1750 2300 50 0001 C CNN +F 0 "#PWR10" H 1750 2300 50 0001 C CNN F 1 "VSTM33" H 1750 2590 50 0000 C CNN F 2 "" H 1750 2450 50 0000 C CNN F 3 "" H 1750 2450 50 0000 C CNN @@ -1261,10 +1185,10 @@ F 3 "" H 7950 1250 30 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR245 +L GND #PWR45 U 1 1 56C5AF1C P 7950 1500 -F 0 "#PWR245" H 7950 1250 50 0001 C CNN +F 0 "#PWR45" H 7950 1250 50 0001 C CNN F 1 "GND" H 7950 1350 50 0000 C CNN F 2 "" H 7950 1500 60 0000 C CNN F 3 "" H 7950 1500 60 0000 C CNN @@ -1294,10 +1218,10 @@ F 3 "" H 3650 7000 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR220 +L GND #PWR20 U 1 1 56C58F25 P 3650 7300 -F 0 "#PWR220" H 3650 7050 50 0001 C CNN +F 0 "#PWR20" H 3650 7050 50 0001 C CNN F 1 "GND" H 3650 7150 50 0000 C CNN F 2 "" H 3650 7300 60 0000 C CNN F 3 "" H 3650 7300 60 0000 C CNN @@ -1305,10 +1229,10 @@ F 3 "" H 3650 7300 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR236 +L GND #PWR36 U 1 1 56C592D8 P 5850 7300 -F 0 "#PWR236" H 5850 7050 50 0001 C CNN +F 0 "#PWR36" H 5850 7050 50 0001 C CNN F 1 "GND" H 5850 7150 50 0000 C CNN F 2 "" H 5850 7300 60 0000 C CNN F 3 "" H 5850 7300 60 0000 C CNN @@ -1327,10 +1251,10 @@ F 3 "http://www.digikey.com/product-search/en/discrete-semiconductor-products/fe 0 1 -1 0 $EndComp $Comp -L VFPGA33 #PWR224 +L VFPGA33 #PWR24 U 1 1 56C61112 P 3850 6800 -F 0 "#PWR224" H 3850 6650 50 0001 C CNN +F 0 "#PWR24" H 3850 6650 50 0001 C CNN F 1 "VFPGA33" H 3868 6974 50 0000 C CNN F 2 "" H 3850 6800 50 0000 C CNN F 3 "" H 3850 6800 50 0000 C CNN @@ -1362,10 +1286,10 @@ F 3 "" H 4650 7000 30 0000 C CNN 0 1 1 0 $EndComp $Comp -L VFPGA33 #PWR234 +L VFPGA33 #PWR34 U 1 1 56C69ECC P 5550 4850 -F 0 "#PWR234" H 5550 4700 50 0001 C CNN +F 0 "#PWR34" H 5550 4700 50 0001 C CNN F 1 "VFPGA33" H 5568 5024 50 0000 C CNN F 2 "" H 5550 4850 50 0000 C CNN F 3 "" H 5550 4850 50 0000 C CNN @@ -1373,10 +1297,10 @@ F 3 "" H 5550 4850 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VFPGA33 #PWR223 +L VFPGA33 #PWR23 U 1 1 56C69FA9 P 3700 4850 -F 0 "#PWR223" H 3700 4700 50 0001 C CNN +F 0 "#PWR23" H 3700 4700 50 0001 C CNN F 1 "VFPGA33" H 3718 5024 50 0000 C CNN F 2 "" H 3700 4850 50 0000 C CNN F 3 "" H 3700 4850 50 0000 C CNN @@ -1408,10 +1332,10 @@ F 3 "" H 1100 6100 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VFPGA33 #PWR202 +L VFPGA33 #PWR2 U 1 1 56C7605B P 850 6000 -F 0 "#PWR202" H 850 5850 50 0001 C CNN +F 0 "#PWR2" H 850 5850 50 0001 C CNN F 1 "VFPGA33" H 868 6174 50 0000 C CNN F 2 "" H 850 6000 50 0000 C CNN F 3 "" H 850 6000 50 0000 C CNN @@ -1419,10 +1343,10 @@ F 3 "" H 850 6000 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VFPGA33 #PWR212 +L VFPGA33 #PWR12 U 1 1 56C7613E P 1900 6000 -F 0 "#PWR212" H 1900 5850 50 0001 C CNN +F 0 "#PWR12" H 1900 5850 50 0001 C CNN F 1 "VFPGA33" H 1918 6174 50 0000 C CNN F 2 "" H 1900 6000 50 0000 C CNN F 3 "" H 1900 6000 50 0000 C CNN @@ -1430,10 +1354,10 @@ F 3 "" H 1900 6000 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR203 +L GND #PWR3 U 1 1 56C779A7 P 850 7050 -F 0 "#PWR203" H 850 6800 50 0001 C CNN +F 0 "#PWR3" H 850 6800 50 0001 C CNN F 1 "GND" H 850 6900 50 0000 C CNN F 2 "" H 850 7050 60 0000 C CNN F 3 "" H 850 7050 60 0000 C CNN @@ -1441,10 +1365,10 @@ F 3 "" H 850 7050 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR213 +L GND #PWR13 U 1 1 56C77AD2 P 1900 7050 -F 0 "#PWR213" H 1900 6800 50 0001 C CNN +F 0 "#PWR13" H 1900 6800 50 0001 C CNN F 1 "GND" H 1900 6900 50 0000 C CNN F 2 "" H 1900 7050 60 0000 C CNN F 3 "" H 1900 7050 60 0000 C CNN @@ -1496,10 +1420,10 @@ F 3 "" H 2850 6500 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR217 +L GND #PWR17 U 1 1 56C7870C P 2350 6750 -F 0 "#PWR217" H 2350 6500 50 0001 C CNN +F 0 "#PWR17" H 2350 6500 50 0001 C CNN F 1 "GND" H 2350 6600 50 0000 C CNN F 2 "" H 2350 6750 60 0000 C CNN F 3 "" H 2350 6750 60 0000 C CNN @@ -1507,10 +1431,10 @@ F 3 "" H 2350 6750 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VFPGA33 #PWR216 +L VFPGA33 #PWR16 U 1 1 56C78A86 P 2350 6250 -F 0 "#PWR216" H 2350 6100 50 0001 C CNN +F 0 "#PWR16" H 2350 6100 50 0001 C CNN F 1 "VFPGA33" H 2368 6424 50 0000 C CNN F 2 "" H 2350 6250 50 0000 C CNN F 3 "" H 2350 6250 50 0000 C CNN @@ -1529,10 +1453,10 @@ F 3 "" H 6950 5900 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VFPGA33 #PWR237 +L VFPGA33 #PWR37 U 1 1 56CA7120 P 6700 5900 -F 0 "#PWR237" H 6700 5750 50 0001 C CNN +F 0 "#PWR37" H 6700 5750 50 0001 C CNN F 1 "VFPGA33" H 6718 6074 50 0000 C CNN F 2 "" H 6700 5900 50 0000 C CNN F 3 "" H 6700 5900 50 0000 C CNN @@ -1696,19 +1620,19 @@ Wire Wire Line 7500 3000 7550 3000 Connection ~ 7500 2900 Wire Wire Line - 9800 2750 9800 3250 + 8850 2750 8850 3250 Wire Wire Line 7500 3950 7500 3500 Wire Wire Line 7500 3500 7550 3500 Wire Wire Line - 9800 3950 9800 3350 + 8850 3400 8850 3350 Wire Wire Line - 9800 3250 9850 3250 + 8850 3250 8900 3250 Wire Wire Line - 9800 3350 9850 3350 + 8850 3350 8900 3350 Wire Wire Line - 8600 3950 8600 3850 + 8600 3900 8600 3850 Wire Wire Line 8600 3550 8600 3500 Wire Wire Line @@ -1746,31 +1670,7 @@ Wire Wire Line 7250 3100 7250 3150 Connection ~ 7250 3150 Wire Wire Line - 8550 3150 8850 3150 -Wire Wire Line - 9200 2750 9200 3000 -Wire Wire Line - 8850 3550 8850 3950 -Wire Wire Line - 8850 3150 8850 2950 -Wire Wire Line - 9850 2950 9850 3150 -Wire Wire Line - 9150 3350 9200 3350 -Wire Wire Line - 9200 3750 9200 3950 -Wire Wire Line - 9500 3550 9850 3550 -Wire Wire Line - 9550 3900 9550 3950 -Wire Wire Line - 9550 3550 9550 3600 -Connection ~ 9550 3550 -Wire Wire Line - 10200 3550 10150 3550 -Wire Wire Line - 8850 2950 9850 2950 -Connection ~ 8850 3150 + 8550 3150 8900 3150 Wire Wire Line 7200 3150 7550 3150 Wire Wire Line @@ -1847,25 +1747,6 @@ Wire Wire Line 2800 1300 2950 1300 Wire Wire Line 2950 1300 2950 1050 -Wire Notes Line - 8700 3200 9050 3200 -Wire Notes Line - 9050 3200 9050 3000 -Wire Notes Line - 9050 3000 9700 3000 -Wire Notes Line - 9700 3000 9700 3450 -Wire Notes Line - 9700 3450 11050 3450 -Wire Notes Line - 11050 3450 11050 3900 -Wire Notes Line - 11050 3900 8700 3900 -Wire Notes Line - 8700 3900 8700 3200 -Connection ~ 9200 3350 -Wire Wire Line - 9200 3350 9200 3300 Wire Wire Line 1250 4300 1300 4300 Wire Wire Line @@ -2051,10 +1932,10 @@ Wire Wire Line 7650 6050 7700 6050 Connection ~ 7700 6050 $Comp -L GND #PWR244 +L GND #PWR44 U 1 1 56CA7BD2 P 7700 6100 -F 0 "#PWR244" H 7700 5850 50 0001 C CNN +F 0 "#PWR44" H 7700 5850 50 0001 C CNN F 1 "GND" H 7700 5950 50 0000 C CNN F 2 "" H 7700 6100 60 0000 C CNN F 3 "" H 7700 6100 60 0000 C CNN @@ -2101,10 +1982,10 @@ Wire Wire Line 8100 6150 8500 6150 Connection ~ 8300 6150 $Comp -L GND #PWR247 +L GND #PWR47 U 1 1 56CA9ED8 P 8300 6200 -F 0 "#PWR247" H 8300 5950 50 0001 C CNN +F 0 "#PWR47" H 8300 5950 50 0001 C CNN F 1 "GND" H 8300 6050 50 0000 C CNN F 2 "" H 8300 6200 60 0000 C CNN F 3 "" H 8300 6200 60 0000 C CNN @@ -2116,10 +1997,10 @@ Wire Wire Line Wire Wire Line 8300 5850 8300 5800 $Comp -L VFPGA33 #PWR246 +L VFPGA33 #PWR46 U 1 1 56CAA2F9 P 8300 5800 -F 0 "#PWR246" H 8300 5650 50 0001 C CNN +F 0 "#PWR46" H 8300 5650 50 0001 C CNN F 1 "VFPGA33" H 8318 5974 50 0000 C CNN F 2 "" H 8300 5800 50 0000 C CNN F 3 "" H 8300 5800 50 0000 C CNN @@ -2136,14 +2017,34 @@ NoConn ~ 7400 1450 Wire Wire Line 7050 1900 7300 1900 $Comp -L GND #PWR238 +L GND #PWR38 U 1 1 56CD8CEE P 6800 1900 -F 0 "#PWR238" H 6800 1650 50 0001 C CNN +F 0 "#PWR38" H 6800 1650 50 0001 C CNN F 1 "GND" H 6808 1726 50 0000 C CNN F 2 "" H 6800 1900 50 0000 C CNN F 3 "" H 6800 1900 50 0000 C CNN 1 6800 1900 1 0 0 -1 $EndComp +Wire Wire Line + 8600 4500 8600 4300 +Wire Wire Line + 8950 4150 8950 4100 +Wire Wire Line + 8900 4100 9100 4100 +$Comp +L GND #PWR55 +U 1 1 56CAF6AE +P 8950 4500 +F 0 "#PWR55" H 8950 4250 50 0001 C CNN +F 1 "GND" H 8950 4350 50 0000 C CNN +F 2 "" H 8950 4500 60 0000 C CNN +F 3 "" H 8950 4500 60 0000 C CNN + 1 8950 4500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8950 4500 8950 4450 +Connection ~ 8950 4100 $EndSCHEMATC diff --git a/sdcard.sch b/sdcard.sch index c3df79b..ee3f90b 100644 --- a/sdcard.sch +++ b/sdcard.sch @@ -69,10 +69,10 @@ SDIO_D0 Text Label 3400 3050 2 60 ~ 0 SDIO_D1 $Comp -L GND #PWR805 +L GND #PWR105 U 1 1 56C7E69F P 3500 4350 -F 0 "#PWR805" H 3500 4100 50 0001 C CNN +F 0 "#PWR105" H 3500 4100 50 0001 C CNN F 1 "GND" H 3508 4176 50 0000 C CNN F 2 "" H 3500 4350 50 0000 C CNN F 3 "" H 3500 4350 50 0000 C CNN @@ -80,10 +80,10 @@ F 3 "" H 3500 4350 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VSTM33 #PWR806 +L VSTM33 #PWR106 U 1 1 56C7E6CF P 3550 2500 -F 0 "#PWR806" H 3550 2350 50 0001 C CNN +F 0 "#PWR106" H 3550 2350 50 0001 C CNN F 1 "VSTM33" H 3568 2674 50 0000 C CNN F 2 "" H 3550 2500 50 0000 C CNN F 3 "" H 3550 2500 50 0000 C CNN @@ -113,10 +113,10 @@ F 3 "" H 3950 3400 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR808 +L GND #PWR108 U 1 1 56C7E8BC P 3850 4350 -F 0 "#PWR808" H 3850 4100 50 0001 C CNN +F 0 "#PWR108" H 3850 4100 50 0001 C CNN F 1 "GND" H 3858 4176 50 0000 C CNN F 2 "" H 3850 4350 50 0000 C CNN F 3 "" H 3850 4350 50 0000 C CNN @@ -124,10 +124,10 @@ F 3 "" H 3850 4350 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VSTM33 #PWR807 +L VSTM33 #PWR107 U 1 1 56C7E9D7 P 3850 2500 -F 0 "#PWR807" H 3850 2350 50 0001 C CNN +F 0 "#PWR107" H 3850 2350 50 0001 C CNN F 1 "VSTM33" H 3868 2674 50 0000 C CNN F 2 "" H 3850 2500 50 0000 C CNN F 3 "" H 3850 2500 50 0000 C CNN @@ -170,10 +170,10 @@ F 3 "" H 800 4750 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR801 +L GND #PWR101 U 1 1 56C8C9BD P 1350 4350 -F 0 "#PWR801" H 1350 4100 50 0001 C CNN +F 0 "#PWR101" H 1350 4100 50 0001 C CNN F 1 "GND" H 1358 4176 50 0000 C CNN F 2 "" H 1350 4350 50 0000 C CNN F 3 "" H 1350 4350 50 0000 C CNN @@ -251,10 +251,10 @@ Wire Wire Line Wire Wire Line 1350 2500 1350 2450 $Comp -L GND #PWR804 +L GND #PWR104 U 1 1 56C8CA7C P 2050 4350 -F 0 "#PWR804" H 2050 4100 50 0001 C CNN +F 0 "#PWR104" H 2050 4100 50 0001 C CNN F 1 "GND" H 2058 4176 50 0000 C CNN F 2 "" H 2050 4350 50 0000 C CNN F 3 "" H 2050 4350 50 0000 C CNN @@ -262,10 +262,10 @@ F 3 "" H 2050 4350 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR802 +L GND #PWR102 U 1 1 56C8CA9B P 1500 2450 -F 0 "#PWR802" H 1500 2200 50 0001 C CNN +F 0 "#PWR102" H 1500 2200 50 0001 C CNN F 1 "GND" H 1508 2276 50 0000 C CNN F 2 "" H 1500 2450 50 0000 C CNN F 3 "" H 1500 2450 50 0000 C CNN @@ -275,10 +275,10 @@ $EndComp Wire Wire Line 1350 2450 1500 2450 $Comp -L GND #PWR803 +L GND #PWR103 U 1 1 56C8CADC P 1900 2450 -F 0 "#PWR803" H 1900 2200 50 0001 C CNN +F 0 "#PWR103" H 1900 2200 50 0001 C CNN F 1 "GND" H 1908 2276 50 0000 C CNN F 2 "" H 1900 2450 50 0000 C CNN F 3 "" H 1900 2450 50 0000 C CNN diff --git a/sdram.sch b/sdram.sch index 41a3b02..4fb6f9c 100644 --- a/sdram.sch +++ b/sdram.sch @@ -192,8 +192,8 @@ U 5 1 56C7D396 P 6800 2300 AR Path="/56C43C85/56C7D396" Ref="U?" Part="5" AR Path="/56C6F777/56C7D396" Ref="U3" Part="5" -F 0 "U3" H 6800 3237 60 0000 C CNN -F 1 "LFXP2-5E-6TN144C" H 6800 3131 60 0000 C CNN +F 0 "U3" H 6800 3200 60 0000 C CNN +F 1 "LFXP2-5E-6TN144C" H 6800 3100 60 0000 C CNN F 2 "Housings_QFP:LQFP-144_20x20mm_Pitch0.5mm" H 6100 2650 60 0001 C CNN F 3 "http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/LatticeXP2/LatticeXP2FamilyDataSheet.pdf" H 5750 3550 60 0001 C CNN F 4 "1.0" H 3150 3450 60 0001 C CNN "Version" @@ -224,10 +224,10 @@ F 3 "" H 5550 4100 50 0000 C CNN -1 0 0 -1 $EndComp $Comp -L GND #PWR608 +L GND #PWR89 U 1 1 56C80525 P 6100 4400 -F 0 "#PWR608" H 6100 4150 50 0001 C CNN +F 0 "#PWR89" H 6100 4150 50 0001 C CNN F 1 "GND" H 6108 4226 50 0000 C CNN F 2 "" H 6100 4400 50 0000 C CNN F 3 "" H 6100 4400 50 0000 C CNN @@ -235,10 +235,10 @@ F 3 "" H 6100 4400 50 0000 C CNN -1 0 0 -1 $EndComp $Comp -L GND #PWR607 +L GND #PWR88 U 1 1 56C8052B P 5900 4400 -F 0 "#PWR607" H 5900 4150 50 0001 C CNN +F 0 "#PWR88" H 5900 4150 50 0001 C CNN F 1 "GND" H 5908 4226 50 0000 C CNN F 2 "" H 5900 4400 50 0000 C CNN F 3 "" H 5900 4400 50 0000 C CNN @@ -246,10 +246,10 @@ F 3 "" H 5900 4400 50 0000 C CNN -1 0 0 -1 $EndComp $Comp -L GND #PWR605 +L GND #PWR86 U 1 1 56C80531 P 5650 4400 -F 0 "#PWR605" H 5650 4150 50 0001 C CNN +F 0 "#PWR86" H 5650 4150 50 0001 C CNN F 1 "GND" H 5658 4226 50 0000 C CNN F 2 "" H 5650 4400 50 0000 C CNN F 3 "" H 5650 4400 50 0000 C CNN @@ -257,10 +257,10 @@ F 3 "" H 5650 4400 50 0000 C CNN -1 0 0 -1 $EndComp $Comp -L VFPGA33 #PWR604 +L VFPGA33 #PWR85 U 1 1 56C8053D P 5550 3850 -F 0 "#PWR604" H 5550 3700 50 0001 C CNN +F 0 "#PWR85" H 5550 3700 50 0001 C CNN F 1 "VFPGA33" H 5568 4024 50 0000 C CNN F 2 "" H 5550 3850 50 0000 C CNN F 3 "" H 5550 3850 50 0000 C CNN @@ -268,10 +268,10 @@ F 3 "" H 5550 3850 50 0000 C CNN -1 0 0 -1 $EndComp $Comp -L VFPGA33 #PWR606 +L VFPGA33 #PWR87 U 1 1 56C80543 P 5750 3750 -F 0 "#PWR606" H 5750 3600 50 0001 C CNN +F 0 "#PWR87" H 5750 3600 50 0001 C CNN F 1 "VFPGA33" H 5768 3924 50 0000 C CNN F 2 "" H 5750 3750 50 0000 C CNN F 3 "" H 5750 3750 50 0000 C CNN @@ -301,10 +301,10 @@ F 3 "" H 8150 4100 50 0000 C CNN -1 0 0 -1 $EndComp $Comp -L GND #PWR616 +L GND #PWR97 U 1 1 56C8079E P 8700 4400 -F 0 "#PWR616" H 8700 4150 50 0001 C CNN +F 0 "#PWR97" H 8700 4150 50 0001 C CNN F 1 "GND" H 8708 4226 50 0000 C CNN F 2 "" H 8700 4400 50 0000 C CNN F 3 "" H 8700 4400 50 0000 C CNN @@ -312,10 +312,10 @@ F 3 "" H 8700 4400 50 0000 C CNN -1 0 0 -1 $EndComp $Comp -L GND #PWR615 +L GND #PWR96 U 1 1 56C807A4 P 8500 4400 -F 0 "#PWR615" H 8500 4150 50 0001 C CNN +F 0 "#PWR96" H 8500 4150 50 0001 C CNN F 1 "GND" H 8508 4226 50 0000 C CNN F 2 "" H 8500 4400 50 0000 C CNN F 3 "" H 8500 4400 50 0000 C CNN @@ -323,10 +323,10 @@ F 3 "" H 8500 4400 50 0000 C CNN -1 0 0 -1 $EndComp $Comp -L GND #PWR613 +L GND #PWR94 U 1 1 56C807AA P 8250 4400 -F 0 "#PWR613" H 8250 4150 50 0001 C CNN +F 0 "#PWR94" H 8250 4150 50 0001 C CNN F 1 "GND" H 8258 4226 50 0000 C CNN F 2 "" H 8250 4400 50 0000 C CNN F 3 "" H 8250 4400 50 0000 C CNN @@ -334,10 +334,10 @@ F 3 "" H 8250 4400 50 0000 C CNN -1 0 0 -1 $EndComp $Comp -L VFPGA33 #PWR612 +L VFPGA33 #PWR93 U 1 1 56C807B6 P 8150 3850 -F 0 "#PWR612" H 8150 3700 50 0001 C CNN +F 0 "#PWR93" H 8150 3700 50 0001 C CNN F 1 "VFPGA33" H 8168 4024 50 0000 C CNN F 2 "" H 8150 3850 50 0000 C CNN F 3 "" H 8150 3850 50 0000 C CNN @@ -345,10 +345,10 @@ F 3 "" H 8150 3850 50 0000 C CNN -1 0 0 -1 $EndComp $Comp -L VFPGA33 #PWR614 +L VFPGA33 #PWR95 U 1 1 56C807BC P 8350 3750 -F 0 "#PWR614" H 8350 3600 50 0001 C CNN +F 0 "#PWR95" H 8350 3600 50 0001 C CNN F 1 "VFPGA33" H 8368 3924 50 0000 C CNN F 2 "" H 8350 3750 50 0000 C CNN F 3 "" H 8350 3750 50 0000 C CNN @@ -367,10 +367,10 @@ F 3 "" H 7700 4200 50 0000 C CNN -1 0 0 -1 $EndComp $Comp -L GND #PWR609 +L GND #PWR90 U 1 1 56C8090E P 7500 4400 -F 0 "#PWR609" H 7500 4150 50 0001 C CNN +F 0 "#PWR90" H 7500 4150 50 0001 C CNN F 1 "GND" H 7508 4226 50 0000 C CNN F 2 "" H 7500 4400 50 0000 C CNN F 3 "" H 7500 4400 50 0000 C CNN @@ -378,10 +378,10 @@ F 3 "" H 7500 4400 50 0000 C CNN -1 0 0 -1 $EndComp $Comp -L GND #PWR611 +L GND #PWR92 U 1 1 56C80914 P 7700 4400 -F 0 "#PWR611" H 7700 4150 50 0001 C CNN +F 0 "#PWR92" H 7700 4150 50 0001 C CNN F 1 "GND" H 7708 4226 50 0000 C CNN F 2 "" H 7700 4400 50 0000 C CNN F 3 "" H 7700 4400 50 0000 C CNN @@ -389,10 +389,10 @@ F 3 "" H 7700 4400 50 0000 C CNN -1 0 0 -1 $EndComp $Comp -L VFPGA33 #PWR610 +L VFPGA33 #PWR91 U 1 1 56C8091F P 7700 3750 -F 0 "#PWR610" H 7700 3600 50 0001 C CNN +F 0 "#PWR91" H 7700 3600 50 0001 C CNN F 1 "VFPGA33" H 7718 3924 50 0000 C CNN F 2 "" H 7700 3750 50 0000 C CNN F 3 "" H 7700 3750 50 0000 C CNN @@ -411,10 +411,10 @@ F 3 "" H 10300 4200 50 0000 C CNN -1 0 0 -1 $EndComp $Comp -L GND #PWR617 +L GND #PWR98 U 1 1 56C80AD8 P 10100 4400 -F 0 "#PWR617" H 10100 4150 50 0001 C CNN +F 0 "#PWR98" H 10100 4150 50 0001 C CNN F 1 "GND" H 10108 4226 50 0000 C CNN F 2 "" H 10100 4400 50 0000 C CNN F 3 "" H 10100 4400 50 0000 C CNN @@ -422,10 +422,10 @@ F 3 "" H 10100 4400 50 0000 C CNN -1 0 0 -1 $EndComp $Comp -L GND #PWR619 +L GND #PWR100 U 1 1 56C80ADE P 10300 4400 -F 0 "#PWR619" H 10300 4150 50 0001 C CNN +F 0 "#PWR100" H 10300 4150 50 0001 C CNN F 1 "GND" H 10308 4226 50 0000 C CNN F 2 "" H 10300 4400 50 0000 C CNN F 3 "" H 10300 4400 50 0000 C CNN @@ -433,10 +433,10 @@ F 3 "" H 10300 4400 50 0000 C CNN -1 0 0 -1 $EndComp $Comp -L VFPGA33 #PWR618 +L VFPGA33 #PWR99 U 1 1 56C80AE9 P 10300 3750 -F 0 "#PWR618" H 10300 3600 50 0001 C CNN +F 0 "#PWR99" H 10300 3600 50 0001 C CNN F 1 "VFPGA33" H 10318 3924 50 0000 C CNN F 2 "" H 10300 3750 50 0000 C CNN F 3 "" H 10300 3750 50 0000 C CNN @@ -833,10 +833,10 @@ F 3 "" H 2850 5400 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR603 +L GND #PWR84 U 1 1 56CA301B P 3650 5650 -F 0 "#PWR603" H 3650 5400 50 0001 C CNN +F 0 "#PWR84" H 3650 5400 50 0001 C CNN F 1 "GND" H 3650 5500 50 0000 C CNN F 2 "" H 3650 5650 60 0000 C CNN F 3 "" H 3650 5650 60 0000 C CNN @@ -844,10 +844,10 @@ F 3 "" H 3650 5650 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VFPGA33 #PWR601 +L VFPGA33 #PWR82 U 1 1 56CA3022 P 1950 5150 -F 0 "#PWR601" H 1950 5000 50 0001 C CNN +F 0 "#PWR82" H 1950 5000 50 0001 C CNN F 1 "VFPGA33" H 1968 5324 50 0000 C CNN F 2 "" H 1950 5150 50 0000 C CNN F 3 "" H 1950 5150 50 0000 C CNN @@ -878,10 +878,10 @@ F 3 "" H 1950 5450 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR602 +L GND #PWR83 U 1 1 56CA3322 P 1950 5650 -F 0 "#PWR602" H 1950 5400 50 0001 C CNN +F 0 "#PWR83" H 1950 5400 50 0001 C CNN F 1 "GND" H 1950 5500 50 0000 C CNN F 2 "" H 1950 5650 60 0000 C CNN F 3 "" H 1950 5650 60 0000 C CNN diff --git a/userif.sch b/userif.sch index 33a3aca..47cec52 100644 --- a/userif.sch +++ b/userif.sch @@ -99,10 +99,10 @@ F 3 "" H 3150 3000 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR701 +L GND #PWR117 U 1 1 56C87F68 P 3550 3200 -F 0 "#PWR701" H 3550 2950 50 0001 C CNN +F 0 "#PWR117" H 3550 2950 50 0001 C CNN F 1 "GND" H 3558 3026 50 0000 C CNN F 2 "" H 3550 3200 50 0000 C CNN F 3 "" H 3550 3200 50 0000 C CNN @@ -110,10 +110,10 @@ F 3 "" H 3550 3200 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR702 +L GND #PWR118 U 1 1 56C87F8A P 3800 3200 -F 0 "#PWR702" H 3800 2950 50 0001 C CNN +F 0 "#PWR118" H 3800 2950 50 0001 C CNN F 1 "GND" H 3808 3026 50 0000 C CNN F 2 "" H 3800 3200 50 0000 C CNN F 3 "" H 3800 3200 50 0000 C CNN @@ -121,10 +121,10 @@ F 3 "" H 3800 3200 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR703 +L GND #PWR119 U 1 1 56C87FA1 P 4050 3200 -F 0 "#PWR703" H 4050 2950 50 0001 C CNN +F 0 "#PWR119" H 4050 2950 50 0001 C CNN F 1 "GND" H 4058 3026 50 0000 C CNN F 2 "" H 4050 3200 50 0000 C CNN F 3 "" H 4050 3200 50 0000 C CNN @@ -132,10 +132,10 @@ F 3 "" H 4050 3200 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR704 +L GND #PWR120 U 1 1 56C87FE7 P 4300 3200 -F 0 "#PWR704" H 4300 2950 50 0001 C CNN +F 0 "#PWR120" H 4300 2950 50 0001 C CNN F 1 "GND" H 4308 3026 50 0000 C CNN F 2 "" H 4300 3200 50 0000 C CNN F 3 "" H 4300 3200 50 0000 C CNN @@ -225,10 +225,10 @@ F 3 "" H 6850 3000 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR705 +L GND #PWR121 U 1 1 56C88444 P 7250 3200 -F 0 "#PWR705" H 7250 2950 50 0001 C CNN +F 0 "#PWR121" H 7250 2950 50 0001 C CNN F 1 "GND" H 7258 3026 50 0000 C CNN F 2 "" H 7250 3200 50 0000 C CNN F 3 "" H 7250 3200 50 0000 C CNN @@ -236,10 +236,10 @@ F 3 "" H 7250 3200 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR706 +L GND #PWR122 U 1 1 56C8844A P 7500 3200 -F 0 "#PWR706" H 7500 2950 50 0001 C CNN +F 0 "#PWR122" H 7500 2950 50 0001 C CNN F 1 "GND" H 7508 3026 50 0000 C CNN F 2 "" H 7500 3200 50 0000 C CNN F 3 "" H 7500 3200 50 0000 C CNN @@ -247,10 +247,10 @@ F 3 "" H 7500 3200 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR707 +L GND #PWR123 U 1 1 56C88450 P 7750 3200 -F 0 "#PWR707" H 7750 2950 50 0001 C CNN +F 0 "#PWR123" H 7750 2950 50 0001 C CNN F 1 "GND" H 7758 3026 50 0000 C CNN F 2 "" H 7750 3200 50 0000 C CNN F 3 "" H 7750 3200 50 0000 C CNN @@ -258,10 +258,10 @@ F 3 "" H 7750 3200 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR708 +L GND #PWR124 U 1 1 56C88456 P 8000 3200 -F 0 "#PWR708" H 8000 2950 50 0001 C CNN +F 0 "#PWR124" H 8000 2950 50 0001 C CNN F 1 "GND" H 8008 3026 50 0000 C CNN F 2 "" H 8000 3200 50 0000 C CNN F 3 "" H 8000 3200 50 0000 C CNN @@ -401,10 +401,10 @@ Wire Wire Line 9800 2650 9850 2650 Connection ~ 9850 2650 $Comp -L GND #PWR709 +L GND #PWR125 U 1 1 56C8F2B5 P 9850 3000 -F 0 "#PWR709" H 9850 2750 50 0001 C CNN +F 0 "#PWR125" H 9850 2750 50 0001 C CNN F 1 "GND" H 9858 2826 50 0000 C CNN F 2 "" H 9850 3000 50 0000 C CNN F 3 "" H 9850 3000 50 0000 C CNN