FPGA Power

master
Markus Koch 2016-03-05 15:57:29 +01:00
parent 50759ecd91
commit bc439332a0
6 changed files with 3048 additions and 1968 deletions

View File

@ -101,7 +101,7 @@ U 1 1 56CAE8FF
P 4500 3050
F 0 "C803" H 4588 3096 50 0000 L CNN
F 1 "47u" H 4588 3004 50 0000 L CNN
F 2 "Capacitors_SMD:c_elec_4x4.5" H 4500 3050 50 0001 C CNN
F 2 "Capacitors_SMD:C_0805" H 4500 3050 50 0001 C CNN
F 3 "" H 4500 3050 50 0000 C CNN
1 4500 3050
1 0 0 -1
@ -470,4 +470,6 @@ F 3 "" H 3900 2850 50 0000 C CNN
1 3900 2850
1 0 0 -1
$EndComp
Text Label 4250 2350 0 60 ~ 0
APPSEL
$EndSCHEMATC

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1255
fpgna.net

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@ -122,7 +122,6 @@ F7 "L3MODE" O R 9450 4750 60
F8 "L3DATA" O R 9450 4650 60
F9 "ADATA" O R 9450 4550 60
F10 "ACLK" O R 9450 4450 60
F11 "OSC_EN" I L 8100 4600 60
$EndSheet
Wire Bus Line
8100 4500 7950 4500
@ -143,7 +142,6 @@ F6 "SW_A" I L 4350 3500 60
F7 "SW_D" I L 4350 3800 60
F8 "SW_C" I L 4350 3700 60
F9 "SDCARD_DETECT" O L 4350 3400 60
F10 "OSC_EN" O R 5750 3300 60
$EndSheet
Wire Wire Line
7950 3200 8100 3200
@ -256,10 +254,4 @@ Wire Wire Line
1650 4700 1650 2850
Wire Wire Line
1650 2850 1750 2850
Wire Wire Line
5750 3300 5800 3300
Wire Wire Line
5800 3300 5800 4600
Wire Wire Line
5800 4600 8100 4600
$EndSCHEMATC

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@ -308,8 +308,5 @@ Text HLabel 2950 2850 2 60 Output ~ 0
SDCARD_DETECT
Wire Wire Line
2950 2850 2900 2850
Wire Wire Line
5600 2950 5100 2950
Text HLabel 5100 2950 0 60 Output ~ 0
OSC_EN
NoConn ~ 5600 2950
$EndSCHEMATC

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@ -893,8 +893,5 @@ Wire Wire Line
Wire Wire Line
2150 5250 1950 5250
Connection ~ 1950 5250
Wire Wire Line
2150 5550 1550 5550
Text HLabel 1550 5550 0 60 Input ~ 0
OSC_EN
NoConn ~ 2150 5550
$EndSCHEMATC