FPGA Power
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parent
50759ecd91
commit
bc439332a0
@ -101,7 +101,7 @@ U 1 1 56CAE8FF
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P 4500 3050
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P 4500 3050
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F 0 "C803" H 4588 3096 50 0000 L CNN
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F 0 "C803" H 4588 3096 50 0000 L CNN
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F 1 "47u" H 4588 3004 50 0000 L CNN
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F 1 "47u" H 4588 3004 50 0000 L CNN
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F 2 "Capacitors_SMD:c_elec_4x4.5" H 4500 3050 50 0001 C CNN
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F 2 "Capacitors_SMD:C_0805" H 4500 3050 50 0001 C CNN
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F 3 "" H 4500 3050 50 0000 C CNN
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F 3 "" H 4500 3050 50 0000 C CNN
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1 4500 3050
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1 4500 3050
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1 0 0 -1
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1 0 0 -1
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@ -470,4 +470,6 @@ F 3 "" H 3900 2850 50 0000 C CNN
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1 3900 2850
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1 3900 2850
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1 0 0 -1
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1 0 0 -1
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$EndComp
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$EndComp
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Text Label 4250 2350 0 60 ~ 0
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APPSEL
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$EndSCHEMATC
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$EndSCHEMATC
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3739
fpgna.kicad_pcb
3739
fpgna.kicad_pcb
File diff suppressed because it is too large
Load Diff
@ -122,7 +122,6 @@ F7 "L3MODE" O R 9450 4750 60
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F8 "L3DATA" O R 9450 4650 60
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F8 "L3DATA" O R 9450 4650 60
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F9 "ADATA" O R 9450 4550 60
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F9 "ADATA" O R 9450 4550 60
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F10 "ACLK" O R 9450 4450 60
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F10 "ACLK" O R 9450 4450 60
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F11 "OSC_EN" I L 8100 4600 60
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$EndSheet
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$EndSheet
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Wire Bus Line
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Wire Bus Line
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8100 4500 7950 4500
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8100 4500 7950 4500
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@ -143,7 +142,6 @@ F6 "SW_A" I L 4350 3500 60
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F7 "SW_D" I L 4350 3800 60
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F7 "SW_D" I L 4350 3800 60
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F8 "SW_C" I L 4350 3700 60
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F8 "SW_C" I L 4350 3700 60
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F9 "SDCARD_DETECT" O L 4350 3400 60
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F9 "SDCARD_DETECT" O L 4350 3400 60
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F10 "OSC_EN" O R 5750 3300 60
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$EndSheet
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$EndSheet
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Wire Wire Line
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Wire Wire Line
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7950 3200 8100 3200
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7950 3200 8100 3200
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@ -256,10 +254,4 @@ Wire Wire Line
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1650 4700 1650 2850
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1650 4700 1650 2850
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Wire Wire Line
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Wire Wire Line
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1650 2850 1750 2850
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1650 2850 1750 2850
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Wire Wire Line
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5750 3300 5800 3300
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Wire Wire Line
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5800 3300 5800 4600
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Wire Wire Line
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5800 4600 8100 4600
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$EndSCHEMATC
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$EndSCHEMATC
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@ -308,8 +308,5 @@ Text HLabel 2950 2850 2 60 Output ~ 0
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SDCARD_DETECT
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SDCARD_DETECT
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Wire Wire Line
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Wire Wire Line
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2950 2850 2900 2850
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2950 2850 2900 2850
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Wire Wire Line
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NoConn ~ 5600 2950
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5600 2950 5100 2950
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Text HLabel 5100 2950 0 60 Output ~ 0
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OSC_EN
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$EndSCHEMATC
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$EndSCHEMATC
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