From f46704f400f67155a707ae1a2743a87c0a63f417 Mon Sep 17 00:00:00 2001 From: Makise Kurisu Date: Thu, 18 Feb 2016 15:59:42 +0100 Subject: [PATCH] Started wiring LCD --- FSMC.sch | 84 +-- debug.sch | 57 +- display.sch | 475 ++++++++++++ fp-lib-table | 3 + fpgna-cache.lib | 77 +- fpgna.kicad_pcb | 1866 +++++++++++++++++++++++++++-------------------- fpgna.net | 1318 ++++++++++++++++++++------------- fpgna.sch | 11 +- power.sch | 417 +++++++---- 9 files changed, 2760 insertions(+), 1548 deletions(-) create mode 100644 display.sch create mode 100644 fp-lib-table diff --git a/FSMC.sch b/FSMC.sch index a0df2ec..ab946b5 100644 --- a/FSMC.sch +++ b/FSMC.sch @@ -34,12 +34,13 @@ LIBS:pmic LIBS:specific-powersyms LIBS:regulators LIBS:stm32f4 +LIBS:itead-displays LIBS:fpgna-cache EELAYER 25 0 EELAYER END $Descr A4 11693 8268 encoding utf-8 -Sheet 4 4 +Sheet 4 5 Title "" Date "" Rev "" @@ -189,19 +190,6 @@ F 5 "Makise Kurisu " H 1850 5950 60 0001 C CNN "Author" $EndComp $Comp L LFXP2-5E-6TN144C U3 -U 3 1 56C48B2B -P 6650 2300 -F 0 "U3" H 6650 3237 60 0000 C CNN -F 1 "LFXP2-5E-6TN144C" H 6650 3131 60 0000 C CNN -F 2 "Housings_QFP:LQFP-144_20x20mm_Pitch0.5mm" H 5950 2650 60 0001 C CNN -F 3 "http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/LatticeXP2/LatticeXP2FamilyDataSheet.pdf" H 5600 3550 60 0001 C CNN -F 4 "1.0" H 3000 3450 60 0001 C CNN "Version" -F 5 "Makise Kurisu " H 3800 3350 60 0001 C CNN "Author" - 3 6650 2300 - 1 0 0 -1 -$EndComp -$Comp -L LFXP2-5E-6TN144C U3 U 4 1 56C48B85 P 4950 1450 F 0 "U3" H 4950 2387 60 0000 C CNN @@ -230,10 +218,6 @@ Text Label 5600 1050 0 60 ~ 0 B4 Text Label 4300 1550 2 60 ~ 0 B5 -Text Label 7300 2450 0 60 ~ 0 -B2 -Text Label 6000 1900 2 60 ~ 0 -B3 Text Label 8700 5150 0 60 ~ 0 B6 Text Label 7400 5350 2 60 ~ 0 @@ -244,7 +228,7 @@ U 1 1 56C675D2 P 5750 6900 F 0 "C28" H 5800 7000 50 0000 L CNN F 1 "100n" H 5800 6800 50 0000 L CNN -F 2 "" H 5788 6750 50 0000 C CNN +F 2 "" H 5788 6750 50 0001 C CNN F 3 "" H 5750 6900 50 0000 C CNN 1 5750 6900 1 0 0 -1 @@ -255,16 +239,16 @@ U 1 1 56C676A2 P 5950 6900 F 0 "C29" H 6000 7000 50 0000 L CNN F 1 "100n" H 6000 6800 50 0000 L CNN -F 2 "" H 5988 6750 50 0000 C CNN +F 2 "" H 5988 6750 50 0001 C CNN F 3 "" H 5950 6900 50 0000 C CNN 1 5950 6900 1 0 0 -1 $EndComp $Comp -L GND #PWR54 +L GND #PWR62 U 1 1 56C67B1F P 5400 7200 -F 0 "#PWR54" H 5400 6950 50 0001 C CNN +F 0 "#PWR62" H 5400 6950 50 0001 C CNN F 1 "GND" H 5408 7026 50 0000 C CNN F 2 "" H 5400 7200 50 0000 C CNN F 3 "" H 5400 7200 50 0000 C CNN @@ -272,10 +256,10 @@ F 3 "" H 5400 7200 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR55 +L GND #PWR63 U 1 1 56C67B55 P 5600 7200 -F 0 "#PWR55" H 5600 6950 50 0001 C CNN +F 0 "#PWR63" H 5600 6950 50 0001 C CNN F 1 "GND" H 5608 7026 50 0000 C CNN F 2 "" H 5600 7200 50 0000 C CNN F 3 "" H 5600 7200 50 0000 C CNN @@ -283,10 +267,10 @@ F 3 "" H 5600 7200 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR57 +L GND #PWR65 U 1 1 56C67C80 P 5850 7200 -F 0 "#PWR57" H 5850 6950 50 0001 C CNN +F 0 "#PWR65" H 5850 6950 50 0001 C CNN F 1 "GND" H 5858 7026 50 0000 C CNN F 2 "" H 5850 7200 50 0000 C CNN F 3 "" H 5850 7200 50 0000 C CNN @@ -299,16 +283,16 @@ U 1 1 56C67EC9 P 3800 7000 F 0 "C27" H 3850 7100 50 0000 L CNN F 1 "100n" H 3850 6900 50 0000 L CNN -F 2 "" H 3838 6850 50 0000 C CNN +F 2 "" H 3838 6850 50 0001 C CNN F 3 "" H 3800 7000 50 0000 C CNN 1 3800 7000 1 0 0 -1 $EndComp $Comp -L GND #PWR53 +L GND #PWR61 U 1 1 56C680A6 P 4000 7200 -F 0 "#PWR53" H 4000 6950 50 0001 C CNN +F 0 "#PWR61" H 4000 6950 50 0001 C CNN F 1 "GND" H 4008 7026 50 0000 C CNN F 2 "" H 4000 7200 50 0000 C CNN F 3 "" H 4000 7200 50 0000 C CNN @@ -316,10 +300,10 @@ F 3 "" H 4000 7200 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR52 +L GND #PWR60 U 1 1 56C6815E P 3800 7200 -F 0 "#PWR52" H 3800 6950 50 0001 C CNN +F 0 "#PWR60" H 3800 6950 50 0001 C CNN F 1 "GND" H 3808 7026 50 0000 C CNN F 2 "" H 3800 7200 50 0000 C CNN F 3 "" H 3800 7200 50 0000 C CNN @@ -424,10 +408,6 @@ Connection ~ 4300 2250 Connection ~ 4300 2350 Connection ~ 4300 2450 Connection ~ 4300 2550 -Wire Wire Line - 7300 1800 7300 3500 -Wire Wire Line - 6000 1800 6000 2100 Wire Wire Line 8700 4650 8700 5350 Wire Wire Line @@ -454,28 +434,6 @@ Connection ~ 8700 5050 Connection ~ 8700 5250 Connection ~ 8700 4850 Connection ~ 8700 4750 -Connection ~ 7300 3350 -Connection ~ 7300 3400 -Connection ~ 7300 3300 -Connection ~ 7300 3250 -Connection ~ 7300 3200 -Connection ~ 7300 3100 -Connection ~ 7300 3000 -Connection ~ 7300 2900 -Connection ~ 7300 2800 -Connection ~ 7300 2700 -Connection ~ 7300 2600 -Connection ~ 7300 2500 -Connection ~ 7300 2350 -Connection ~ 7300 2400 -Connection ~ 7300 2300 -Connection ~ 7300 2200 -Connection ~ 7300 2100 -Connection ~ 7300 1950 -Connection ~ 7300 1900 -Connection ~ 7300 2000 -Connection ~ 6000 2000 -Connection ~ 6000 1900 Wire Wire Line 5400 7200 5400 6900 Wire Wire Line @@ -600,10 +558,10 @@ A18 Text Label 5750 6300 2 60 ~ 0 A19 $Comp -L VFPGA33 #PWR58 +L VFPGA33 #PWR66 U 1 1 56C6B01D P 5950 6650 -F 0 "#PWR58" H 5950 6500 50 0001 C CNN +F 0 "#PWR66" H 5950 6500 50 0001 C CNN F 1 "VFPGA33" H 5968 6824 50 0000 C CNN F 2 "" H 5950 6650 50 0000 C CNN F 3 "" H 5950 6650 50 0000 C CNN @@ -611,10 +569,10 @@ F 3 "" H 5950 6650 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VFPGA33 #PWR56 +L VFPGA33 #PWR64 U 1 1 56C6B114 P 5750 6550 -F 0 "#PWR56" H 5750 6400 50 0001 C CNN +F 0 "#PWR64" H 5750 6400 50 0001 C CNN F 1 "VFPGA33" H 5768 6724 50 0000 C CNN F 2 "" H 5750 6550 50 0000 C CNN F 3 "" H 5750 6550 50 0000 C CNN @@ -622,10 +580,10 @@ F 3 "" H 5750 6550 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VFPGA33 #PWR51 +L VFPGA33 #PWR59 U 1 1 56C6B644 P 3800 6550 -F 0 "#PWR51" H 3800 6400 50 0001 C CNN +F 0 "#PWR59" H 3800 6400 50 0001 C CNN F 1 "VFPGA33" H 3818 6724 50 0000 C CNN F 2 "" H 3800 6550 50 0000 C CNN F 3 "" H 3800 6550 50 0000 C CNN diff --git a/debug.sch b/debug.sch index 121a82e..1c52c58 100644 --- a/debug.sch +++ b/debug.sch @@ -34,12 +34,13 @@ LIBS:pmic LIBS:specific-powersyms LIBS:regulators LIBS:stm32f4 +LIBS:itead-displays LIBS:fpgna-cache EELAYER 25 0 EELAYER END $Descr A4 11693 8268 encoding utf-8 -Sheet 3 4 +Sheet 3 5 Title "" Date "" Rev "" @@ -93,10 +94,10 @@ F 3 "" H 3750 1050 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GNDD #PWR48 +L GNDD #PWR55 U 1 1 5633954D P 3750 1300 -F 0 "#PWR48" H 3750 1050 50 0001 C CNN +F 0 "#PWR55" H 3750 1050 50 0001 C CNN F 1 "GNDD" H 3750 1150 50 0000 C CNN F 2 "" H 3750 1300 60 0000 C CNN F 3 "" H 3750 1300 60 0000 C CNN @@ -117,10 +118,10 @@ Wire Wire Line Wire Wire Line 5150 1600 4900 1600 $Comp -L GNDD #PWR50 +L GNDD #PWR58 U 1 1 568DA1F8 P 5150 1900 -F 0 "#PWR50" H 5150 1650 50 0001 C CNN +F 0 "#PWR58" H 5150 1650 50 0001 C CNN F 1 "GNDD" H 5150 1750 50 0000 C CNN F 2 "" H 5150 1900 60 0000 C CNN F 3 "" H 5150 1900 60 0000 C CNN @@ -135,12 +136,12 @@ Wire Wire Line 4900 1700 5150 1700 Connection ~ 5150 1800 $Comp -L STM32F407VGT U? +L STM32F407VGT U4 U 7 1 56C69145 P 2450 2800 -F 0 "U?" H 3028 2578 60 0000 L CNN +F 0 "U4" H 3028 2578 60 0000 L CNN F 1 "STM32F407VGT" H 3028 2472 60 0000 L CNN -F 2 "" H 1950 3300 60 0000 C CNN +F 2 "Housings_QFP:LQFP-100_14x14mm_Pitch0.5mm" H 1950 3300 60 0001 C CNN F 3 "" H 1950 3300 60 0000 C CNN 7 2450 2800 1 0 0 -1 @@ -158,10 +159,10 @@ JRST_N Text HLabel 2450 3450 2 60 Output ~ 0 BOOT1 $Comp -L VSTM33 #PWR? +L VSTM33 #PWR57 U 1 1 56C71229 P 5150 1400 -F 0 "#PWR?" H 5150 1250 50 0001 C CNN +F 0 "#PWR57" H 5150 1250 50 0001 C CNN F 1 "VSTM33" H 5168 1574 50 0000 C CNN F 2 "" H 5150 1400 50 0000 C CNN F 3 "" H 5150 1400 50 0000 C CNN @@ -169,10 +170,10 @@ F 3 "" H 5150 1400 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VSTM33 #PWR? +L VSTM33 #PWR54 U 1 1 56C71245 P 3550 800 -F 0 "#PWR?" H 3550 650 50 0001 C CNN +F 0 "#PWR54" H 3550 650 50 0001 C CNN F 1 "VSTM33" H 3568 974 50 0000 C CNN F 2 "" H 3550 800 50 0000 C CNN F 3 "" H 3550 800 50 0000 C CNN @@ -180,12 +181,12 @@ F 3 "" H 3550 800 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L Crystal_Small Y? +L Crystal_Small Y1 U 1 1 56C71642 P 1950 2900 -F 0 "Y?" V 1904 2988 50 0000 L CNN +F 0 "Y1" V 1904 2988 50 0000 L CNN F 1 "8M" V 1996 2988 50 0000 L CNN -F 2 "" H 1950 2900 50 0000 C CNN +F 2 "" H 1950 2900 50 0001 C CNN F 3 "" H 1950 2900 50 0000 C CNN 1 1950 2900 0 1 1 0 @@ -199,23 +200,23 @@ Wire Wire Line Wire Wire Line 2200 2900 2250 2900 $Comp -L C_Small C? +L C_Small C40 U 1 1 56C717BF P 1800 2800 -F 0 "C?" V 1650 2800 50 0000 C CNN +F 0 "C40" V 1650 2800 50 0000 C CNN F 1 "5p" V 1700 2800 50 0000 C CNN -F 2 "" H 1800 2800 50 0000 C CNN +F 2 "" H 1800 2800 50 0001 C CNN F 3 "" H 1800 2800 50 0000 C CNN 1 1800 2800 0 1 1 0 $EndComp $Comp -L C_Small C? +L C_Small C41 U 1 1 56C7180C P 1800 3000 -F 0 "C?" V 1900 3000 50 0000 C CNN +F 0 "C41" V 1900 3000 50 0000 C CNN F 1 "5p" V 1700 3000 50 0000 C CNN -F 2 "" H 1800 3000 50 0000 C CNN +F 2 "" H 1800 3000 50 0001 C CNN F 3 "" H 1800 3000 50 0000 C CNN 1 1800 3000 0 1 1 0 @@ -230,10 +231,10 @@ Wire Wire Line 1600 2900 1600 3550 Connection ~ 1700 2900 $Comp -L GND #PWR? +L GND #PWR53 U 1 1 56C718AB P 1600 3550 -F 0 "#PWR?" H 1600 3300 50 0001 C CNN +F 0 "#PWR53" H 1600 3300 50 0001 C CNN F 1 "GND" H 1608 3376 50 0000 C CNN F 2 "" H 1600 3550 50 0000 C CNN F 3 "" H 1600 3550 50 0000 C CNN @@ -241,12 +242,12 @@ F 3 "" H 1600 3550 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L CONN_01X06 P? +L CONN_01X06 P4 U 1 1 56C73EAE P 5250 2850 -F 0 "P?" H 5327 2888 50 0000 L CNN +F 0 "P4" H 5327 2888 50 0000 L CNN F 1 "JTAG-STM" H 5327 2796 50 0000 L CNN -F 2 "" H 5250 2850 50 0000 C CNN +F 2 "" H 5250 2850 50 0001 C CNN F 3 "" H 5250 2850 50 0000 C CNN 1 5250 2850 1 0 0 -1 @@ -262,10 +263,10 @@ Wire Wire Line Wire Wire Line 4850 3000 5050 3000 $Comp -L GND #PWR? +L GND #PWR56 U 1 1 56C74066 P 5000 3150 -F 0 "#PWR?" H 5000 2900 50 0001 C CNN +F 0 "#PWR56" H 5000 2900 50 0001 C CNN F 1 "GND" H 5008 2976 50 0000 C CNN F 2 "" H 5000 3150 50 0000 C CNN F 3 "" H 5000 3150 50 0000 C CNN diff --git a/display.sch b/display.sch new file mode 100644 index 0000000..2c02e05 --- /dev/null +++ b/display.sch @@ -0,0 +1,475 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:Oscillators +LIBS:lattice +LIBS:pmic +LIBS:specific-powersyms +LIBS:regulators +LIBS:stm32f4 +LIBS:itead-displays +LIBS:fpgna-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 5 5 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L ITDB02-3.2WD U6 +U 2 1 56C57B15 +P 2550 2250 +F 0 "U6" H 2825 2437 60 0000 C CNN +F 1 "ITDB02-3.2WD" H 2825 2331 60 0000 C CNN +F 2 "itead-display:ITDB02-3.2WD" H 2550 2250 60 0001 C CNN +F 3 "" H 2550 2250 60 0000 C CNN + 2 2550 2250 + 1 0 0 -1 +$EndComp +$Comp +L ITDB02-3.2WD U6 +U 3 1 56C57B5E +P 5200 2600 +F 0 "U6" H 5778 2303 60 0000 L CNN +F 1 "ITDB02-3.2WD" H 5778 2197 60 0000 L CNN +F 2 "itead-display:ITDB02-3.2WD" H 5200 2600 60 0001 C CNN +F 3 "" H 5200 2600 60 0000 C CNN + 3 5200 2600 + 1 0 0 -1 +$EndComp +$Comp +L ITDB02-3.2WD U6 +U 5 1 56C6C241 +P 5200 3400 +F 0 "U6" H 5778 3103 60 0000 L CNN +F 1 "ITDB02-3.2WD" H 5778 2997 60 0000 L CNN +F 2 "itead-display:ITDB02-3.2WD" H 5200 3400 60 0001 C CNN +F 3 "" H 5200 3400 60 0000 C CNN + 5 5200 3400 + 1 0 0 -1 +$EndComp +$Comp +L ITDB02-3.2WD U6 +U 4 1 56C6C295 +P 5200 2000 +F 0 "U6" H 5778 1803 60 0000 L CNN +F 1 "ITDB02-3.2WD" H 5778 1697 60 0000 L CNN +F 2 "itead-display:ITDB02-3.2WD" H 5200 2000 60 0001 C CNN +F 3 "" H 5200 2000 60 0000 C CNN + 4 5200 2000 + 1 0 0 -1 +$EndComp +Text Label 2050 2350 0 60 ~ 0 +DB0 +Text Label 2050 2450 0 60 ~ 0 +DB1 +Text Label 2050 2550 0 60 ~ 0 +DB2 +Text Label 2050 2650 0 60 ~ 0 +DB3 +Text Label 2050 2750 0 60 ~ 0 +DB4 +Text Label 2050 2850 0 60 ~ 0 +DB5 +Text Label 2050 2950 0 60 ~ 0 +DB6 +Text Label 2050 3050 0 60 ~ 0 +DB7 +Text Label 2050 3150 0 60 ~ 0 +DB8 +Text Label 2050 3250 0 60 ~ 0 +DB9 +Text Label 2050 3350 0 60 ~ 0 +DB10 +Text Label 2050 3450 0 60 ~ 0 +DB11 +Text Label 2050 3550 0 60 ~ 0 +DB12 +Text Label 2050 3650 0 60 ~ 0 +DB13 +Text Label 2050 3750 0 60 ~ 0 +DB14 +Text Label 2050 3850 0 60 ~ 0 +DB15 +Wire Wire Line + 2350 2350 2050 2350 +Wire Wire Line + 2350 2450 2050 2450 +Wire Wire Line + 2350 2550 2050 2550 +Wire Wire Line + 2350 2650 2050 2650 +Wire Wire Line + 2350 2750 2050 2750 +Wire Wire Line + 2350 2850 2050 2850 +Wire Wire Line + 2350 2950 2050 2950 +Wire Wire Line + 2350 3050 2050 3050 +Wire Wire Line + 2350 3150 2050 3150 +Wire Wire Line + 2350 3250 2050 3250 +Wire Wire Line + 2350 3350 2050 3350 +Wire Wire Line + 2350 3450 2050 3450 +Wire Wire Line + 2350 3550 2050 3550 +Wire Wire Line + 2350 3650 2050 3650 +Wire Wire Line + 2350 3750 2050 3750 +Wire Wire Line + 2350 3850 2050 3850 +Wire Wire Line + 3300 2350 3600 2350 +Wire Wire Line + 3300 2450 3600 2450 +Wire Wire Line + 3300 2550 3600 2550 +Wire Wire Line + 3300 2650 3600 2650 +Wire Wire Line + 3300 2750 3600 2750 +Text Label 3600 2350 2 60 ~ 0 +RST +Text Label 3600 2450 2 60 ~ 0 +CS +Text Label 3600 2550 2 60 ~ 0 +RS +Text Label 3600 2650 2 60 ~ 0 +WR +Text Label 3600 2750 2 60 ~ 0 +RD +$Comp +L LFXP2-5E-6TN144C U? +U 3 1 56C5FD8D +P 2000 5350 +AR Path="/56C43C85/56C5FD8D" Ref="U?" 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0000 C CNN +F 2 "" H 3150 7450 50 0000 C CNN +F 3 "" H 3150 7450 50 0000 C CNN + 1 3150 7450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2700 7450 2700 7150 +Wire Wire Line + 2700 7150 2650 7150 +Wire Wire Line + 2650 7050 2900 7050 +Wire Wire Line + 2900 7050 2900 7450 +Wire Wire Line + 3150 7450 3150 7300 +Connection ~ 3150 7300 +$Comp +L VFPGA33 #PWR73 +U 1 1 56C62B84 +P 3250 6900 +F 0 "#PWR73" H 3250 6750 50 0001 C CNN +F 1 "VFPGA33" H 3268 7074 50 0000 C CNN +F 2 "" H 3250 6900 50 0000 C CNN +F 3 "" H 3250 6900 50 0000 C CNN + 1 3250 6900 + 1 0 0 -1 +$EndComp +$Comp +L VFPGA33 #PWR71 +U 1 1 56C62B8A +P 3050 6800 +F 0 "#PWR71" H 3050 6650 50 0001 C CNN +F 1 "VFPGA33" H 3068 6974 50 0000 C CNN +F 2 "" H 3050 6800 50 0000 C CNN +F 3 "" H 3050 6800 50 0000 C CNN + 1 3050 6800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3250 6900 3250 7000 +Connection ~ 3250 6950 +Wire Wire Line + 3050 7300 3250 7300 +Wire Wire Line + 3050 6800 3050 7000 +Wire Wire Line + 3250 6950 2650 6950 +Wire Wire Line + 2650 6850 3050 6850 +Connection ~ 3050 6850 +$Comp +L C C43 +U 1 1 56C62CBE +P 1150 7200 +F 0 "C43" H 1200 7300 50 0000 L CNN +F 1 "100n" H 1200 7100 50 0000 L CNN +F 2 "" H 1188 7050 50 0001 C CNN +F 3 "" H 1150 7200 50 0000 C CNN + 1 1150 7200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1150 7050 1350 7050 +$Comp +L VFPGA33 #PWR67 +U 1 1 56C62DAA +P 1150 7000 +F 0 "#PWR67" H 1150 6850 50 0001 C CNN +F 1 "VFPGA33" H 1168 7174 50 0000 C CNN +F 2 "" H 1150 7000 50 0000 C CNN +F 3 "" H 1150 7000 50 0000 C CNN + 1 1150 7000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1150 7000 1150 7050 +Wire Wire Line + 1150 7350 1150 7400 +Wire Wire Line + 1150 7400 1350 7400 +Wire Wire Line + 1350 7400 1350 7150 +Wire Wire Line + 1250 7400 1250 7450 +Connection ~ 1250 7400 +$Comp +L GND #PWR68 +U 1 1 56C62F03 +P 1250 7450 +F 0 "#PWR68" H 1250 7200 50 0001 C CNN +F 1 "GND" H 1258 7276 50 0000 C CNN +F 2 "" H 1250 7450 50 0000 C CNN +F 3 "" H 1250 7450 50 0000 C CNN + 1 1250 7450 + 1 0 0 -1 +$EndComp +Connection ~ 1150 7050 +$EndSCHEMATC diff --git a/fp-lib-table b/fp-lib-table new file mode 100644 index 0000000..1c1cd59 --- /dev/null +++ b/fp-lib-table @@ -0,0 +1,3 @@ +(fp_lib_table + (lib (name itead-display)(type KiCad)(uri /home/kurisu/projects/kicad/ShimattaPCBLibs/footprints/pretty/itead-display.pretty)(options "")(descr "")) +) diff --git a/fpgna-cache.lib b/fpgna-cache.lib index c4a469d..e8ca89e 100644 --- a/fpgna-cache.lib +++ b/fpgna-cache.lib @@ -16,22 +16,6 @@ X +1V2 1 0 0 0 U 50 50 1 1 W N ENDDRAW ENDDEF # -# +3V3 -# -DEF +3V3 #PWR 0 0 Y Y 1 F P -F0 "#PWR" 0 -150 50 H I C CNN -F1 "+3V3" 0 140 50 H V C CNN -F2 "" 0 0 50 H V C CNN -F3 "" 0 0 50 H V C CNN -ALIAS +3.3V -DRAW -P 2 0 1 0 -30 50 0 100 N -P 2 0 1 0 0 0 0 100 N -P 2 0 1 0 0 100 30 50 N -X +3V3 1 0 0 0 U 50 50 1 1 W N -ENDDRAW -ENDDEF -# # C # DEF C C 0 10 N Y 1 F N @@ -244,6 +228,67 @@ X 2 2 0 -300 100 U 50 50 1 1 P ENDDRAW ENDDEF # +# ITDB02-3.2WD +# +DEF ITDB02-3.2WD U 0 40 Y Y 5 L N +F0 "U" 750 50 60 H V C CNN +F1 "ITDB02-3.2WD" 300 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 400 -250 60 0 1 0 PWR Normal 0 C C +T 900 300 -800 60 0 2 0 HX8352-A Normal 0 C C +T 900 450 -350 60 0 3 0 TSC2046 Normal 0 C C +S 0 0 550 -700 3 0 0 f +T 900 450 -250 60 0 4 0 SD-Card Normal 0 C C +S 0 0 550 -500 4 0 0 f +T 900 450 -350 60 0 5 0 Ununsed~pins Normal 0 C C +S 0 0 550 -700 5 0 0 f +S 0 0 550 -350 1 1 0 f +X GND 1 750 -100 200 L 50 50 1 1 W +X VCC 3 -200 -100 200 R 50 50 1 1 W +X LED+ 37 -200 -250 200 R 50 50 1 1 W +S 0 0 550 -1700 2 1 0 f +X DB0 2 -200 -100 200 R 50 50 2 1 B +X DB1 4 -200 -200 200 R 50 50 2 1 B +X DB2 6 -200 -300 200 R 50 50 2 1 B +X RS 7 750 -300 200 L 50 50 2 1 I +X DB3 8 -200 -400 200 R 50 50 2 1 B +X WR 9 750 -400 200 L 50 50 2 1 I +X DB4 10 -200 -500 200 R 50 50 2 1 B +X RD 11 750 -500 200 L 50 50 2 1 I +X DB12 21 -200 -1300 200 R 50 50 2 1 B +X DB5 12 -200 -600 200 R 50 50 2 1 B +X DB8 13 -200 -900 200 R 50 50 2 1 B +X DB13 23 -200 -1400 200 R 50 50 2 1 B +X RST 33 750 -100 200 L 50 50 2 1 I +X DB6 14 -200 -700 200 R 50 50 2 1 B +X DB9 15 -200 -1000 200 R 50 50 2 1 B +X DB14 25 -200 -1500 200 R 50 50 2 1 B +X DB7 16 -200 -800 200 R 50 50 2 1 B +X DB10 17 -200 -1100 200 R 50 50 2 1 B +X DB15 27 -200 -1600 200 R 50 50 2 1 B +X DB11 19 -200 -1200 200 R 50 50 2 1 B +X CS 29 750 -200 200 L 50 50 2 1 I +X T_CS 20 -200 -200 200 R 50 50 3 1 I +X T_DIN 22 -200 -300 200 R 50 50 3 1 I +X T_BUSY 24 -200 -500 200 R 50 50 3 1 I +X T_DOUT 26 -200 -400 200 R 50 50 3 1 O +X T_CLK 18 -200 -100 200 R 50 50 3 1 I C +X T_IRQ 28 -200 -600 200 R 50 50 3 1 O +X SD_SO 30 -200 -200 200 R 50 50 4 1 O +X SD_SCK 32 -200 -100 200 R 50 50 4 1 O C +X SD_SI 34 -200 -300 200 R 50 50 4 1 I +X SD_NSS 36 -200 -400 200 R 50 50 4 1 I +X NC5 5 -200 -100 200 R 50 50 5 1 B +X NC40 40 -200 -600 200 R 50 50 5 1 B +X NC31 31 -200 -200 200 R 50 50 5 1 B +X NC35 35 -200 -300 200 R 50 50 5 1 B +X NC38 38 -200 -400 200 R 50 50 5 1 I +X NC39 39 -200 -500 200 R 50 50 5 1 B +ENDDRAW +ENDDEF +# # LD1117S33TR # DEF LD1117S33TR U 0 30 Y Y 1 F N diff --git a/fpgna.kicad_pcb b/fpgna.kicad_pcb index 8661ac3..f06e75f 100644 --- a/fpgna.kicad_pcb +++ b/fpgna.kicad_pcb @@ -1,15 +1,15 @@ (kicad_pcb (version 4) (host pcbnew "(2016-02-12 BZR 6554)-stable") (general - (links 124) - (no_connects 99) + (links 134) + (no_connects 98) (area 0 0 0 0) (thickness 1.6) (drawings 0) - (tracks 193) + (tracks 249) (zones 0) - (modules 3) - (nets 124) + (modules 4) + (nets 154) ) (page A4) @@ -99,120 +99,150 @@ (net 7 "Net-(U3-Pad4)") (net 8 "Net-(U3-Pad12)") (net 9 "Net-(U3-Pad14)") - (net 10 +3V3) - (net 11 +1V2) - (net 12 "Net-(R2-Pad2)") - (net 13 "Net-(R3-Pad2)") - (net 14 "Net-(U3-Pad33)") - (net 15 "Net-(U3-Pad34)") - (net 16 "Net-(U3-Pad41)") - (net 17 "Net-(U3-Pad42)") - (net 18 "Net-(U3-Pad49)") - (net 19 "Net-(U3-Pad51)") - (net 20 "Net-(U3-Pad63)") - (net 21 "Net-(U3-Pad64)") - (net 22 "Net-(U3-Pad75)") - (net 23 "Net-(U3-Pad76)") - (net 24 "Net-(P3-Pad3)") - (net 25 "Net-(P3-Pad5)") - (net 26 "Net-(P3-Pad1)") - (net 27 "Net-(P3-Pad7)") - (net 28 "Net-(U3-Pad95)") - (net 29 "Net-(U3-Pad97)") - (net 30 "Net-(U3-Pad105)") - (net 31 "Net-(U3-Pad106)") - (net 32 /FSMC/A23) - (net 33 /FSMC/A19) - (net 34 /FSMC/A20) - (net 35 /FSMC/A21) - (net 36 /FSMC/A22) - (net 37 "Net-(U4-Pad7)") - (net 38 "Net-(U4-Pad8)") - (net 39 "Net-(U4-Pad9)") - (net 40 "Net-(U4-Pad12)") - (net 41 "Net-(U4-Pad13)") - (net 42 "Net-(U4-Pad14)") - (net 43 "Net-(U4-Pad15)") - (net 44 "Net-(U4-Pad16)") - (net 45 "Net-(U4-Pad17)") - (net 46 "Net-(U4-Pad18)") - (net 47 "Net-(U4-Pad23)") - (net 48 "Net-(U4-Pad24)") - (net 49 "Net-(U4-Pad25)") - (net 50 "Net-(U4-Pad26)") - (net 51 "Net-(U4-Pad29)") - (net 52 "Net-(U4-Pad30)") - (net 53 "Net-(U4-Pad31)") - (net 54 "Net-(U4-Pad32)") - (net 55 "Net-(U4-Pad33)") - (net 56 "Net-(U4-Pad34)") - (net 57 "Net-(U4-Pad35)") - (net 58 "Net-(U4-Pad36)") - (net 59 /FSMC/BOOT1) - (net 60 /FSMC/DA4) - (net 61 /FSMC/DA5) - (net 62 /FSMC/DA6) - (net 63 /FSMC/DA7) - (net 64 /FSMC/DA8) - (net 65 /FSMC/DA9) - (net 66 /FSMC/DA10) - (net 67 /FSMC/DA11) - (net 68 /FSMC/DA12) - (net 69 "Net-(U4-Pad47)") - (net 70 "Net-(U4-Pad48)") - (net 71 "Net-(U4-Pad51)") - (net 72 "Net-(U4-Pad52)") - (net 73 "Net-(U4-Pad53)") - (net 74 "Net-(U4-Pad54)") - (net 75 /FSMC/DA14) - (net 76 /FSMC/DA15) - (net 77 /FSMC/A16) - (net 78 /FSMC/A17) - (net 79 /FSMC/A18) - (net 80 /FSMC/DA0) - (net 81 /FSMC/DA1) - (net 82 "Net-(U4-Pad63)") - (net 83 "Net-(U4-Pad64)") - (net 84 "Net-(U4-Pad65)") - (net 85 "Net-(U4-Pad66)") - (net 86 "Net-(U4-Pad67)") - (net 87 "Net-(U4-Pad68)") - (net 88 "Net-(U4-Pad69)") - (net 89 "Net-(U4-Pad70)") - (net 90 "Net-(U4-Pad71)") - (net 91 "Net-(U4-Pad72)") - (net 92 "Net-(U4-Pad76)") - (net 93 "Net-(U4-Pad77)") - (net 94 "Net-(U4-Pad78)") - (net 95 "Net-(U4-Pad79)") - (net 96 "Net-(U4-Pad80)") - (net 97 /FSMC/DA2) - (net 98 /FSMC/DA3) - (net 99 "Net-(U4-Pad83)") - (net 100 /FSMC/CLK) - (net 101 /FSMC/OE_N) - (net 102 /FSMC/WE_N) - (net 103 /FSMC/WAIT_N) - (net 104 /FSMC/JTDO) - (net 105 /FSMC/JRST_N) - (net 106 "Net-(U4-Pad91)") - (net 107 "Net-(U4-Pad92)") - (net 108 /FSMC/ADV_N) - (net 109 "Net-(U4-Pad94)") - (net 110 "Net-(U4-Pad95)") - (net 111 "Net-(U4-Pad96)") - (net 112 /FSMC/BL0_N) - (net 113 /FSMC/BL1_N) - (net 114 /FSMC/B7) - (net 115 /FSMC/B6) - (net 116 /FSMC/B5) - (net 117 /FSMC/B4) - (net 118 /FSMC/B3) - (net 119 /FSMC/B2) - (net 120 VSTM33) - (net 121 GND) - (net 122 /powersupply/VCAP1) - (net 123 /powersupply/VCAP2) + (net 10 +1V2) + (net 11 "Net-(R2-Pad2)") + (net 12 "Net-(R3-Pad2)") + (net 13 "Net-(U3-Pad33)") + (net 14 "Net-(U3-Pad34)") + (net 15 "Net-(U3-Pad41)") + (net 16 "Net-(U3-Pad42)") + (net 17 "Net-(U3-Pad49)") + (net 18 "Net-(U3-Pad51)") + (net 19 "Net-(U3-Pad63)") + (net 20 "Net-(U3-Pad64)") + (net 21 "Net-(P3-Pad3)") + (net 22 "Net-(P3-Pad5)") + (net 23 "Net-(P3-Pad1)") + (net 24 "Net-(P3-Pad7)") + (net 25 /FSMC/A23) + (net 26 /FSMC/A19) + (net 27 /FSMC/A20) + (net 28 /FSMC/A21) + (net 29 /FSMC/A22) + (net 30 "Net-(U4-Pad7)") + (net 31 "Net-(U4-Pad8)") + (net 32 "Net-(U4-Pad9)") + (net 33 "Net-(U4-Pad14)") + (net 34 "Net-(U4-Pad15)") + (net 35 "Net-(U4-Pad16)") + (net 36 "Net-(U4-Pad17)") + (net 37 "Net-(U4-Pad18)") + (net 38 "Net-(U4-Pad23)") + (net 39 "Net-(U4-Pad24)") + (net 40 "Net-(U4-Pad25)") + (net 41 "Net-(U4-Pad26)") + (net 42 "Net-(U4-Pad29)") + (net 43 "Net-(U4-Pad30)") + (net 44 "Net-(U4-Pad31)") + (net 45 "Net-(U4-Pad32)") + (net 46 "Net-(U4-Pad33)") + (net 47 "Net-(U4-Pad34)") + (net 48 "Net-(U4-Pad35)") + (net 49 "Net-(U4-Pad36)") + (net 50 /FSMC/BOOT1) + (net 51 /FSMC/DA4) + (net 52 /FSMC/DA5) + (net 53 /FSMC/DA6) + (net 54 /FSMC/DA7) + (net 55 /FSMC/DA8) + (net 56 /FSMC/DA9) + (net 57 /FSMC/DA10) + (net 58 /FSMC/DA11) + (net 59 /FSMC/DA12) + (net 60 "Net-(U4-Pad47)") + (net 61 "Net-(U4-Pad48)") + (net 62 "Net-(U4-Pad51)") + (net 63 "Net-(U4-Pad52)") + (net 64 "Net-(U4-Pad53)") + (net 65 "Net-(U4-Pad54)") + (net 66 /FSMC/DA14) + (net 67 /FSMC/DA15) + (net 68 /FSMC/A16) + (net 69 /FSMC/A17) + (net 70 /FSMC/A18) + (net 71 /FSMC/DA0) + (net 72 /FSMC/DA1) + (net 73 "Net-(U4-Pad63)") + (net 74 "Net-(U4-Pad64)") + (net 75 "Net-(U4-Pad65)") + (net 76 "Net-(U4-Pad66)") + (net 77 "Net-(U4-Pad67)") + (net 78 "Net-(U4-Pad68)") + (net 79 "Net-(U4-Pad69)") + (net 80 "Net-(U4-Pad70)") + (net 81 "Net-(U4-Pad71)") + (net 82 "Net-(U4-Pad72)") + (net 83 "Net-(U4-Pad76)") + (net 84 "Net-(U4-Pad77)") + (net 85 "Net-(U4-Pad78)") + (net 86 "Net-(U4-Pad79)") + (net 87 "Net-(U4-Pad80)") + (net 88 /FSMC/DA2) + (net 89 /FSMC/DA3) + (net 90 "Net-(U4-Pad83)") + (net 91 /FSMC/CLK) + (net 92 /FSMC/OE_N) + (net 93 /FSMC/WE_N) + (net 94 /FSMC/WAIT_N) + (net 95 /FSMC/JTDO) + (net 96 /FSMC/JRST_N) + (net 97 "Net-(U4-Pad91)") + (net 98 "Net-(U4-Pad92)") + (net 99 /FSMC/ADV_N) + (net 100 "Net-(U4-Pad94)") + (net 101 "Net-(U4-Pad95)") + (net 102 "Net-(U4-Pad96)") + (net 103 /FSMC/BL0_N) + (net 104 /FSMC/BL1_N) + (net 105 /FSMC/B7) + (net 106 /FSMC/B6) + (net 107 /FSMC/B5) + (net 108 /FSMC/B4) + (net 109 VSTM33) + (net 110 GND) + (net 111 /powersupply/VCAP1) + (net 112 /powersupply/VCAP2) + (net 113 "Net-(C40-Pad1)") + (net 114 "Net-(C41-Pad1)") + (net 115 "Net-(U6-Pad5)") + (net 116 "Net-(U6-Pad31)") + (net 117 "Net-(U6-Pad35)") + (net 118 "Net-(R14-Pad1)") + (net 119 "Net-(U6-Pad38)") + (net 120 "Net-(U6-Pad39)") + (net 121 "Net-(U6-Pad40)") + (net 122 /display/DB0) + (net 123 /display/DB1) + (net 124 /display/DB2) + (net 125 /display/RS) + (net 126 /display/DB3) + (net 127 /display/WR) + (net 128 /display/DB4) + (net 129 /display/RD) + (net 130 /display/DB5) + (net 131 /display/DB8) + (net 132 /display/DB6) + (net 133 /display/DB9) + (net 134 /display/DB7) + (net 135 /display/DB10) + (net 136 /display/DB11) + (net 137 /display/DB12) + (net 138 /display/DB13) + (net 139 /display/DB14) + (net 140 /display/DB15) + (net 141 /display/CS) + (net 142 /display/RST) + (net 143 "Net-(U3-Pad73)") + (net 144 /display/T_CLK) + (net 145 /display/T_CS) + (net 146 /display/T_DIN) + (net 147 /display/T_BUSY) + (net 148 /display/T_DOUT) + (net 149 /display/T_IRQ) + (net 150 /display/SD_SO) + (net 151 /display/SD_SCK) + (net 152 /display/SD_SI) + (net 153 /display/SD_NSS) (net_class Default "This is the default net class." (clearance 0.153) @@ -222,7 +252,6 @@ (uvia_dia 0.3) (uvia_drill 0.1) (add_net +1V2) - (add_net +3V3) (add_net /FSMC/A16) (add_net /FSMC/A17) (add_net /FSMC/A18) @@ -232,8 +261,6 @@ (add_net /FSMC/A22) (add_net /FSMC/A23) (add_net /FSMC/ADV_N) - (add_net /FSMC/B2) - (add_net /FSMC/B3) (add_net /FSMC/B4) (add_net /FSMC/B5) (add_net /FSMC/B6) @@ -264,19 +291,51 @@ (add_net /FSMC/OE_N) (add_net /FSMC/WAIT_N) (add_net /FSMC/WE_N) + (add_net /display/CS) + (add_net /display/DB0) + (add_net /display/DB1) + (add_net /display/DB10) + (add_net /display/DB11) + (add_net /display/DB12) + (add_net /display/DB13) + (add_net /display/DB14) + (add_net /display/DB15) + (add_net /display/DB2) + (add_net /display/DB3) + (add_net /display/DB4) + (add_net /display/DB5) + (add_net /display/DB6) + (add_net /display/DB7) + (add_net /display/DB8) + (add_net /display/DB9) + (add_net /display/RD) + (add_net /display/RS) + (add_net /display/RST) + (add_net /display/SD_NSS) + (add_net /display/SD_SCK) + (add_net /display/SD_SI) + (add_net /display/SD_SO) + (add_net /display/T_BUSY) + (add_net /display/T_CLK) + (add_net /display/T_CS) + (add_net /display/T_DIN) + (add_net /display/T_DOUT) + (add_net /display/T_IRQ) + (add_net /display/WR) (add_net /powersupply/VCAP1) (add_net /powersupply/VCAP2) (add_net GND) (add_net GNDD) (add_net "Net-(C4-Pad1)") + (add_net "Net-(C40-Pad1)") + (add_net "Net-(C41-Pad1)") (add_net "Net-(P3-Pad1)") (add_net "Net-(P3-Pad3)") (add_net "Net-(P3-Pad5)") (add_net "Net-(P3-Pad7)") + (add_net "Net-(R14-Pad1)") (add_net "Net-(R2-Pad2)") (add_net "Net-(R3-Pad2)") - (add_net "Net-(U3-Pad105)") - (add_net "Net-(U3-Pad106)") (add_net "Net-(U3-Pad12)") (add_net "Net-(U3-Pad14)") (add_net "Net-(U3-Pad3)") @@ -289,12 +348,7 @@ (add_net "Net-(U3-Pad51)") (add_net "Net-(U3-Pad63)") (add_net "Net-(U3-Pad64)") - (add_net "Net-(U3-Pad75)") - (add_net "Net-(U3-Pad76)") - (add_net "Net-(U3-Pad95)") - (add_net "Net-(U3-Pad97)") - (add_net "Net-(U4-Pad12)") - (add_net "Net-(U4-Pad13)") + (add_net "Net-(U3-Pad73)") (add_net "Net-(U4-Pad14)") (add_net "Net-(U4-Pad15)") (add_net "Net-(U4-Pad16)") @@ -342,20 +396,26 @@ (add_net "Net-(U4-Pad94)") (add_net "Net-(U4-Pad95)") (add_net "Net-(U4-Pad96)") + (add_net "Net-(U6-Pad31)") + (add_net "Net-(U6-Pad35)") + (add_net "Net-(U6-Pad38)") + (add_net "Net-(U6-Pad39)") + (add_net "Net-(U6-Pad40)") + (add_net "Net-(U6-Pad5)") (add_net VFPGA33) (add_net VSTM33) ) (module Housings_QFP:LQFP-100_14x14mm_Pitch0.5mm (layer F.Cu) (tedit 54130A77) (tstamp 56C4508F) - (at 162.3 66.104 270) + (at 77.793728 84.329542 180) (descr "LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm (see NXP sot407-1_po.pdf and sot407-1_fr.pdf)") (tags "QFP 0.5") (path /563244F7/56C476C3) (attr smd) - (fp_text reference U4 (at 0 -9.65 270) (layer F.SilkS) + (fp_text reference U4 (at 0 -9.65 180) (layer F.SilkS) (effects (font (size 1 1) (thickness 0.15))) ) - (fp_text value STM32F407VGT (at 0 9.65 270) (layer F.Fab) + (fp_text value STM32F407VGT (at 0 9.65 180) (layer F.Fab) (effects (font (size 1 1) (thickness 0.15))) ) (fp_line (start -8.9 -8.9) (end -8.9 8.9) (layer F.CrtYd) (width 0.05)) @@ -371,206 +431,206 @@ (fp_line (start 7.125 7.125) (end 6.365 7.125) (layer F.SilkS) (width 0.15)) (fp_line (start 7.125 -7.125) (end 6.365 -7.125) (layer F.SilkS) (width 0.15)) (fp_line (start -7.125 -6.365) (end -8.65 -6.365) (layer F.SilkS) (width 0.15)) - (pad 1 smd rect (at -7.9 -6 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 32 /FSMC/A23)) - (pad 2 smd rect (at -7.9 -5.5 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 33 /FSMC/A19)) - (pad 3 smd rect (at -7.9 -5 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 34 /FSMC/A20)) - (pad 4 smd rect (at -7.9 -4.5 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 35 /FSMC/A21)) - (pad 5 smd rect (at -7.9 -4 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 36 /FSMC/A22)) - (pad 6 smd rect (at -7.9 -3.5 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 120 VSTM33)) - (pad 7 smd rect (at -7.9 -3 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 37 "Net-(U4-Pad7)")) - (pad 8 smd rect (at -7.9 -2.5 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 38 "Net-(U4-Pad8)")) - (pad 9 smd rect (at -7.9 -2 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 39 "Net-(U4-Pad9)")) - (pad 10 smd rect (at -7.9 -1.5 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 121 GND)) - (pad 11 smd rect (at -7.9 -1 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 120 VSTM33)) - (pad 12 smd rect (at -7.9 -0.5 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 40 "Net-(U4-Pad12)")) - (pad 13 smd rect (at -7.9 0 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 41 "Net-(U4-Pad13)")) - (pad 14 smd rect (at -7.9 0.5 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 42 "Net-(U4-Pad14)")) - (pad 15 smd rect (at -7.9 1 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 43 "Net-(U4-Pad15)")) - (pad 16 smd rect (at -7.9 1.5 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 44 "Net-(U4-Pad16)")) - (pad 17 smd rect (at -7.9 2 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 45 "Net-(U4-Pad17)")) - (pad 18 smd rect (at -7.9 2.5 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 46 "Net-(U4-Pad18)")) - (pad 19 smd rect (at -7.9 3 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 120 VSTM33)) - (pad 20 smd rect (at -7.9 3.5 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 121 GND)) - (pad 21 smd rect (at -7.9 4 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 120 VSTM33)) - (pad 22 smd rect (at -7.9 4.5 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 120 VSTM33)) - (pad 23 smd rect (at -7.9 5 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 47 "Net-(U4-Pad23)")) - (pad 24 smd rect (at -7.9 5.5 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 48 "Net-(U4-Pad24)")) - (pad 25 smd rect (at -7.9 6 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 49 "Net-(U4-Pad25)")) - (pad 26 smd rect (at -6 7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 50 "Net-(U4-Pad26)")) - (pad 27 smd rect (at -5.5 7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 121 GND)) - (pad 28 smd rect (at -5 7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 120 VSTM33)) - (pad 29 smd rect (at -4.5 7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 51 "Net-(U4-Pad29)")) - (pad 30 smd rect (at -4 7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 52 "Net-(U4-Pad30)")) - (pad 31 smd rect (at -3.5 7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 53 "Net-(U4-Pad31)")) - (pad 32 smd rect (at -3 7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 54 "Net-(U4-Pad32)")) - (pad 33 smd rect (at -2.5 7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 55 "Net-(U4-Pad33)")) - (pad 34 smd rect (at -2 7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 56 "Net-(U4-Pad34)")) - (pad 35 smd rect (at -1.5 7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 57 "Net-(U4-Pad35)")) - (pad 36 smd rect (at -1 7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 58 "Net-(U4-Pad36)")) - (pad 37 smd rect (at -0.5 7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 59 /FSMC/BOOT1)) - (pad 38 smd rect (at 0 7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 60 /FSMC/DA4)) - (pad 39 smd rect (at 0.5 7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 61 /FSMC/DA5)) - (pad 40 smd rect (at 1 7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 62 /FSMC/DA6)) - (pad 41 smd rect (at 1.5 7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 63 /FSMC/DA7)) - (pad 42 smd rect (at 2 7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 64 /FSMC/DA8)) - (pad 43 smd rect (at 2.5 7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 65 /FSMC/DA9)) - (pad 44 smd rect (at 3 7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 66 /FSMC/DA10)) - (pad 45 smd rect (at 3.5 7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 67 /FSMC/DA11)) - (pad 46 smd rect (at 4 7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 68 /FSMC/DA12)) - (pad 47 smd rect (at 4.5 7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 69 "Net-(U4-Pad47)")) - (pad 48 smd rect (at 5 7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 70 "Net-(U4-Pad48)")) - (pad 49 smd rect (at 5.5 7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 122 /powersupply/VCAP1)) - (pad 50 smd rect (at 6 7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 120 VSTM33)) - (pad 51 smd rect (at 7.9 6 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 71 "Net-(U4-Pad51)")) - (pad 52 smd rect (at 7.9 5.5 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 72 "Net-(U4-Pad52)")) - (pad 53 smd rect (at 7.9 5 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 73 "Net-(U4-Pad53)")) - (pad 54 smd rect (at 7.9 4.5 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 74 "Net-(U4-Pad54)")) - (pad 55 smd rect (at 7.9 4 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -7.9 -6 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 25 /FSMC/A23)) + (pad 2 smd rect (at -7.9 -5.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 26 /FSMC/A19)) + (pad 3 smd rect (at -7.9 -5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 27 /FSMC/A20)) + (pad 4 smd rect (at -7.9 -4.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 28 /FSMC/A21)) + (pad 5 smd rect (at -7.9 -4 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 29 /FSMC/A22)) + (pad 6 smd rect (at -7.9 -3.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 109 VSTM33)) + (pad 7 smd rect (at -7.9 -3 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 30 "Net-(U4-Pad7)")) + (pad 8 smd rect (at -7.9 -2.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 31 "Net-(U4-Pad8)")) + (pad 9 smd rect (at -7.9 -2 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 32 "Net-(U4-Pad9)")) + (pad 10 smd rect (at -7.9 -1.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 110 GND)) + (pad 11 smd rect (at -7.9 -1 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 109 VSTM33)) + (pad 12 smd rect (at -7.9 -0.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 113 "Net-(C40-Pad1)")) + (pad 13 smd rect (at -7.9 0 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 114 "Net-(C41-Pad1)")) + (pad 14 smd rect (at -7.9 0.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 33 "Net-(U4-Pad14)")) + (pad 15 smd rect (at -7.9 1 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 34 "Net-(U4-Pad15)")) + (pad 16 smd rect (at -7.9 1.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 35 "Net-(U4-Pad16)")) + (pad 17 smd rect (at -7.9 2 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 36 "Net-(U4-Pad17)")) + (pad 18 smd rect (at -7.9 2.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 37 "Net-(U4-Pad18)")) + (pad 19 smd rect (at -7.9 3 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 109 VSTM33)) + (pad 20 smd rect (at -7.9 3.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 110 GND)) + (pad 21 smd rect (at -7.9 4 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 109 VSTM33)) + (pad 22 smd rect (at -7.9 4.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 109 VSTM33)) + (pad 23 smd rect (at -7.9 5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 38 "Net-(U4-Pad23)")) + (pad 24 smd rect (at -7.9 5.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 39 "Net-(U4-Pad24)")) + (pad 25 smd rect (at -7.9 6 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 40 "Net-(U4-Pad25)")) + (pad 26 smd rect (at -6 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 41 "Net-(U4-Pad26)")) + (pad 27 smd rect (at -5.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 110 GND)) + (pad 28 smd rect (at -5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 109 VSTM33)) + (pad 29 smd rect (at -4.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 42 "Net-(U4-Pad29)")) + (pad 30 smd rect (at -4 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 43 "Net-(U4-Pad30)")) + (pad 31 smd rect (at -3.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 44 "Net-(U4-Pad31)")) + (pad 32 smd rect (at -3 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 45 "Net-(U4-Pad32)")) + (pad 33 smd rect (at -2.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 46 "Net-(U4-Pad33)")) + (pad 34 smd rect (at -2 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 47 "Net-(U4-Pad34)")) + (pad 35 smd rect (at -1.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 48 "Net-(U4-Pad35)")) + (pad 36 smd rect (at -1 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 49 "Net-(U4-Pad36)")) + (pad 37 smd rect (at -0.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 50 /FSMC/BOOT1)) + (pad 38 smd rect (at 0 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 51 /FSMC/DA4)) + (pad 39 smd rect (at 0.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 52 /FSMC/DA5)) + (pad 40 smd rect (at 1 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 53 /FSMC/DA6)) + (pad 41 smd rect (at 1.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 54 /FSMC/DA7)) + (pad 42 smd rect (at 2 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 55 /FSMC/DA8)) + (pad 43 smd rect (at 2.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 56 /FSMC/DA9)) + (pad 44 smd rect (at 3 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 57 /FSMC/DA10)) + (pad 45 smd rect (at 3.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 58 /FSMC/DA11)) + (pad 46 smd rect (at 4 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 59 /FSMC/DA12)) + (pad 47 smd rect (at 4.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 60 "Net-(U4-Pad47)")) + (pad 48 smd rect (at 5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 61 "Net-(U4-Pad48)")) + (pad 49 smd rect (at 5.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 111 /powersupply/VCAP1)) + (pad 50 smd rect (at 6 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 109 VSTM33)) + (pad 51 smd rect (at 7.9 6 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 62 "Net-(U4-Pad51)")) + (pad 52 smd rect (at 7.9 5.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 63 "Net-(U4-Pad52)")) + (pad 53 smd rect (at 7.9 5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 64 "Net-(U4-Pad53)")) + (pad 54 smd rect (at 7.9 4.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 65 "Net-(U4-Pad54)")) + (pad 55 smd rect (at 7.9 4 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) (net 1 /FSMC/DA13)) - (pad 56 smd rect (at 7.9 3.5 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 75 /FSMC/DA14)) - (pad 57 smd rect (at 7.9 3 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 76 /FSMC/DA15)) - (pad 58 smd rect (at 7.9 2.5 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 77 /FSMC/A16)) - (pad 59 smd rect (at 7.9 2 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 78 /FSMC/A17)) - (pad 60 smd rect (at 7.9 1.5 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 79 /FSMC/A18)) - (pad 61 smd rect (at 7.9 1 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 80 /FSMC/DA0)) - (pad 62 smd rect (at 7.9 0.5 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 81 /FSMC/DA1)) - (pad 63 smd rect (at 7.9 0 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 82 "Net-(U4-Pad63)")) - (pad 64 smd rect (at 7.9 -0.5 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 83 "Net-(U4-Pad64)")) - (pad 65 smd rect (at 7.9 -1 270) (size 1.5 0.28) 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(layers F.Cu F.Paste F.Mask) - (net 121 GND)) - (pad 75 smd rect (at 7.9 -6 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 120 VSTM33)) - (pad 76 smd rect (at 6 -7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 92 "Net-(U4-Pad76)")) - (pad 77 smd rect (at 5.5 -7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 93 "Net-(U4-Pad77)")) - (pad 78 smd rect (at 5 -7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 94 "Net-(U4-Pad78)")) - (pad 79 smd rect (at 4.5 -7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 95 "Net-(U4-Pad79)")) - (pad 80 smd rect (at 4 -7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 96 "Net-(U4-Pad80)")) - (pad 81 smd rect (at 3.5 -7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 97 /FSMC/DA2)) - (pad 82 smd rect (at 3 -7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 98 /FSMC/DA3)) - (pad 83 smd rect (at 2.5 -7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 99 "Net-(U4-Pad83)")) - (pad 84 smd rect (at 2 -7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 100 /FSMC/CLK)) - (pad 85 smd rect (at 1.5 -7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 101 /FSMC/OE_N)) - (pad 86 smd rect (at 1 -7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 102 /FSMC/WE_N)) - (pad 87 smd rect (at 0.5 -7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 103 /FSMC/WAIT_N)) - (pad 88 smd rect (at 0 -7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (pad 56 smd rect (at 7.9 3.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 66 /FSMC/DA14)) + (pad 57 smd rect (at 7.9 3 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 67 /FSMC/DA15)) + (pad 58 smd rect (at 7.9 2.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 68 /FSMC/A16)) + (pad 59 smd rect (at 7.9 2 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 69 /FSMC/A17)) + (pad 60 smd rect (at 7.9 1.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 70 /FSMC/A18)) + (pad 61 smd rect (at 7.9 1 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 71 /FSMC/DA0)) + (pad 62 smd rect (at 7.9 0.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 72 /FSMC/DA1)) + (pad 63 smd rect (at 7.9 0 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 73 "Net-(U4-Pad63)")) + (pad 64 smd rect (at 7.9 -0.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 74 "Net-(U4-Pad64)")) + (pad 65 smd rect (at 7.9 -1 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 75 "Net-(U4-Pad65)")) + (pad 66 smd rect (at 7.9 -1.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 76 "Net-(U4-Pad66)")) + (pad 67 smd rect (at 7.9 -2 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 77 "Net-(U4-Pad67)")) + (pad 68 smd rect (at 7.9 -2.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 78 "Net-(U4-Pad68)")) + (pad 69 smd rect (at 7.9 -3 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 79 "Net-(U4-Pad69)")) + (pad 70 smd rect (at 7.9 -3.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 80 "Net-(U4-Pad70)")) + (pad 71 smd rect (at 7.9 -4 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 81 "Net-(U4-Pad71)")) + (pad 72 smd rect (at 7.9 -4.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 82 "Net-(U4-Pad72)")) + (pad 73 smd rect (at 7.9 -5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 112 /powersupply/VCAP2)) + (pad 74 smd rect (at 7.9 -5.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 110 GND)) + (pad 75 smd rect (at 7.9 -6 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 109 VSTM33)) + (pad 76 smd rect (at 6 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 83 "Net-(U4-Pad76)")) + (pad 77 smd rect (at 5.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 84 "Net-(U4-Pad77)")) + (pad 78 smd rect (at 5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 85 "Net-(U4-Pad78)")) + (pad 79 smd rect (at 4.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 86 "Net-(U4-Pad79)")) + (pad 80 smd rect (at 4 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 87 "Net-(U4-Pad80)")) + (pad 81 smd rect (at 3.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 88 /FSMC/DA2)) + (pad 82 smd rect (at 3 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 89 /FSMC/DA3)) + (pad 83 smd rect (at 2.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 90 "Net-(U4-Pad83)")) + (pad 84 smd rect (at 2 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 91 /FSMC/CLK)) + (pad 85 smd rect (at 1.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 92 /FSMC/OE_N)) + (pad 86 smd rect (at 1 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 93 /FSMC/WE_N)) + (pad 87 smd rect (at 0.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 94 /FSMC/WAIT_N)) + (pad 88 smd rect (at 0 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) (net 2 /FSMC/E1_N)) - (pad 89 smd rect (at -0.5 -7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 104 /FSMC/JTDO)) - (pad 90 smd rect (at -1 -7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 105 /FSMC/JRST_N)) - (pad 91 smd rect (at -1.5 -7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 106 "Net-(U4-Pad91)")) - (pad 92 smd rect (at -2 -7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 107 "Net-(U4-Pad92)")) - (pad 93 smd rect (at -2.5 -7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 108 /FSMC/ADV_N)) - (pad 94 smd rect (at -3 -7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 109 "Net-(U4-Pad94)")) - (pad 95 smd rect (at -3.5 -7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 110 "Net-(U4-Pad95)")) - (pad 96 smd rect (at -4 -7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 111 "Net-(U4-Pad96)")) - (pad 97 smd rect (at -4.5 -7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 112 /FSMC/BL0_N)) - (pad 98 smd rect (at -5 -7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 113 /FSMC/BL1_N)) - (pad 99 smd rect (at -5.5 -7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 121 GND)) - (pad 100 smd rect (at -6 -7.9) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) - (net 120 VSTM33)) + (pad 89 smd rect (at -0.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 95 /FSMC/JTDO)) + (pad 90 smd rect (at -1 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 96 /FSMC/JRST_N)) + (pad 91 smd rect (at -1.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 97 "Net-(U4-Pad91)")) + (pad 92 smd rect (at -2 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 98 "Net-(U4-Pad92)")) + (pad 93 smd rect (at -2.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 99 /FSMC/ADV_N)) + (pad 94 smd rect (at -3 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 100 "Net-(U4-Pad94)")) + (pad 95 smd rect (at -3.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 101 "Net-(U4-Pad95)")) + (pad 96 smd rect (at -4 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 102 "Net-(U4-Pad96)")) + (pad 97 smd rect (at -4.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 103 /FSMC/BL0_N)) + (pad 98 smd rect (at -5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 104 /FSMC/BL1_N)) + (pad 99 smd rect (at -5.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 110 GND)) + (pad 100 smd rect (at -6 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask) + (net 109 VSTM33)) (model Housings_QFP.3dshapes/LQFP-100_14x14mm_Pitch0.5mm.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -579,15 +639,15 @@ ) (module Housings_QFP:LQFP-144_20x20mm_Pitch0.5mm (layer F.Cu) (tedit 54130A77) (tstamp 56C45027) - (at 136.366 70.354 270) + (at 73.543728 58.395542 180) (descr "144-Lead Plastic Low Profile Quad Flatpack (PL) - 20x20x1.40 mm Body [LQFP], 2.00 mm Footprint (see Microchip Packaging Specification 00000049BS.pdf)") (tags "QFP 0.5") (path /563244F7/56323459) (attr smd) - (fp_text reference U3 (at 0 -12.475 270) (layer F.SilkS) + (fp_text reference U3 (at 0 -12.475 180) (layer F.SilkS) (effects (font (size 1 1) (thickness 0.15))) ) - (fp_text value LFXP2-5E-6TN144C (at 0 12.475 270) (layer F.Fab) + (fp_text value LFXP2-5E-6TN144C (at 0 12.475 180) (layer F.Fab) (effects (font (size 1 1) (thickness 0.15))) ) (fp_line (start -11.75 -11.75) (end -11.75 11.75) (layer F.CrtYd) (width 0.05)) @@ -603,294 +663,294 @@ (fp_line (start 10.175 10.175) (end 9.125 10.175) (layer F.SilkS) (width 0.15)) (fp_line (start 10.175 -10.175) (end 9.125 -10.175) (layer F.SilkS) (width 0.15)) (fp_line (start -10.175 -9.125) (end -11.475 -9.125) (layer F.SilkS) (width 0.15)) - (pad 1 smd rect (at -10.7 -8.75 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 114 /FSMC/B7)) - (pad 2 smd rect (at -10.7 -8.25 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 114 /FSMC/B7)) - (pad 3 smd rect (at -10.7 -7.75 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -10.7 -8.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 105 /FSMC/B7)) + (pad 2 smd rect (at -10.7 -8.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 105 /FSMC/B7)) + (pad 3 smd rect (at -10.7 -7.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) (net 6 "Net-(U3-Pad3)")) - (pad 4 smd rect (at -10.7 -7.25 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (pad 4 smd rect (at -10.7 -7.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) (net 7 "Net-(U3-Pad4)")) - (pad 5 smd rect (at -10.7 -6.75 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 114 /FSMC/B7)) - (pad 6 smd rect (at -10.7 -6.25 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 114 /FSMC/B7)) - (pad 7 smd rect (at -10.7 -5.75 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 114 /FSMC/B7)) - (pad 8 smd rect (at -10.7 -5.25 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 114 /FSMC/B7)) - (pad 9 smd rect (at -10.7 -4.75 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 114 /FSMC/B7)) - (pad 10 smd rect (at -10.7 -4.25 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 114 /FSMC/B7)) - (pad 11 smd rect (at -10.7 -3.75 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 114 /FSMC/B7)) - (pad 12 smd rect (at -10.7 -3.25 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (pad 5 smd rect (at -10.7 -6.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 105 /FSMC/B7)) + (pad 6 smd rect (at -10.7 -6.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 105 /FSMC/B7)) + (pad 7 smd rect (at -10.7 -5.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 105 /FSMC/B7)) + (pad 8 smd rect (at -10.7 -5.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 105 /FSMC/B7)) + (pad 9 smd rect (at -10.7 -4.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 105 /FSMC/B7)) + (pad 10 smd rect (at -10.7 -4.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 105 /FSMC/B7)) + (pad 11 smd rect (at -10.7 -3.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 105 /FSMC/B7)) + (pad 12 smd rect (at -10.7 -3.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) (net 8 "Net-(U3-Pad12)")) - (pad 13 smd rect (at -10.7 -2.75 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 114 /FSMC/B7)) - (pad 14 smd rect (at -10.7 -2.25 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (pad 13 smd rect (at -10.7 -2.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 105 /FSMC/B7)) + (pad 14 smd rect (at -10.7 -2.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) (net 9 "Net-(U3-Pad14)")) - (pad 15 smd rect (at -10.7 -1.75 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 114 /FSMC/B7)) - (pad 16 smd rect (at -10.7 -1.25 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 114 /FSMC/B7)) - (pad 17 smd rect (at -10.7 -0.75 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 114 /FSMC/B7)) - (pad 18 smd rect (at -10.7 -0.25 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 114 /FSMC/B7)) - (pad 19 smd rect (at -10.7 0.25 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 114 /FSMC/B7)) - (pad 20 smd rect (at -10.7 0.75 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 114 /FSMC/B7)) - (pad 21 smd rect (at -10.7 1.25 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 114 /FSMC/B7)) - (pad 22 smd rect (at -10.7 1.75 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 114 /FSMC/B7)) - (pad 23 smd rect (at -10.7 2.25 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 10 +3V3)) - (pad 24 smd rect (at -10.7 2.75 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 11 +1V2)) - (pad 25 smd rect (at -10.7 3.25 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 12 "Net-(R2-Pad2)")) - (pad 26 smd rect (at -10.7 3.75 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 13 "Net-(R3-Pad2)")) - (pad 27 smd rect (at -10.7 4.25 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 115 /FSMC/B6)) - (pad 28 smd rect (at -10.7 4.75 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 115 /FSMC/B6)) - (pad 29 smd rect (at -10.7 5.25 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 115 /FSMC/B6)) - (pad 30 smd rect (at -10.7 5.75 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 115 /FSMC/B6)) - (pad 31 smd rect (at -10.7 6.25 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 115 /FSMC/B6)) - (pad 32 smd rect (at -10.7 6.75 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 115 /FSMC/B6)) - (pad 33 smd rect (at -10.7 7.25 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 14 "Net-(U3-Pad33)")) - (pad 34 smd rect (at -10.7 7.75 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 15 "Net-(U3-Pad34)")) - (pad 35 smd rect (at -10.7 8.25 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 115 /FSMC/B6)) - (pad 36 smd rect (at -10.7 8.75 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 115 /FSMC/B6)) - (pad 37 smd rect (at -8.75 10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 116 /FSMC/B5)) - (pad 38 smd rect (at -8.25 10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 116 /FSMC/B5)) - (pad 39 smd rect (at -7.75 10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 116 /FSMC/B5)) - (pad 40 smd rect (at -7.25 10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 116 /FSMC/B5)) - (pad 41 smd rect (at -6.75 10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 16 "Net-(U3-Pad41)")) - (pad 42 smd rect (at -6.25 10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 17 "Net-(U3-Pad42)")) - (pad 43 smd rect (at -5.75 10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 116 /FSMC/B5)) - (pad 44 smd rect (at -5.25 10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 116 /FSMC/B5)) - (pad 45 smd rect (at -4.75 10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 116 /FSMC/B5)) - (pad 46 smd rect (at -4.25 10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 116 /FSMC/B5)) - (pad 47 smd rect (at -3.75 10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 116 /FSMC/B5)) - (pad 48 smd rect (at -3.25 10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 116 /FSMC/B5)) - (pad 49 smd rect (at -2.75 10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 18 "Net-(U3-Pad49)")) - (pad 50 smd rect (at -2.25 10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 116 /FSMC/B5)) - (pad 51 smd rect (at -1.75 10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 19 "Net-(U3-Pad51)")) - (pad 52 smd rect (at -1.25 10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 116 /FSMC/B5)) - (pad 53 smd rect (at -0.75 10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 116 /FSMC/B5)) - (pad 54 smd rect (at -0.25 10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 116 /FSMC/B5)) - (pad 55 smd rect (at 0.25 10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 116 /FSMC/B5)) - (pad 56 smd rect (at 0.75 10.7) (size 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smd rect (at 10.7 -3.75 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 119 /FSMC/B2)) - (pad 99 smd rect (at 10.7 -4.25 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 119 /FSMC/B2)) - (pad 100 smd rect (at 10.7 -4.75 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 119 /FSMC/B2)) - (pad 101 smd rect (at 10.7 -5.25 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 119 /FSMC/B2)) - (pad 102 smd rect (at 10.7 -5.75 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 119 /FSMC/B2)) - (pad 103 smd rect (at 10.7 -6.25 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 119 /FSMC/B2)) - (pad 104 smd rect (at 10.7 -6.75 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 119 /FSMC/B2)) - (pad 105 smd rect (at 10.7 -7.25 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 30 "Net-(U3-Pad105)")) - (pad 106 smd rect (at 10.7 -7.75 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 31 "Net-(U3-Pad106)")) - (pad 107 smd rect (at 10.7 -8.25 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 119 /FSMC/B2)) - (pad 108 smd rect (at 10.7 -8.75 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 119 /FSMC/B2)) - (pad 109 smd rect (at 8.75 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 108 /FSMC/ADV_N)) - (pad 110 smd rect (at 8.25 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (pad 87 smd rect (at 10.7 1.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 127 /display/WR)) + (pad 88 smd rect (at 10.7 1.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 129 /display/RD)) + (pad 89 smd rect (at 10.7 0.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 122 /display/DB0)) + (pad 90 smd rect (at 10.7 0.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 123 /display/DB1)) + (pad 91 smd rect (at 10.7 -0.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 124 /display/DB2)) + (pad 92 smd rect (at 10.7 -0.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 126 /display/DB3)) + (pad 93 smd rect (at 10.7 -1.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 128 /display/DB4)) + (pad 94 smd rect (at 10.7 -1.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 130 /display/DB5)) + (pad 95 smd rect (at 10.7 -2.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 4 VFPGA33)) + (pad 96 smd rect (at 10.7 -2.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 131 /display/DB8)) + (pad 97 smd rect (at 10.7 -3.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 110 GND)) + (pad 98 smd rect (at 10.7 -3.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 132 /display/DB6)) + (pad 99 smd rect (at 10.7 -4.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 133 /display/DB9)) + (pad 100 smd rect (at 10.7 -4.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 134 /display/DB7)) + (pad 101 smd rect (at 10.7 -5.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 135 /display/DB10)) + (pad 102 smd rect (at 10.7 -5.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 136 /display/DB11)) + (pad 103 smd rect (at 10.7 -6.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 137 /display/DB12)) + (pad 104 smd rect (at 10.7 -6.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 138 /display/DB13)) + (pad 105 smd rect (at 10.7 -7.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 4 VFPGA33)) + (pad 106 smd rect (at 10.7 -7.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 110 GND)) + (pad 107 smd rect (at 10.7 -8.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 139 /display/DB14)) + (pad 108 smd rect (at 10.7 -8.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 140 /display/DB15)) + (pad 109 smd rect (at 8.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 99 /FSMC/ADV_N)) + (pad 110 smd rect (at 8.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) (net 2 /FSMC/E1_N)) - (pad 111 smd rect (at 7.75 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 121 GND)) - (pad 112 smd rect (at 7.25 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (pad 111 smd rect (at 7.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 110 GND)) + (pad 112 smd rect (at 7.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) (net 4 VFPGA33)) - (pad 113 smd rect (at 6.75 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 103 /FSMC/WAIT_N)) - (pad 114 smd rect (at 6.25 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 102 /FSMC/WE_N)) - (pad 115 smd rect (at 5.75 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 101 /FSMC/OE_N)) - (pad 116 smd rect (at 5.25 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 100 /FSMC/CLK)) - (pad 117 smd rect (at 4.75 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 10 +3V3)) - (pad 118 smd rect (at 4.25 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 11 +1V2)) - (pad 119 smd rect (at 3.75 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 81 /FSMC/DA1)) - (pad 120 smd rect (at 3.25 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 80 /FSMC/DA0)) - (pad 121 smd rect (at 2.75 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 97 /FSMC/DA2)) - (pad 122 smd rect (at 2.25 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 98 /FSMC/DA3)) - (pad 123 smd rect (at 1.75 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 76 /FSMC/DA15)) - (pad 124 smd rect (at 1.25 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 75 /FSMC/DA14)) - (pad 125 smd rect (at 0.75 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (pad 113 smd rect (at 6.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 94 /FSMC/WAIT_N)) + (pad 114 smd rect (at 6.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 93 /FSMC/WE_N)) + (pad 115 smd rect (at 5.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 92 /FSMC/OE_N)) + (pad 116 smd rect (at 5.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 91 /FSMC/CLK)) + (pad 117 smd rect (at 4.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 4 VFPGA33)) + (pad 118 smd rect (at 4.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 10 +1V2)) + (pad 119 smd rect (at 3.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 72 /FSMC/DA1)) + (pad 120 smd rect (at 3.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 71 /FSMC/DA0)) + (pad 121 smd rect (at 2.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 88 /FSMC/DA2)) + (pad 122 smd rect (at 2.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 89 /FSMC/DA3)) + (pad 123 smd rect (at 1.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 67 /FSMC/DA15)) + (pad 124 smd rect (at 1.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 66 /FSMC/DA14)) + (pad 125 smd rect (at 0.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) (net 1 /FSMC/DA13)) - (pad 126 smd rect (at 0.25 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 121 GND)) - (pad 127 smd rect (at -0.25 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 68 /FSMC/DA12)) - (pad 128 smd rect (at -0.75 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (pad 126 smd rect (at 0.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 110 GND)) + (pad 127 smd rect (at -0.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 59 /FSMC/DA12)) + (pad 128 smd rect (at -0.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) (net 4 VFPGA33)) - (pad 129 smd rect (at -1.25 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 67 /FSMC/DA11)) - (pad 130 smd rect (at -1.75 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 66 /FSMC/DA10)) - (pad 131 smd rect (at -2.25 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 65 /FSMC/DA9)) - (pad 132 smd rect (at -2.75 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 64 /FSMC/DA8)) - (pad 133 smd rect (at -3.25 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 63 /FSMC/DA7)) - (pad 134 smd rect (at -3.75 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 62 /FSMC/DA6)) - (pad 135 smd rect (at -4.25 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 121 GND)) - (pad 136 smd rect (at -4.75 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (pad 129 smd rect (at -1.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 58 /FSMC/DA11)) + (pad 130 smd rect (at -1.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 57 /FSMC/DA10)) + (pad 131 smd rect (at -2.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 56 /FSMC/DA9)) + (pad 132 smd rect (at -2.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 55 /FSMC/DA8)) + (pad 133 smd rect (at -3.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 54 /FSMC/DA7)) + (pad 134 smd rect (at -3.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 53 /FSMC/DA6)) + (pad 135 smd rect (at -4.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 110 GND)) + (pad 136 smd rect (at -4.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) (net 4 VFPGA33)) - (pad 137 smd rect (at -5.25 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 61 /FSMC/DA5)) - (pad 138 smd rect (at -5.75 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 60 /FSMC/DA4)) - (pad 139 smd rect (at -6.25 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (pad 137 smd rect (at -5.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 52 /FSMC/DA5)) + (pad 138 smd rect (at -5.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 51 /FSMC/DA4)) + (pad 139 smd rect (at -6.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) (net 5 GNDD)) - (pad 140 smd rect (at -6.75 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 10 +3V3)) - (pad 141 smd rect (at -7.25 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 77 /FSMC/A16)) - (pad 142 smd rect (at -7.75 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 78 /FSMC/A17)) - (pad 143 smd rect (at -8.25 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 79 /FSMC/A18)) - (pad 144 smd rect (at -8.75 -10.7) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) - (net 33 /FSMC/A19)) + (pad 140 smd rect (at -6.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 4 VFPGA33)) + (pad 141 smd rect (at -7.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 68 /FSMC/A16)) + (pad 142 smd rect (at -7.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 69 /FSMC/A17)) + (pad 143 smd rect (at -8.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 70 /FSMC/A18)) + (pad 144 smd rect (at -8.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask) + (net 26 /FSMC/A19)) (model Housings_QFP.3dshapes/LQFP-144_20x20mm_Pitch0.5mm.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) @@ -899,15 +959,15 @@ ) (module TO_SOT_Packages_SMD:SOT-223 (layer F.Cu) (tedit 0) (tstamp 56C44F93) - (at 179.832 62.23) + (at 104.648 84.582 270) (descr "module CMS SOT223 4 pins") (tags "CMS SOT") (path /563244F7/5632574B) (attr smd) - (fp_text reference U1 (at 0 -0.762) (layer F.SilkS) + (fp_text reference U1 (at 0 -0.762 270) (layer F.SilkS) (effects (font (size 1 1) (thickness 0.15))) ) - (fp_text value LD1117S12CTR (at 0 0.762) (layer F.Fab) + (fp_text value LD1117S12CTR (at 0 0.762 270) (layer F.Fab) (effects (font (size 1 1) (thickness 0.15))) ) (fp_line (start -3.556 1.524) (end -3.556 4.572) (layer F.SilkS) (width 0.15)) @@ -918,12 +978,12 @@ (fp_line (start -2.032 -4.572) (end 2.032 -4.572) (layer F.SilkS) (width 0.15)) (fp_line (start 2.032 -4.572) (end 3.556 -2.286) (layer F.SilkS) (width 0.15)) (fp_line (start 3.556 -2.286) (end 3.556 -1.524) (layer F.SilkS) (width 0.15)) - (pad 4 smd rect (at 0 -3.302) (size 3.6576 2.032) (layers F.Cu F.Paste F.Mask)) - (pad 2 smd rect (at 0 3.302) (size 1.016 2.032) (layers F.Cu F.Paste F.Mask) + (pad 4 smd rect (at 0 -3.302 270) (size 3.6576 2.032) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd rect (at 0 3.302 270) (size 1.016 2.032) (layers F.Cu F.Paste F.Mask) (net 3 "Net-(C4-Pad1)")) - (pad 3 smd rect (at 2.286 3.302) (size 1.016 2.032) (layers F.Cu F.Paste F.Mask) + (pad 3 smd rect (at 2.286 3.302 270) (size 1.016 2.032) (layers F.Cu F.Paste F.Mask) (net 4 VFPGA33)) - (pad 1 smd rect (at -2.286 3.302) (size 1.016 2.032) (layers F.Cu F.Paste F.Mask) + (pad 1 smd rect (at -2.286 3.302 270) (size 1.016 2.032) (layers F.Cu F.Paste F.Mask) (net 5 GNDD)) (model TO_SOT_Packages_SMD.3dshapes/SOT-223.wrl (at (xyz 0 0 0)) @@ -932,198 +992,384 @@ ) ) - (segment (start 152.058687 74.983501) (end 158.223499 74.983501) (width 0.153) (layer F.Cu) (net 1)) - (segment (start 158.223499 74.983501) (end 158.3 74.907) (width 0.153) (layer F.Cu) (net 1)) - (segment (start 158.3 74.907) (end 158.3 74.004) (width 0.153) (layer F.Cu) (net 1)) - (segment (start 152.058687 74.983501) (end 148.179186 71.104) (width 0.153) (layer F.Cu) (net 1)) - (segment (start 148.179186 71.104) (end 147.066 71.104) (width 0.153) (layer F.Cu) (net 1)) - (segment (start 149.020789 78.6) (end 148.453553 78.6) (width 0.153) (layer B.Cu) (net 2)) - (segment (start 173.50354 67.449987) (end 173.50354 69.837173) (width 0.153) (layer B.Cu) (net 2)) - (segment (start 171.8 66.1) (end 172.153553 66.1) (width 0.153) (layer B.Cu) (net 2)) - (segment (start 172.153553 66.1) (end 173.50354 67.449987) (width 0.153) (layer B.Cu) (net 2)) - (segment (start 148.453553 78.6) (end 148.1 78.6) (width 0.153) (layer B.Cu) (net 2)) - (segment (start 150.8268 76.793989) (end 149.020789 78.6) (width 0.153) (layer B.Cu) (net 2)) - (segment (start 166.546724 76.793989) (end 150.8268 76.793989) (width 0.153) (layer B.Cu) (net 2)) - (segment (start 173.50354 69.837173) (end 166.546724 76.793989) (width 0.153) (layer B.Cu) (net 2)) - (segment (start 170.232 66.104) (end 171.796 66.104) (width 0.153) (layer F.Cu) (net 2)) - (segment (start 171.796 66.104) (end 171.8 66.1) (width 0.153) (layer F.Cu) (net 2)) - (via (at 171.8 66.1) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 2)) - (segment (start 147.066 78.604) (end 148.096 78.604) (width 0.153) (layer F.Cu) (net 2)) - (segment (start 148.096 78.604) (end 148.1 78.6) (width 0.153) (layer F.Cu) (net 2)) - (via (at 148.1 78.6) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 2)) - (segment (start 154.432 66.104) (end 149.336864 66.104) (width 0.153) (layer F.Cu) (net 60)) - (segment (start 149.336864 66.104) (end 147.836864 64.604) (width 0.153) (layer F.Cu) (net 60)) - (segment (start 147.836864 64.604) (end 147.066 64.604) (width 0.153) (layer F.Cu) (net 60)) - (segment (start 154.432 66.604) (end 149.404102 66.604) (width 0.153) (layer F.Cu) (net 61)) - (segment (start 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(end 41.820458 67.145542) (width 0.153) (layer F.Cu) (net 140)) + (segment (start 41.820458 67.145542) (end 32.082595 76.883405) (width 0.153) (layer F.Cu) (net 140)) + (segment (start 31.015311 76.865499) (end 30.446899 77.433911) (width 0.153) (layer F.Cu) (net 140)) + (segment (start 32.082595 76.883405) (end 32.064689 76.865499) (width 0.153) (layer F.Cu) (net 140)) + (segment (start 30.446899 78.483289) (end 30.464805 78.501195) (width 0.153) (layer F.Cu) (net 140)) + (segment (start 30.464805 78.501195) (end 30.093101 78.872899) (width 0.153) (layer F.Cu) (net 140)) + (segment (start 30.093101 78.872899) (end 30.093101 79.405499) (width 0.153) (layer F.Cu) (net 140)) + (segment (start 30.093101 79.405499) (end 29.863599 79.635001) (width 0.153) (layer F.Cu) (net 140)) + (segment (start 29.863599 79.635001) (end 29 80.4986) (width 0.153) (layer F.Cu) (net 140)) ) diff --git a/fpgna.net b/fpgna.net index ba0f07f..82372c1 100644 --- a/fpgna.net +++ b/fpgna.net @@ -1,7 +1,7 @@ (export (version D) (design (source /home/kurisu/projects/kicad/fpgna/fpgna.sch) - (date "Wed 17 Feb 2016 03:43:00 PM CET") + (date "Thu 18 Feb 2016 02:14:17 PM CET") (tool "Eeschema (2016-02-12 BZR 6554)-stable") (sheet (number 1) (name /) (tstamps /) (title_block @@ -21,7 +21,7 @@ (rev) (date) (source power.sch) - (comment (number 1) (value "Power supply, clock and JTAG")) + (comment (number 1) (value "Power supply and clock")) (comment (number 2) (value "")) (comment (number 3) (value "")) (comment (number 4) (value "")))) @@ -46,6 +46,17 @@ (comment (number 1) (value "")) (comment (number 2) (value "")) (comment (number 3) (value "")) + (comment (number 4) (value "")))) + (sheet (number 5) (name /display/) (tstamps /56C579FC/) + (title_block + (title) + (company) + (rev) + (date) + (source display.sch) + (comment (number 1) (value "")) + (comment (number 2) (value "")) + (comment (number 3) (value "")) (comment (number 4) (value ""))))) (components (comp (ref U3) @@ -333,6 +344,88 @@ (libsource (lib device) (part CP)) (sheetpath (names /powersupply/) (tstamps /563244F7/)) (tstamp 56C62D98)) + (comp (ref C33) + (value 100n) + (libsource (lib device) (part C)) + (sheetpath (names /powersupply/) (tstamps /563244F7/)) + (tstamp 56C5067D)) + (comp (ref C34) + (value 100n) + (libsource (lib device) (part C)) + (sheetpath (names /powersupply/) (tstamps /563244F7/)) + (tstamp 56C50683)) + (comp (ref C35) + (value 100n) + (libsource (lib device) (part C)) + (sheetpath (names /powersupply/) (tstamps /563244F7/)) + (tstamp 56C50689)) + (comp (ref C36) + (value 100n) + (libsource (lib device) (part C)) + (sheetpath (names /powersupply/) (tstamps /563244F7/)) + (tstamp 56C5068F)) + (comp (ref C37) + (value 100n) + (libsource (lib device) (part C)) + (sheetpath (names /powersupply/) (tstamps /563244F7/)) + (tstamp 56C50695)) + (comp (ref C38) + (value 100n) + (libsource (lib device) (part C)) + (sheetpath (names /powersupply/) (tstamps /563244F7/)) + (tstamp 56C5069B)) + (comp (ref C39) + (value 100n) + (libsource (lib device) (part C)) + (sheetpath (names /powersupply/) (tstamps /563244F7/)) + (tstamp 56C506A1)) + (comp (ref C32) + (value 100n) + (libsource (lib device) (part C)) + (sheetpath (names /powersupply/) (tstamps /563244F7/)) + (tstamp 56C50D95)) + (comp (ref C31) + (value 10u) + (libsource (lib device) (part C)) + (sheetpath (names /powersupply/) (tstamps /563244F7/)) + (tstamp 56C52C65)) + (comp (ref R15) + (value 0) + (libsource (lib device) (part R)) + (sheetpath (names /powersupply/) (tstamps /563244F7/)) + (tstamp 56C5AB35)) + (comp (ref U6) + (value ITDB02-3.2WD) + (footprint itead-display:ITDB02-3.2WD) + (libsource (lib itead-displays) (part ITDB02-3.2WD)) + (sheetpath (names /powersupply/) (tstamps /563244F7/)) + (tstamp 56C57ED6)) + (comp (ref C30) + (value 2.2u) + (libsource (lib device) (part C)) + (sheetpath (names /powersupply/) (tstamps /563244F7/)) + (tstamp 56C58841)) + (comp (ref Q5) + (value 3.3LogicLv-P) + (datasheet http://www.digikey.com/product-search/en/discrete-semiconductor-products/fets-single/1376381) + (libsource (lib device) (part Q_PMOS_DGS)) + (sheetpath (names /powersupply/) (tstamps /563244F7/)) + (tstamp 56C5D295)) + (comp (ref R13) + (value 10k) + (libsource (lib device) (part R)) + (sheetpath (names /powersupply/) (tstamps /563244F7/)) + (tstamp 56C641C3)) + (comp (ref R14) + (value 0) + (libsource (lib device) (part R)) + (sheetpath (names /powersupply/) (tstamps /563244F7/)) + (tstamp 56C66E4A)) + (comp (ref C42) + (value 100n) + (libsource (lib device) (part C)) + (sheetpath (names /powersupply/) (tstamps /563244F7/)) + (tstamp 56C5BFA7)) (comp (ref P3) (value Lattice-JTAG) (libsource (lib lattice) (part Lattice-JTAG)) @@ -343,6 +436,26 @@ (libsource (lib device) (part C)) (sheetpath (names /debug/) (tstamps /56337D98/)) (tstamp 56339277)) + (comp (ref Y1) + (value 8M) + (libsource (lib device) (part Crystal_Small)) + (sheetpath (names /debug/) (tstamps /56337D98/)) + (tstamp 56C71642)) + (comp (ref C40) + (value 5p) + (libsource (lib device) (part C_Small)) + (sheetpath (names /debug/) (tstamps /56337D98/)) + (tstamp 56C717BF)) + (comp (ref C41) + (value 5p) + (libsource (lib device) (part C_Small)) + (sheetpath (names /debug/) (tstamps /56337D98/)) + (tstamp 56C7180C)) + (comp (ref P4) + (value JTAG-STM) + (libsource (lib conn) (part CONN_01X06)) + (sheetpath (names /debug/) (tstamps /56337D98/)) + (tstamp 56C73EAE)) (comp (ref C28) (value 100n) (libsource (lib device) (part C)) @@ -357,7 +470,22 @@ (value 100n) (libsource (lib device) (part C)) (sheetpath (names /FSMC/) (tstamps /56C43C85/)) - (tstamp 56C67EC9))) + (tstamp 56C67EC9)) + (comp (ref C44) + (value 100n) + (libsource (lib device) (part C)) + (sheetpath (names /display/) (tstamps /56C579FC/)) + (tstamp 56C62B5E)) + (comp (ref C45) + (value 100n) + (libsource (lib device) (part C)) + (sheetpath (names /display/) (tstamps /56C579FC/)) + (tstamp 56C62B65)) + (comp (ref C43) + (value 100n) + (libsource (lib device) (part C)) + (sheetpath (names /display/) (tstamps /56C579FC/)) + (tstamp 56C62CBE))) (libparts (libpart (lib device) (part C) (description "Unpolarized capacitor") @@ -387,6 +515,23 @@ (pin (num 1) (name P1) (type passive)) (pin (num 2) (name P2) (type passive)) (pin (num 3) (name P3) (type passive)))) + (libpart (lib conn) (part CONN_01X06) + (description "Connector 01x06") + (footprints + (fp Pin_Header_Straight_1X06) + (fp Pin_Header_Angled_1X06) + (fp Socket_Strip_Straight_1X06) + (fp Socket_Strip_Angled_1X06)) + (fields + (field (name Reference) P) + (field (name Value) CONN_01X06)) + (pins + (pin (num 1) (name P1) (type passive)) + (pin (num 2) (name P2) (type passive)) + (pin (num 3) (name P3) (type passive)) + (pin (num 4) (name P4) (type passive)) + (pin (num 5) (name P5) (type passive)) + (pin (num 6) (name P6) (type passive)))) (libpart (lib device) (part CP) (description "Polarised capacitor") (footprints @@ -402,6 +547,30 @@ (pins (pin (num 1) (name ~) (type passive)) (pin (num 2) (name ~) (type passive)))) + (libpart (lib device) (part C_Small) + (description "Unpolarized capacitor") + (footprints + (fp C?) + (fp C_????_*) + (fp C_????) + (fp SMD*_c) + (fp Capacitor*)) + (fields + (field (name Reference) C) + (field (name Value) C_Small)) + (pins + (pin (num 1) (name ~) (type passive)) + (pin (num 2) (name ~) (type passive)))) + (libpart (lib device) (part Crystal_Small) + (description "Two pin crystal") + (footprints + (fp Crystal_)) + (fields + (field (name Reference) Y) + (field (name Value) Crystal_Small)) + (pins + (pin (num 1) (name 1) (type passive)) + (pin (num 2) (name 2) (type passive)))) (libpart (lib device) (part D_Schottky_Small) (description "Diode Schottky") (footprints @@ -423,6 +592,51 @@ (pins (pin (num 1) (name 1) (type passive)) (pin (num 2) (name 2) (type passive)))) + (libpart (lib itead-displays) (part ITDB02-3.2WD) + (fields + (field (name Reference) U) + (field (name Value) ITDB02-3.2WD)) + (pins + (pin (num 1) (name GND) (type power_in)) + (pin (num 2) (name DB0) (type BiDi)) + (pin (num 3) (name VCC) (type power_in)) + (pin (num 4) (name DB1) (type BiDi)) + (pin (num 5) (name NC5) (type BiDi)) + (pin (num 6) (name DB2) (type BiDi)) + (pin (num 7) (name RS) (type input)) + (pin (num 8) (name DB3) (type BiDi)) + (pin (num 9) (name WR) (type input)) + (pin (num 10) (name DB4) (type BiDi)) + (pin (num 11) (name RD) (type input)) + (pin (num 12) (name DB5) (type BiDi)) + (pin (num 13) (name DB8) (type BiDi)) + (pin (num 14) (name DB6) (type BiDi)) + (pin (num 15) (name DB9) (type BiDi)) + (pin (num 16) (name DB7) (type BiDi)) + (pin (num 17) (name DB10) (type BiDi)) + (pin (num 18) (name T_CLK) (type input)) + (pin (num 19) (name DB11) (type BiDi)) + (pin (num 20) (name T_CS) (type input)) + (pin (num 21) (name DB12) (type BiDi)) + (pin (num 22) (name T_DIN) (type input)) + (pin (num 23) (name DB13) (type BiDi)) + (pin (num 24) (name T_BUSY) (type input)) + (pin (num 25) (name DB14) (type BiDi)) + (pin (num 26) (name T_DOUT) (type output)) + (pin (num 27) (name DB15) (type BiDi)) + (pin (num 28) (name T_IRQ) (type output)) + (pin (num 29) (name CS) (type input)) + (pin (num 30) (name SD_SO) (type output)) + (pin (num 31) (name NC31) (type BiDi)) + (pin (num 32) (name SD_SCK) (type output)) + (pin (num 33) (name RST) (type input)) + (pin (num 34) (name SD_SI) (type input)) + (pin (num 35) (name NC35) (type BiDi)) + (pin (num 36) (name SD_NSS) (type input)) + (pin (num 37) (name LED+) (type power_in)) + (pin (num 38) (name NC38) (type input)) + (pin (num 39) (name NC39) (type BiDi)) + (pin (num 40) (name NC40) (type BiDi)))) (libpart (lib regul) (part LD1117S33TR) (aliases (alias LD1117S33CTR) @@ -821,558 +1035,686 @@ (pin (num 1) (name K) (type passive)) (pin (num 2) (name A) (type passive))))) (libraries + (library (logical device) + (uri /usr/share/kicad/library/device.lib)) (library (logical lattice) (uri /home/kurisu/projects/kicad/ShimattaPCBLibs/schematics/lattice/lattice.lib)) (library (logical pmic) (uri /home/kurisu/projects/kicad/ShimattaPCBLibs/schematics/power/pmic.lib)) - (library (logical stm32f4) - (uri /home/kurisu/projects/kicad/ShimattaPCBLibs/schematics/stm/stm32f4.lib)) - (library (logical regulators) - (uri /home/kurisu/projects/kicad/ShimattaPCBLibs/schematics/power/regulators.lib)) - (library (logical regul) - (uri /usr/share/kicad/library/regul.lib)) (library (logical conn) (uri /usr/share/kicad/library/conn.lib)) (library (logical Oscillators) (uri /usr/share/kicad/library/Oscillators.lib)) - (library (logical device) - (uri /usr/share/kicad/library/device.lib))) + (library (logical regul) + (uri /usr/share/kicad/library/regul.lib)) + (library (logical regulators) + (uri /home/kurisu/projects/kicad/ShimattaPCBLibs/schematics/power/regulators.lib)) + (library (logical itead-displays) + (uri /home/kurisu/projects/kicad/ShimattaPCBLibs/schematics/shields/itead-displays.lib)) + (library (logical stm32f4) + (uri /home/kurisu/projects/kicad/ShimattaPCBLibs/schematics/stm/stm32f4.lib))) (nets - (net (code 1) (name GNDD) - (node (ref C19) (pin 2)) - (node (ref C5) (pin 2)) - (node (ref C9) (pin 2)) - (node (ref C11) (pin 2)) - (node (ref C13) (pin 2)) - (node (ref C15) (pin 2)) - (node (ref C17) (pin 2)) - (node (ref C21) (pin 2)) - (node (ref U3) (pin 86)) - (node (ref U3) (pin 68)) - (node (ref U3) (pin 139)) - (node (ref P2) (pin 3)) - (node (ref U2) (pin 3)) - (node (ref U2) (pin 5)) - (node (ref D1) (pin 2)) - (node (ref U1) (pin 1)) - (node (ref C6) (pin 2)) - (node (ref C1) (pin 2)) - (node (ref C2) (pin 2)) - (node (ref C23) (pin 2)) - (node (ref X1) (pin 2)) - (node (ref C4) (pin 2)) - (node (ref C22) (pin 2)) - (node (ref U5) (pin 5)) - (node (ref C3) (pin 2)) - (node (ref P1) (pin 5)) - (node (ref C8) (pin 2)) - (node (ref C10) (pin 2)) - (node (ref C12) (pin 2)) - (node (ref C14) (pin 2)) - (node (ref C16) (pin 2)) - (node (ref C18) (pin 2)) - (node (ref C20) (pin 2)) - (node (ref C24) (pin 2)) - (node (ref P3) (pin 4)) - (node (ref P3) (pin 2)) - (node (ref Q2) (pin 3)) - (node (ref R6) (pin 2)) - (node (ref D2) (pin 2)) - (node (ref R8) (pin 2)) - (node (ref R10) (pin 2)) - (node (ref Q4) (pin 3)) - (node (ref R11) (pin 1))) - (net (code 2) (name +3V3) - (node (ref U3) (pin 67)) - (node (ref U3) (pin 140)) - (node (ref P3) (pin 6)) - (node (ref U3) (pin 83)) - (node (ref U3) (pin 85)) - (node (ref U3) (pin 23)) - (node (ref U3) (pin 117)) - (node (ref X1) (pin 4)) - (node (ref R2) (pin 1)) - (node (ref R3) (pin 1)) - (node (ref C24) (pin 1)) - (node (ref U3) (pin 60))) - (net (code 3) (name /powersupply/CLK_50M) + (net (code 1) (name /powersupply/USB_PRESENT_N) + (node (ref R7) (pin 2)) + (node (ref U5) (pin 7))) + (net (code 2) (name /powersupply/CHG_ACTIVE_N) + (node (ref U5) (pin 3)) + (node (ref R4) (pin 2))) + (net (code 3) (name /FSMC/JRST_N) + (node (ref U4) (pin 90))) + (net (code 4) (name /FSMC/JTDO) + (node (ref U4) (pin 89))) + (net (code 5) (name /FSMC/BOOT1) + (node (ref U4) (pin 37))) + (net (code 7) (name /debug/JRST_N) + (node (ref P4) (pin 5))) + (net (code 8) (name /debug/JTCK) + (node (ref P4) (pin 1))) + (net (code 9) (name /debug/JTDO) + (node (ref P4) (pin 4))) + (net (code 10) (name /debug/JTMS) + (node (ref P4) (pin 2))) + (net (code 11) (name /debug/JTDI) + (node (ref P4) (pin 3))) + (net (code 12) (name /powersupply/FPGA_ENABLE_N) + (node (ref Q1) (pin 2)) + (node (ref R1) (pin 2))) + (net (code 13) (name /powersupply/CLK_50M) (node (ref X1) (pin 3))) - (net (code 4) (name "Net-(R8-Pad1)") - (node (ref U5) (pin 6)) - (node (ref R8) (pin 1))) - (net (code 5) (name VUSB) - (node (ref L3) (pin 1)) - (node (ref C7) (pin 1)) - (node (ref R9) (pin 1)) - (node (ref U5) (pin 1)) - (node (ref U5) (pin 2)) - (node (ref D3) (pin 2)) - (node (ref R10) (pin 1)) - (node (ref Q3) (pin 2))) - (net (code 6) (name VBAT) - (node (ref Q3) (pin 1)) - (node (ref P2) (pin 2)) - (node (ref U5) (pin 10)) - (node (ref U5) (pin 9))) - (net (code 7) (name "Net-(C7-Pad2)") + (net (code 14) (name /powersupply/SYS_VOLTAGE) + (node (ref D2) (pin 1)) + (node (ref R6) (pin 1)) + (node (ref R5) (pin 2))) + (net (code 15) (name /powersupply/CHARGE_ENABLE) + (node (ref R12) (pin 1))) + (net (code 16) (name "Net-(R8-Pad1)") + (node (ref R8) (pin 1)) + (node (ref U5) (pin 6))) + (net (code 17) (name "Net-(C7-Pad2)") (node (ref C7) (pin 2)) - (node (ref P1) (pin 1)) - (node (ref L3) (pin 2))) - (net (code 8) (name +1V2) - (node (ref C15) (pin 1)) - (node (ref C17) (pin 1)) - (node (ref C19) (pin 1)) - (node (ref C21) (pin 1)) - (node (ref C11) (pin 1)) - (node (ref U3) (pin 24)) - (node (ref U3) (pin 84)) - (node (ref U3) (pin 118)) - (node (ref C13) (pin 1)) - (node (ref U3) (pin 59)) - (node (ref C9) (pin 1)) - (node (ref L2) (pin 2))) - (net (code 9) (name VFPGA33) - (node (ref Q1) (pin 1)) - (node (ref U1) (pin 3)) - (node (ref C2) (pin 1)) - (node (ref C28) (pin 1)) - (node (ref U3) (pin 136)) - (node (ref U3) (pin 128)) - (node (ref U3) (pin 112)) - (node (ref C27) (pin 1)) - (node (ref C29) (pin 1))) - (net (code 10) (name "Net-(C4-Pad1)") - (node (ref C4) (pin 1)) - (node (ref U1) (pin 2)) - (node (ref L2) (pin 1)) - (node (ref C5) (pin 1))) - (net (code 11) (name "Net-(R2-Pad2)") - (node (ref U3) (pin 25)) - (node (ref R2) (pin 2))) - (net (code 12) (name "Net-(R3-Pad2)") - (node (ref R3) (pin 2)) - (node (ref U3) (pin 26))) - (net (code 13) (name VSTM33) - (node (ref U4) (pin 19)) - (node (ref U4) (pin 75)) - (node (ref U2) (pin 4)) - (node (ref U4) (pin 22)) - (node (ref U4) (pin 21)) - (node (ref U4) (pin 11)) - (node (ref U4) (pin 50)) - (node (ref U4) (pin 6)) - (node (ref R1) (pin 1)) - (node (ref Q1) (pin 3)) - (node (ref C6) (pin 1)) - (node (ref R4) (pin 1)) - (node (ref R7) (pin 1)) - (node (ref U4) (pin 28)) - (node (ref C20) (pin 1)) - (node (ref C8) (pin 1)) - (node (ref C10) (pin 1)) - (node (ref C12) (pin 1)) - (node (ref C14) (pin 1)) - (node (ref C18) (pin 1)) - (node (ref C16) (pin 1)) - (node (ref C22) (pin 1)) - (node (ref C23) (pin 1)) - (node (ref L1) (pin 2)) - (node (ref U4) (pin 100))) - (net (code 14) (name "Net-(Q2-Pad2)") - (node (ref Q4) (pin 1)) - (node (ref Q2) (pin 2)) - (node (ref R9) (pin 2))) - (net (code 15) (name /powersupply/FPGA_ENABLE_N) - (node (ref R1) (pin 2)) - (node (ref Q1) (pin 2))) - (net (code 16) (name /powersupply/VCAP2) - (node (ref C26) (pin 1)) - (node (ref U4) (pin 73))) - (net (code 17) (name /powersupply/VCAP1) - (node (ref C25) (pin 1)) - (node (ref U4) (pin 49))) + (node (ref L3) (pin 2)) + (node (ref P1) (pin 1))) (net (code 18) (name "Net-(P2-Pad1)") (node (ref U5) (pin 8)) (node (ref P2) (pin 1)) (node (ref Q2) (pin 1))) - (net (code 19) (name /powersupply/CHARGE_ENABLE) - (node (ref R12) (pin 1))) + (net (code 19) (name "Net-(Q2-Pad2)") + (node (ref R9) (pin 2)) + (node (ref Q4) (pin 1)) + (node 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(net (code 185) (name /display/RD) + (node (ref U3) (pin 88)) + (node (ref U6) (pin 11))))) \ No newline at end of file diff --git a/fpgna.sch b/fpgna.sch index d0a2f5e..7500ab1 100644 --- a/fpgna.sch +++ b/fpgna.sch @@ -34,12 +34,13 @@ LIBS:pmic LIBS:specific-powersyms LIBS:regulators LIBS:stm32f4 +LIBS:itead-displays LIBS:fpgna-cache EELAYER 25 0 EELAYER END $Descr A4 11693 8268 encoding utf-8 -Sheet 1 4 +Sheet 1 5 Title "FPGna" Date "" Rev "" @@ -82,4 +83,12 @@ F2 "BOOT1" I R 9300 1300 60 F3 "JTDO" O R 9300 1400 60 F4 "JRST_N" I R 9300 1500 60 $EndSheet +$Sheet +S 4350 3650 2100 1850 +U 56C579FC +F0 "display" 60 +F1 "display.sch" 60 +$EndSheet +Text Notes 7600 4050 0 60 ~ 0 +B5 RAM\nB3 Display $EndSCHEMATC diff --git a/power.sch b/power.sch index fabdf76..2674567 100644 --- a/power.sch +++ b/power.sch @@ -34,12 +34,13 @@ LIBS:pmic LIBS:specific-powersyms LIBS:regulators LIBS:stm32f4 +LIBS:itead-displays LIBS:fpgna-cache EELAYER 25 0 EELAYER END $Descr A4 11693 8268 encoding utf-8 -Sheet 2 4 +Sheet 2 5 Title "FPGna" Date "" Rev "" @@ -63,10 +64,10 @@ F 5 "Makise Kurisu " H -1200 6600 60 0001 C CNN "Author" 1 0 0 -1 $EndComp $Comp -L +1V2 #PWR8 +L +1V2 #PWR6 U 1 1 56323D6C P 950 4850 -F 0 "#PWR8" H 950 4700 50 0001 C CNN +F 0 "#PWR6" H 950 4700 50 0001 C CNN F 1 "+1V2" H 950 4990 50 0000 C CNN F 2 "" H 950 4850 60 0000 C CNN F 3 "" H 950 4850 60 0000 C CNN @@ -74,21 +75,10 @@ F 3 "" H 950 4850 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L +3V3 #PWR3 -U 1 1 56323E2C -P 700 4850 -F 0 "#PWR3" H 700 4700 50 0001 C CNN -F 1 "+3V3" H 700 4990 50 0000 C CNN -F 2 "" H 700 4850 60 0000 C CNN -F 3 "" H 700 4850 60 0000 C CNN - 1 700 4850 - 1 0 0 -1 -$EndComp -$Comp -L GNDD #PWR7 +L GNDD #PWR5 U 1 1 56323EF3 P 900 6250 -F 0 "#PWR7" H 900 6000 50 0001 C CNN +F 0 "#PWR5" H 900 6000 50 0001 C CNN F 1 "GNDD" H 900 6100 50 0000 C CNN F 2 "" H 900 6250 60 0000 C CNN F 3 "" H 900 6250 60 0000 C CNN @@ -129,17 +119,6 @@ F 3 "" H 2700 5150 30 0000 C CNN 1 0 0 -1 $EndComp $Comp -L +3V3 #PWR15 -U 1 1 5632425D -P 2550 4850 -F 0 "#PWR15" H 2550 4700 50 0001 C CNN -F 1 "+3V3" H 2550 4990 50 0000 C CNN -F 2 "" H 2550 4850 60 0000 C CNN -F 3 "" H 2550 4850 60 0000 C CNN - 1 2550 4850 - 1 0 0 -1 -$EndComp -$Comp L C C3 U 1 1 56324973 P 3950 1400 @@ -173,10 +152,10 @@ F 3 "" H 700 2050 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GNDD #PWR10 +L GNDD #PWR8 U 1 1 56325A76 P 1250 2300 -F 0 "#PWR10" H 1250 2050 50 0001 C CNN +F 0 "#PWR8" H 1250 2050 50 0001 C CNN F 1 "GNDD" H 1250 2150 50 0000 C CNN F 2 "" H 1250 2300 60 0000 C CNN F 3 "" H 1250 2300 60 0000 C CNN @@ -206,10 +185,10 @@ F 3 "" H 2400 1850 60 0000 C CNN 0 -1 -1 0 $EndComp $Comp -L +1V2 #PWR18 +L +1V2 #PWR16 U 1 1 56325E26 P 2800 1750 -F 0 "#PWR18" H 2800 1600 50 0001 C CNN +F 0 "#PWR16" H 2800 1600 50 0001 C CNN F 1 "+1V2" H 2800 1890 50 0000 C CNN F 2 "" H 2800 1750 60 0000 C CNN F 3 "" H 2800 1750 60 0000 C CNN @@ -294,10 +273,10 @@ F 3 "" H 2500 4050 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L +1V2 #PWR23 +L +1V2 #PWR12 U 1 1 56326FC5 P 1750 3800 -F 0 "#PWR23" H 1750 3650 50 0001 C CNN +F 0 "#PWR12" H 1750 3650 50 0001 C CNN F 1 "+1V2" H 1750 3940 50 0000 C CNN F 2 "" H 1750 3800 60 0000 C CNN F 3 "" H 1750 3800 60 0000 C CNN @@ -305,10 +284,10 @@ F 3 "" H 1750 3800 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GNDD #PWR24 +L GNDD #PWR13 U 1 1 5632709B P 1750 4300 -F 0 "#PWR24" H 1750 4050 50 0001 C CNN +F 0 "#PWR13" H 1750 4050 50 0001 C CNN F 1 "GNDD" H 1750 4150 50 0000 C CNN F 2 "" H 1750 4300 60 0000 C CNN F 3 "" H 1750 4300 60 0000 C CNN @@ -393,10 +372,10 @@ F 3 "" H 2250 3050 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GNDD #PWR22 +L GNDD #PWR11 U 1 1 5632751F P 1750 3300 -F 0 "#PWR22" H 1750 3050 50 0001 C CNN +F 0 "#PWR11" H 1750 3050 50 0001 C CNN F 1 "GNDD" H 1750 3150 50 0000 C CNN F 2 "" H 1750 3300 60 0000 C CNN F 3 "" H 1750 3300 60 0000 C CNN @@ -437,21 +416,10 @@ F 3 "" H 8700 5300 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L +3V3 #PWR19 -U 1 1 56328BA4 -P 7900 5050 -F 0 "#PWR19" H 7900 4900 50 0001 C CNN -F 1 "+3V3" H 7900 5190 50 0000 C CNN -F 2 "" H 7900 5050 60 0000 C CNN -F 3 "" H 7900 5050 60 0000 C CNN - 1 7900 5050 - 1 0 0 -1 -$EndComp -$Comp -L GNDD #PWR26 +L GNDD #PWR47 U 1 1 56329332 P 9500 5550 -F 0 "#PWR26" H 9500 5300 50 0001 C CNN +F 0 "#PWR47" H 9500 5300 50 0001 C CNN F 1 "GNDD" H 9500 5400 50 0000 C CNN F 2 "" H 9500 5550 60 0000 C CNN F 3 "" H 9500 5550 60 0000 C CNN @@ -472,10 +440,10 @@ F 3 "" V 7450 1050 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GNDD #PWR25 +L GNDD #PWR35 U 1 1 56330682 P 7700 1500 -F 0 "#PWR25" H 7700 1250 50 0001 C CNN +F 0 "#PWR35" H 7700 1250 50 0001 C CNN F 1 "GNDD" H 7700 1350 50 0000 C CNN F 2 "" H 7700 1500 60 0000 C CNN F 3 "" H 7700 1500 60 0000 C CNN @@ -516,10 +484,10 @@ F 3 "" H 7750 3050 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VUSB #PWR20 +L VUSB #PWR31 U 1 1 56C1E573 P 7050 1200 -F 0 "#PWR20" H 7050 1050 50 0001 C CNN +F 0 "#PWR31" H 7050 1050 50 0001 C CNN F 1 "VUSB" H 7068 1374 50 0000 C CNN F 2 "" H 7050 1200 50 0000 C CNN F 3 "" H 7050 1200 50 0000 C CNN @@ -527,10 +495,10 @@ F 3 "" H 7050 1200 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VBAT #PWR35 +L VBAT #PWR40 U 1 1 56C1ED5D P 8600 2750 -F 0 "#PWR35" H 8600 2600 50 0001 C CNN +F 0 "#PWR40" H 8600 2600 50 0001 C CNN F 1 "VBAT" H 8600 2890 50 0000 C CNN F 2 "" H 8600 2750 50 0000 C CNN F 3 "" H 8600 2750 50 0000 C CNN @@ -538,10 +506,10 @@ F 3 "" H 8600 2750 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VUSB #PWR32 +L VUSB #PWR33 U 1 1 56C1F811 P 7500 2750 -F 0 "#PWR32" H 7500 2600 50 0001 C CNN +F 0 "#PWR33" H 7500 2600 50 0001 C CNN F 1 "VUSB" H 7500 2890 50 0000 C CNN F 2 "" H 7500 2750 50 0000 C CNN F 3 "" H 7500 2750 50 0000 C CNN @@ -565,10 +533,10 @@ F 4 "TODO: Verify pinout" H 10127 3150 60 0000 L CNN "TODO" 1 0 0 -1 $EndComp $Comp -L VBAT #PWR45 +L VBAT #PWR51 U 1 1 56C23113 P 9800 2750 -F 0 "#PWR45" H 9800 2600 50 0001 C CNN +F 0 "#PWR51" H 9800 2600 50 0001 C CNN F 1 "VBAT" H 9800 2890 50 0000 C CNN F 2 "" H 9800 2750 50 0000 C CNN F 3 "" H 9800 2750 50 0000 C CNN @@ -576,10 +544,10 @@ F 3 "" H 9800 2750 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GNDD #PWR33 +L GNDD #PWR34 U 1 1 56C23816 P 7500 3950 -F 0 "#PWR33" H 7500 3700 50 0001 C CNN +F 0 "#PWR34" H 7500 3700 50 0001 C CNN F 1 "GNDD" H 7500 3800 50 0000 C CNN F 2 "" H 7500 3950 60 0000 C CNN F 3 "" H 7500 3950 60 0000 C CNN @@ -587,10 +555,10 @@ F 3 "" H 7500 3950 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GNDD #PWR46 +L GNDD #PWR52 U 1 1 56C23E07 P 9800 3950 -F 0 "#PWR46" H 9800 3700 50 0001 C CNN +F 0 "#PWR52" H 9800 3700 50 0001 C CNN F 1 "GNDD" H 9800 3800 50 0000 C CNN F 2 "" H 9800 3950 60 0000 C CNN F 3 "" H 9800 3950 60 0000 C CNN @@ -609,10 +577,10 @@ F 3 "" H 8600 3700 30 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GNDD #PWR36 +L GNDD #PWR41 U 1 1 56C253CE P 8600 3950 -F 0 "#PWR36" H 8600 3700 50 0001 C CNN +F 0 "#PWR41" H 8600 3700 50 0001 C CNN F 1 "GNDD" H 8600 3800 50 0000 C CNN F 2 "" H 8600 3950 60 0000 C CNN F 3 "" H 8600 3950 60 0000 C CNN @@ -631,10 +599,10 @@ F 3 "" H 8600 950 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VBAT #PWR37 +L VBAT #PWR38 U 1 1 56C2D4CD P 8400 950 -F 0 "#PWR37" H 8400 800 50 0001 C CNN +F 0 "#PWR38" H 8400 800 50 0001 C CNN F 1 "VBAT" H 8400 1090 50 0000 C CNN F 2 "" H 8400 950 50 0000 C CNN F 3 "" H 8400 950 50 0000 C CNN @@ -664,10 +632,10 @@ F 3 "" H 8900 1950 30 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GNDD #PWR42 +L GNDD #PWR43 U 1 1 56C307A1 P 8900 2150 -F 0 "#PWR42" H 8900 1900 50 0001 C CNN +F 0 "#PWR43" H 8900 1900 50 0001 C CNN F 1 "GNDD" H 8900 2000 50 0000 C CNN F 2 "" H 8900 2150 60 0000 C CNN F 3 "" H 8900 2150 60 0000 C CNN @@ -686,10 +654,10 @@ F 3 "" V 8900 1050 50 0000 C CNN -1 0 0 1 $EndComp $Comp -L VSYS #PWR5 +L VSYS #PWR20 U 1 1 56C39868 P 3950 1000 -F 0 "#PWR5" H 3950 850 50 0001 C CNN +F 0 "#PWR20" H 3950 850 50 0001 C CNN F 1 "VSYS" H 3950 1140 50 0000 C CNN F 2 "" H 3950 1000 50 0000 C CNN F 3 "" H 3950 1000 50 0000 C CNN @@ -697,10 +665,10 @@ F 3 "" H 3950 1000 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VSYS #PWR44 +L VSYS #PWR46 U 1 1 56C39AFF P 9350 950 -F 0 "#PWR44" H 9350 800 50 0001 C CNN +F 0 "#PWR46" H 9350 800 50 0001 C CNN F 1 "VSYS" H 9350 1090 50 0000 C CNN F 2 "" H 9350 950 50 0000 C CNN F 3 "" H 9350 950 50 0000 C CNN @@ -719,10 +687,10 @@ F 3 "" H 7250 2950 30 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GNDD #PWR38 +L GNDD #PWR42 U 1 1 56C4E595 P 8850 3950 -F 0 "#PWR38" H 8850 3700 50 0001 C CNN +F 0 "#PWR42" H 8850 3700 50 0001 C CNN F 1 "GNDD" H 8850 3800 50 0000 C CNN F 2 "" H 8850 3950 60 0000 C CNN F 3 "" H 8850 3950 60 0000 C CNN @@ -730,10 +698,10 @@ F 3 "" H 8850 3950 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VUSB #PWR40 +L VUSB #PWR44 U 1 1 56C4F548 P 9200 2750 -F 0 "#PWR40" H 9200 2600 50 0001 C CNN +F 0 "#PWR44" H 9200 2600 50 0001 C CNN F 1 "VUSB" H 9200 2890 50 0000 C CNN F 2 "" H 9200 2750 50 0000 C CNN F 3 "" H 9200 2750 50 0000 C CNN @@ -741,10 +709,10 @@ F 3 "" H 9200 2750 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GNDD #PWR41 +L GNDD #PWR45 U 1 1 56C4FA15 P 9200 3950 -F 0 "#PWR41" H 9200 3700 50 0001 C CNN +F 0 "#PWR45" H 9200 3700 50 0001 C CNN F 1 "GNDD" H 9200 3800 50 0000 C CNN F 2 "" H 9200 3950 60 0000 C CNN F 3 "" H 9200 3950 60 0000 C CNN @@ -785,10 +753,10 @@ F 3 "" H 9550 3750 30 0000 C CNN -1 0 0 1 $EndComp $Comp -L GNDD #PWR43 +L GNDD #PWR48 U 1 1 56C59A2E P 9550 3950 -F 0 "#PWR43" H 9550 3700 50 0001 C CNN +F 0 "#PWR48" H 9550 3700 50 0001 C CNN F 1 "GNDD" H 9550 3800 50 0000 C CNN F 2 "" H 9550 3950 60 0000 C CNN F 3 "" H 9550 3950 60 0000 C CNN @@ -820,10 +788,10 @@ F 3 "" H 9700 1550 30 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VSYS #PWR30 +L VSYS #PWR49 U 1 1 56C208D6 P 9700 950 -F 0 "#PWR30" H 9700 800 50 0001 C CNN +F 0 "#PWR49" H 9700 800 50 0001 C CNN F 1 "VSYS" H 9700 1090 50 0000 C CNN F 2 "" H 9700 950 50 0000 C CNN F 3 "" H 9700 950 50 0000 C CNN @@ -831,10 +799,10 @@ F 3 "" H 9700 950 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GNDD #PWR31 +L GNDD #PWR50 U 1 1 56C20CEB P 9700 1800 -F 0 "#PWR31" H 9700 1550 50 0001 C CNN +F 0 "#PWR50" H 9700 1550 50 0001 C CNN F 1 "GNDD" H 9700 1650 50 0000 C CNN F 2 "" H 9700 1800 60 0000 C CNN F 3 "" H 9700 1800 60 0000 C CNN @@ -877,10 +845,10 @@ F 3 "" H 4450 1500 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GNDD #PWR6 +L GNDD #PWR21 U 1 1 56C35DE1 P 3950 1850 -F 0 "#PWR6" H 3950 1600 50 0001 C CNN +F 0 "#PWR21" H 3950 1600 50 0001 C CNN F 1 "GNDD" H 3950 1700 50 0000 C CNN F 2 "" H 3950 1850 60 0000 C CNN F 3 "" H 3950 1850 60 0000 C CNN @@ -888,10 +856,10 @@ F 3 "" H 3950 1850 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GNDD #PWR12 +L GNDD #PWR24 U 1 1 56C35F4F P 4700 1850 -F 0 "#PWR12" H 4700 1600 50 0001 C CNN +F 0 "#PWR24" H 4700 1600 50 0001 C CNN F 1 "GNDD" H 4700 1700 50 0000 C CNN F 2 "" H 4700 1850 60 0000 C CNN F 3 "" H 4700 1850 60 0000 C CNN @@ -899,10 +867,10 @@ F 3 "" H 4700 1850 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GNDD #PWR9 +L GNDD #PWR23 U 1 1 56C360EB P 4350 1850 -F 0 "#PWR9" H 4350 1600 50 0001 C CNN +F 0 "#PWR23" H 4350 1600 50 0001 C CNN F 1 "GNDD" H 4350 1700 50 0000 C CNN F 2 "" H 4350 1850 60 0000 C CNN F 3 "" H 4350 1850 60 0000 C CNN @@ -921,10 +889,10 @@ F 3 "" V 5050 1450 50 0000 C CNN 0 1 1 0 $EndComp $Comp -L GNDD #PWR13 +L GNDD #PWR27 U 1 1 56C2CFDF P 5050 1850 -F 0 "#PWR13" H 5050 1600 50 0001 C CNN +F 0 "#PWR27" H 5050 1600 50 0001 C CNN F 1 "GNDD" H 5050 1700 50 0000 C CNN F 2 "" H 5050 1850 60 0000 C CNN F 3 "" H 5050 1850 60 0000 C CNN @@ -954,10 +922,10 @@ F 3 "" H 5800 1500 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GNDD #PWR16 +L GNDD #PWR29 U 1 1 56C2E498 P 5800 1850 -F 0 "#PWR16" H 5800 1600 50 0001 C CNN +F 0 "#PWR29" H 5800 1600 50 0001 C CNN F 1 "GNDD" H 5800 1700 50 0000 C CNN F 2 "" H 5800 1850 60 0000 C CNN F 3 "" H 5800 1850 60 0000 C CNN @@ -976,10 +944,10 @@ F 3 "" H 3700 1400 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GNDD #PWR1 +L GNDD #PWR18 U 1 1 56C2F49B P 3700 1850 -F 0 "#PWR1" H 3700 1600 50 0001 C CNN +F 0 "#PWR18" H 3700 1600 50 0001 C CNN F 1 "GNDD" H 3700 1700 50 0000 C CNN F 2 "" H 3700 1850 60 0000 C CNN F 3 "" H 3700 1850 60 0000 C CNN @@ -987,10 +955,10 @@ F 3 "" H 3700 1850 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VSTM33 #PWR17 +L VSTM33 #PWR30 U 1 1 56C326BF P 5900 1050 -F 0 "#PWR17" H 5900 900 50 0001 C CNN +F 0 "#PWR30" H 5900 900 50 0001 C CNN F 1 "VSTM33" H 5900 1190 50 0000 C CNN F 2 "" H 5900 1050 50 0000 C CNN F 3 "" H 5900 1050 50 0000 C CNN @@ -1020,10 +988,10 @@ F 3 "http://www.digikey.com/product-search/en/discrete-semiconductor-products/fe 0 1 -1 0 $EndComp $Comp -L VSTM33 #PWR4 +L VSTM33 #PWR1 U 1 1 56C36219 P 700 950 -F 0 "#PWR4" H 700 800 50 0001 C CNN +F 0 "#PWR1" H 700 800 50 0001 C CNN F 1 "VSTM33" H 700 1090 50 0000 C CNN F 2 "" H 700 950 50 0000 C CNN F 3 "" H 700 950 50 0000 C CNN @@ -1031,10 +999,10 @@ F 3 "" H 700 950 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VFPGA33 #PWR11 +L VFPGA33 #PWR9 U 1 1 56C36471 P 1400 950 -F 0 "#PWR11" H 1400 800 50 0001 C CNN +F 0 "#PWR9" H 1400 800 50 0001 C CNN F 1 "VFPGA33" H 1400 1090 50 0000 C CNN F 2 "" H 1400 950 50 0000 C CNN F 3 "" H 1400 950 50 0000 C CNN @@ -1089,10 +1057,10 @@ F 3 "" H 3950 4200 60 0000 C CNN $EndComp NoConn ~ 7550 3250 $Comp -L GND #PWR34 +L GND #PWR28 U 1 1 56C4E388 P 5150 5200 -F 0 "#PWR34" H 5150 4950 50 0001 C CNN +F 0 "#PWR28" H 5150 4950 50 0001 C CNN F 1 "GND" H 5158 5026 50 0000 C CNN F 2 "" H 5150 5200 50 0000 C CNN F 3 "" H 5150 5200 50 0000 C CNN @@ -1100,10 +1068,10 @@ F 3 "" H 5150 5200 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VSTM33 #PWR29 +L VSTM33 #PWR32 U 1 1 56C54669 P 7250 2750 -F 0 "#PWR29" H 7250 2600 50 0001 C CNN +F 0 "#PWR32" H 7250 2600 50 0001 C CNN F 1 "VSTM33" H 7250 2890 50 0000 C CNN F 2 "" H 7250 2750 50 0000 C CNN F 3 "" H 7250 2750 50 0000 C CNN @@ -1111,10 +1079,10 @@ F 3 "" H 7250 2750 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VSTM33 #PWR28 +L VSTM33 #PWR22 U 1 1 56C58A5C P 4200 3450 -F 0 "#PWR28" H 4200 3300 50 0001 C CNN +F 0 "#PWR22" H 4200 3300 50 0001 C CNN F 1 "VSTM33" H 4200 3590 50 0000 C CNN F 2 "" H 4200 3450 50 0000 C CNN F 3 "" H 4200 3450 50 0000 C CNN @@ -1144,10 +1112,10 @@ F 3 "" H 3750 5000 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GND #PWR27 +L GND #PWR19 U 1 1 56C5D446 P 3850 5200 -F 0 "#PWR27" H 3850 4950 50 0001 C CNN +F 0 "#PWR19" H 3850 4950 50 0001 C CNN F 1 "GND" H 3858 5026 50 0000 C CNN F 2 "" H 3850 5200 50 0000 C CNN F 3 "" H 3850 5200 50 0000 C CNN @@ -1170,10 +1138,10 @@ VCAP1 Text Label 3950 4800 0 60 ~ 0 VCAP2 $Comp -L VFPGA33 #PWR? +L VFPGA33 #PWR10 U 1 1 56C4A0C6 P 1750 2800 -F 0 "#PWR?" H 1750 2650 50 0001 C CNN +F 0 "#PWR10" H 1750 2650 50 0001 C CNN F 1 "VFPGA33" H 1750 2940 50 0000 C CNN F 2 "" H 1750 2800 50 0000 C CNN F 3 "" H 1750 2800 50 0000 C CNN @@ -1181,10 +1149,10 @@ F 3 "" H 1750 2800 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L C C? +L C C33 U 1 1 56C5067D P 4200 2700 -F 0 "C?" H 4225 2800 50 0000 L CNN +F 0 "C33" H 4225 2800 50 0000 L CNN F 1 "100n" H 4225 2600 50 0000 L CNN F 2 "" H 4238 2550 30 0001 C CNN F 3 "" H 4200 2700 60 0000 C CNN @@ -1192,10 +1160,10 @@ F 3 "" H 4200 2700 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L C C? +L C C34 U 1 1 56C50683 P 4450 2700 -F 0 "C?" H 4475 2800 50 0000 L CNN +F 0 "C34" H 4475 2800 50 0000 L CNN F 1 "100n" H 4475 2600 50 0000 L CNN F 2 "" H 4488 2550 30 0001 C CNN F 3 "" H 4450 2700 60 0000 C CNN @@ -1203,10 +1171,10 @@ F 3 "" H 4450 2700 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L C C? +L C C35 U 1 1 56C50689 P 4700 2700 -F 0 "C?" H 4725 2800 50 0000 L CNN +F 0 "C35" H 4725 2800 50 0000 L CNN F 1 "100n" H 4725 2600 50 0000 L CNN F 2 "" H 4738 2550 30 0001 C CNN F 3 "" H 4700 2700 60 0000 C CNN @@ -1214,10 +1182,10 @@ F 3 "" H 4700 2700 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L C C? +L C C36 U 1 1 56C5068F P 4950 2700 -F 0 "C?" H 4975 2800 50 0000 L CNN +F 0 "C36" H 4975 2800 50 0000 L CNN F 1 "100n" H 4975 2600 50 0000 L CNN F 2 "" H 4988 2550 30 0001 C CNN F 3 "" H 4950 2700 60 0000 C CNN @@ -1225,10 +1193,10 @@ F 3 "" H 4950 2700 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L C C? +L C C37 U 1 1 56C50695 P 5200 2700 -F 0 "C?" H 5225 2800 50 0000 L CNN +F 0 "C37" H 5225 2800 50 0000 L CNN F 1 "100n" H 5225 2600 50 0000 L CNN F 2 "" H 5238 2550 30 0001 C CNN F 3 "" H 5200 2700 60 0000 C CNN @@ -1236,10 +1204,10 @@ F 3 "" H 5200 2700 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L C C? +L C C38 U 1 1 56C5069B P 5450 2700 -F 0 "C?" H 5475 2800 50 0000 L CNN +F 0 "C38" H 5475 2800 50 0000 L CNN F 1 "100n" H 5475 2600 50 0000 L CNN F 2 "" H 5488 2550 30 0001 C CNN F 3 "" H 5450 2700 60 0000 C CNN @@ -1247,10 +1215,10 @@ F 3 "" H 5450 2700 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L C C? +L C C39 U 1 1 56C506A1 P 5700 2700 -F 0 "C?" H 5725 2800 50 0000 L CNN +F 0 "C39" H 5725 2800 50 0000 L CNN F 1 "100n" H 5725 2600 50 0000 L CNN F 2 "" H 5738 2550 30 0001 C CNN F 3 "" H 5700 2700 60 0000 C CNN @@ -1258,10 +1226,10 @@ F 3 "" H 5700 2700 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L GNDD #PWR? +L GNDD #PWR26 U 1 1 56C506AD P 4700 2950 -F 0 "#PWR?" H 4700 2700 50 0001 C CNN +F 0 "#PWR26" H 4700 2700 50 0001 C CNN F 1 "GNDD" H 4700 2800 50 0000 C CNN F 2 "" H 4700 2950 60 0000 C CNN F 3 "" H 4700 2950 60 0000 C CNN @@ -1269,10 +1237,10 @@ F 3 "" H 4700 2950 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L VSTM33 #PWR? +L VSTM33 #PWR25 U 1 1 56C509AA P 4700 2450 -F 0 "#PWR?" H 4700 2300 50 0001 C CNN +F 0 "#PWR25" H 4700 2300 50 0001 C CNN F 1 "VSTM33" H 4700 2590 50 0000 C CNN F 2 "" H 4700 2450 50 0000 C CNN F 3 "" H 4700 2450 50 0000 C CNN @@ -1280,10 +1248,10 @@ F 3 "" H 4700 2450 50 0000 C CNN 1 0 0 -1 $EndComp $Comp -L C C? +L C C32 U 1 1 56C50D95 P 3950 2700 -F 0 "C?" H 3975 2800 50 0000 L CNN +F 0 "C32" H 3975 2800 50 0000 L CNN F 1 "100n" H 3975 2600 50 0000 L CNN F 2 "" H 3988 2550 30 0001 C CNN F 3 "" H 3950 2700 60 0000 C CNN @@ -1291,10 +1259,10 @@ F 3 "" H 3950 2700 60 0000 C CNN 1 0 0 -1 $EndComp $Comp -L C C? +L C C31 U 1 1 56C52C65 P 3700 2700 -F 0 "C?" H 3725 2800 50 0000 L CNN +F 0 "C31" H 3725 2800 50 0000 L CNN F 1 "10u" H 3725 2600 50 0000 L CNN F 2 "" H 3738 2550 30 0001 C CNN F 3 "" H 3700 2700 60 0000 C CNN @@ -1711,14 +1679,14 @@ Connection ~ 4200 2550 Connection ~ 3950 2550 Connection ~ 3950 2850 Wire Notes Line - 3150 600 3150 7200 + 3150 600 3150 7600 Wire Notes Line - 6250 550 6250 7150 + 6250 550 6250 7600 $Comp -L R R? +L R R15 U 1 1 56C5AB35 P 7950 1250 -F 0 "R?" V 8030 1250 50 0000 C CNN +F 0 "R15" V 8030 1250 50 0000 C CNN F 1 "0" V 7950 1250 50 0000 C CNN F 2 "" V 7880 1250 30 0001 C CNN F 3 "" H 7950 1250 30 0000 C CNN @@ -1730,10 +1698,10 @@ Wire Wire Line Wire Wire Line 7950 1050 7900 1050 $Comp -L GNDD #PWR? +L GNDD #PWR37 U 1 1 56C5AF1C P 7950 1500 -F 0 "#PWR?" H 7950 1250 50 0001 C CNN +F 0 "#PWR37" H 7950 1250 50 0001 C CNN F 1 "GNDD" H 7950 1350 50 0000 C CNN F 2 "" H 7950 1500 60 0000 C CNN F 3 "" H 7950 1500 60 0000 C CNN @@ -1742,4 +1710,169 @@ F 3 "" H 7950 1500 60 0000 C CNN $EndComp Wire Wire Line 7950 1500 7950 1400 +$Comp +L ITDB02-3.2WD U6 +U 1 1 56C57ED6 +P 2200 6750 +F 0 "U6" H 2475 6937 60 0000 C CNN +F 1 "ITDB02-3.2WD" H 2475 6831 60 0000 C CNN +F 2 "itead-display:ITDB02-3.2WD" H 2200 6750 60 0001 C CNN +F 3 "" H 2200 6750 60 0000 C CNN + 1 2200 6750 + 1 0 0 -1 +$EndComp +$Comp +L C C30 +U 1 1 56C58841 +P 800 7000 +F 0 "C30" H 825 7100 50 0000 L CNN +F 1 "2.2u" H 825 6900 50 0000 L CNN +F 2 "" H 838 6850 30 0001 C CNN +F 3 "" H 800 7000 60 0000 C CNN + 1 800 7000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 600 6850 2000 6850 +$Comp +L GNDD #PWR4 +U 1 1 56C58F25 +P 800 7300 +F 0 "#PWR4" H 800 7050 50 0001 C CNN +F 1 "GNDD" H 800 7150 50 0000 C CNN +F 2 "" H 800 7300 60 0000 C CNN +F 3 "" H 800 7300 60 0000 C CNN + 1 800 7300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 800 7300 800 7150 +Wire Wire Line + 2950 6850 3000 6850 +Wire Wire Line + 3000 6850 3000 7300 +$Comp +L GNDD #PWR17 +U 1 1 56C592D8 +P 3000 7300 +F 0 "#PWR17" H 3000 7050 50 0001 C CNN +F 1 "GNDD" H 3000 7150 50 0000 C CNN +F 2 "" H 3000 7300 60 0000 C CNN +F 3 "" H 3000 7300 60 0000 C CNN + 1 3000 7300 + 1 0 0 -1 +$EndComp +$Comp +L Q_PMOS_DGS Q5 +U 1 1 56C5D295 +P 1400 7100 +F 0 "Q5" V 1600 7100 50 0000 C CNN +F 1 "3.3LogicLv-P" V 1350 7450 50 0000 C CNN +F 2 "" H 1600 7200 50 0001 C CNN +F 3 "http://www.digikey.com/product-search/en/discrete-semiconductor-products/fets-single/1376381" H 1400 7100 50 0001 C CNN + 1 1400 7100 + 0 1 -1 0 +$EndComp +Wire Wire Line + 1600 7000 1650 7000 +$Comp +L VFPGA33 #PWR7 +U 1 1 56C61112 +P 1000 6800 +F 0 "#PWR7" H 1000 6650 50 0001 C CNN +F 1 "VFPGA33" H 1018 6974 50 0000 C CNN +F 2 "" H 1000 6800 50 0000 C CNN +F 3 "" H 1000 6800 50 0000 C CNN + 1 1000 6800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1400 7300 1400 7350 +Wire Wire Line + 1350 7350 1600 7350 +Text HLabel 1600 7350 2 60 Input ~ 0 +BACKLIGHT_EN_N +$Comp +L R R13 +U 1 1 56C641C3 +P 1200 7350 +F 0 "R13" V 1280 7350 50 0000 C CNN +F 1 "10k" V 1200 7350 50 0000 C CNN +F 2 "" V 1130 7350 30 0001 C CNN +F 3 "" H 1200 7350 30 0000 C CNN + 1 1200 7350 + 0 1 1 0 +$EndComp +Connection ~ 1400 7350 +Wire Wire Line + 1000 7350 1050 7350 +Wire Wire Line + 1000 6800 1000 7350 +Wire Wire Line + 1000 7000 1200 7000 +Connection ~ 1000 7000 +Connection ~ 1000 6850 +$Comp +L R R14 +U 1 1 56C66E4A +P 1800 7000 +F 0 "R14" V 1880 7000 50 0000 C CNN +F 1 "0" V 1800 7000 50 0000 C CNN +F 2 "" V 1730 7000 30 0001 C CNN +F 3 "" H 1800 7000 30 0000 C CNN + 1 1800 7000 + 0 1 1 0 +$EndComp +Wire Wire Line + 2000 7000 1950 7000 +$Comp +L VFPGA33 #PWR15 +U 1 1 56C69ECC +P 2550 4850 +F 0 "#PWR15" H 2550 4700 50 0001 C CNN +F 1 "VFPGA33" H 2568 5024 50 0000 C CNN +F 2 "" H 2550 4850 50 0000 C CNN +F 3 "" H 2550 4850 50 0000 C CNN + 1 2550 4850 + 1 0 0 -1 +$EndComp +$Comp +L VFPGA33 #PWR3 +U 1 1 56C69FA9 +P 700 4850 +F 0 "#PWR3" H 700 4700 50 0001 C CNN +F 1 "VFPGA33" H 718 5024 50 0000 C CNN +F 2 "" H 700 4850 50 0000 C CNN +F 3 "" H 700 4850 50 0000 C CNN + 1 700 4850 + 1 0 0 -1 +$EndComp +$Comp +L VFPGA33 #PWR36 +U 1 1 56C6AF05 +P 7900 5050 +F 0 "#PWR36" H 7900 4900 50 0001 C CNN +F 1 "VFPGA33" H 7918 5224 50 0000 C CNN +F 2 "" H 7900 5050 50 0000 C CNN +F 3 "" H 7900 5050 50 0000 C CNN + 1 7900 5050 + 1 0 0 -1 +$EndComp +$Comp +L C C42 +U 1 1 56C5BFA7 +P 600 7000 +F 0 "C42" H 625 7100 50 0000 L CNN +F 1 "100n" H 625 6900 50 0000 L CNN +F 2 "" H 638 6850 30 0001 C CNN +F 3 "" H 600 7000 60 0000 C CNN + 1 600 7000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 600 7150 600 7200 +Wire Wire Line + 600 7200 800 7200 +Connection ~ 800 7200 +Connection ~ 800 6850 $EndSCHEMATC