Commit Graph

7 Commits

Author SHA1 Message Date
4d8add7ebe Redesign of SDRAM IF 2016-02-19 14:20:06 +01:00
9eb3271030 SDRAM schematic + first layout try 2016-02-19 11:53:31 +01:00
7ea01f4abb Gneowmeow 2016-02-17 20:30:12 +01:00
4d8213d31b Wired FSMC on STM side 2016-02-17 10:41:34 +01:00
eaf38e8c02 Started design of SMPS for 3.3V 2016-02-15 18:20:08 +01:00
69d2d949e4 Power battery stuff 2016-02-15 15:02:54 +01:00
533ebe19f9 Power supply 2015-10-29 20:36:54 +01:00