EESchema Schematic File Version 2 LIBS:fpgna-rescue LIBS:power LIBS:device LIBS:transistors LIBS:conn LIBS:linear LIBS:regul LIBS:74xx LIBS:cmos4000 LIBS:adc-dac LIBS:memory LIBS:xilinx LIBS:microcontrollers LIBS:dsp LIBS:microchip LIBS:analog_switches LIBS:motorola LIBS:texas LIBS:intel LIBS:audio LIBS:interface LIBS:digital-audio LIBS:philips LIBS:display LIBS:cypress LIBS:siliconi LIBS:opto LIBS:atmel LIBS:contrib LIBS:valves LIBS:Oscillators LIBS:lattice LIBS:pmic LIBS:specific-powersyms LIBS:regulators LIBS:stm32f4 LIBS:itead-displays LIBS:ram LIBS:fpgna-cache EELAYER 25 0 EELAYER END $Descr A4 11693 8268 encoding utf-8 Sheet 1 8 Title "FPGna" Date "" Rev "" Comp "Shimatta" Comment1 "" Comment2 "" Comment3 "" Comment4 "" $EndDescr $Sheet S 1100 1700 2050 1400 U 563244F7 F0 "powersupply" 60 F1 "power.sch" 60 F2 "CHG_ACTIVE_N" O R 3150 2050 60 F3 "USB_PRESENT_N" O R 3150 1950 60 F4 "CHARGE_ENABLE" I R 3150 2150 60 F5 "SYS_VOLTAGE" O R 3150 2350 60 F6 "CLK_50M" O L 1100 1950 60 F7 "FPGA_ENABLE_N" I R 3150 2450 60 $EndSheet $Sheet S 3900 3750 2250 1800 U 56337D98 F0 "debug" 60 F1 "debug.sch" 60 F2 "JTDI" O R 6150 3950 60 F3 "JTMS" O R 6150 4050 60 F4 "JTDO" I R 6150 4150 60 F5 "JTCK" O R 6150 4250 60 F6 "JRST_N" I R 6150 4350 60 F7 "BOOT1" O R 6150 4550 60 $EndSheet $Sheet S 6300 1100 2050 2150 U 56C43C85 F0 "FSMC" 60 F1 "FSMC.sch" 60 F2 "BOOT1" I L 6300 1200 60 F3 "JTDO" O L 6300 1300 60 F4 "JRST_N" I L 6300 1400 60 F5 "BL0_N" O R 8350 2350 60 F6 "BL1_N" O R 8350 2450 60 F7 "A[19..23]" O R 8350 2550 60 F8 "SDIO_CMD" O L 6300 1800 60 F9 "T_CS" O R 8350 1350 60 F10 "T_CLK" O R 8350 1250 60 F11 "T_DOUT" I R 8350 1550 60 F12 "T_DIN" O R 8350 1450 60 $EndSheet $Sheet S 8500 1100 1750 800 U 56C579FC F0 "display" 60 F1 "display.sch" 60 F2 "T_CLK" I L 8500 1250 60 F3 "T_CS" I L 8500 1350 60 F4 "T_DIN" I L 8500 1450 60 F5 "T_DOUT" O L 8500 1550 60 F6 "T_BUSY" O R 10250 1350 60 F7 "T_IRQ" O R 10250 1250 60 $EndSheet $Sheet S 8600 2200 1300 450 U 56C6F777 F0 "sdram" 60 F1 "sdram.sch" 60 F2 "A[19..23]" I L 8600 2550 60 F3 "BL0_N" I L 8600 2350 60 F4 "BL1_N" I L 8600 2450 60 $EndSheet Wire Bus Line 8600 2550 8350 2550 Wire Wire Line 8350 2350 8600 2350 Wire Wire Line 8600 2450 8350 2450 $Sheet S 950 3750 2450 1500 U 56C86141 F0 "userif" 60 F1 "userif.sch" 60 $EndSheet $Sheet S 4600 1650 1400 800 U 56C7DD81 F0 "sdcard" 60 F1 "sdcard.sch" 60 F2 "SDIO_CMD" I R 6000 1800 60 F3 "T_IRQ" I L 4600 1800 60 F4 "T_BUSY" I L 4600 1900 60 $EndSheet Wire Wire Line 8350 1250 8500 1250 Wire Wire Line 8500 1350 8350 1350 Wire Wire Line 8350 1450 8500 1450 Wire Wire Line 8500 1550 8350 1550 Wire Wire Line 6000 1800 6300 1800 Wire Wire Line 10250 1250 10350 1250 Wire Wire Line 10350 1250 10350 950 Wire Wire Line 10350 950 4500 950 Wire Wire Line 4500 950 4500 1800 Wire Wire Line 4500 1800 4600 1800 Wire Wire Line 4600 1900 4450 1900 Wire Wire Line 4450 1900 4450 900 Wire Wire Line 4450 900 10400 900 Wire Wire Line 10400 900 10400 1350 Wire Wire Line 10400 1350 10250 1350 $EndSCHEMATC