fpgna/debug.sch
2015-10-29 20:36:54 +01:00

269 lines
5.2 KiB
Plaintext

EESchema Schematic File Version 2
LIBS:power
LIBS:device
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:74xx
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:lattice
LIBS:Oscillators
LIBS:fpgna-cache
EELAYER 25 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
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Title ""
Date ""
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Comment3 ""
Comment4 ""
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F 0 "P?" H 125 -925 50 0000 C CNN
F 1 "USB_OTG" H -200 -600 50 0000 C CNN
F 2 "" V -250 -900 60 0000 C CNN
F 3 "" V -250 -900 60 0000 C CNN
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$EndComp
$Comp
L GNDD #PWR?
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F 0 "#PWR?" H 0 -700 50 0001 C CNN
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F 3 "" H 0 -450 60 0000 C CNN
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$EndComp
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F 1 "+5V" H -650 -610 50 0000 C CNN
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F 3 "" H -650 -750 60 0000 C CNN
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$EndComp
$Comp
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Wire Wire Line
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Wire Wire Line
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$Comp
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$EndComp
$Comp
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F 3 "http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/LatticeXP2/LatticeXP2FamilyDataSheet.pdf" H 1850 3050 60 0001 C CNN
F 4 "1.0" H -750 2950 60 0001 C CNN "Version"
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Wire Wire Line
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$EndComp
$Comp
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$Comp
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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$EndSCHEMATC