86 lines
1.4 KiB
Plaintext
86 lines
1.4 KiB
Plaintext
EESchema Schematic File Version 2
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LIBS:power
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LIBS:device
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LIBS:transistors
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LIBS:conn
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LIBS:linear
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LIBS:regul
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LIBS:74xx
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LIBS:cmos4000
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LIBS:adc-dac
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LIBS:memory
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LIBS:xilinx
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LIBS:microcontrollers
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LIBS:dsp
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LIBS:microchip
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LIBS:analog_switches
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LIBS:motorola
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LIBS:texas
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LIBS:intel
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LIBS:audio
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LIBS:interface
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LIBS:digital-audio
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LIBS:philips
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LIBS:display
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LIBS:cypress
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LIBS:siliconi
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LIBS:opto
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LIBS:atmel
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LIBS:contrib
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LIBS:valves
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LIBS:Oscillators
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LIBS:lattice
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LIBS:pmic
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LIBS:specific-powersyms
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LIBS:regulators
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LIBS:stm32f4
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LIBS:fpgna-cache
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EELAYER 25 0
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EELAYER END
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$Descr A4 11693 8268
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encoding utf-8
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Sheet 1 4
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Title "FPGna"
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Date ""
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Rev ""
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Comp "Shimatta"
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Comment1 ""
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Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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$Sheet
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S 1100 1700 2050 1400
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U 563244F7
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F0 "powersupply" 60
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F1 "power.sch" 60
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F2 "CHG_ACTIVE_N" O R 3150 2050 60
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F3 "USB_PRESENT_N" O R 3150 1950 60
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F4 "CHARGE_ENABLE" I R 3150 2150 60
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F5 "SYS_VOLTAGE" O R 3150 2350 60
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F6 "CLK_50M" O L 1100 1950 60
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F7 "FPGA_ENABLE_N" I R 3150 2450 60
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$EndSheet
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$Sheet
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S 4450 1100 2250 1800
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U 56337D98
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F0 "debug" 60
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F1 "debug.sch" 60
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F2 "JTDI" O R 6700 1300 60
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F3 "JTMS" O R 6700 1400 60
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F4 "JTDO" I R 6700 1500 60
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F5 "JTCK" O R 6700 1600 60
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F6 "JRST_N" I R 6700 1700 60
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F7 "BOOT1" O R 6700 1900 60
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$EndSheet
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$Sheet
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S 7250 1100 2050 2150
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U 56C43C85
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F0 "FSMC" 60
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F1 "FSMC.sch" 60
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F2 "BOOT1" I R 9300 1300 60
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F3 "JTDO" O R 9300 1400 60
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F4 "JRST_N" I R 9300 1500 60
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$EndSheet
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$EndSCHEMATC
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