fpgna/libs/specific-powersyms.lib
2016-02-16 08:25:23 +01:00

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EESchema-LIBRARY Version 2.3
#encoding utf-8
#
# VBAT
#
DEF VBAT #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "VBAT" 0 140 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X VBAT 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# VFPGA33
#
DEF VFPGA33 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "VFPGA33" 0 140 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X VFPGA33 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# VSTM33
#
DEF VSTM33 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "VSTM33" 0 140 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X VSTM33 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# VSYS
#
DEF VSYS #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "VSYS" 0 140 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X VSYS 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# VUSB
#
DEF VUSB #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "VUSB" 0 140 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X VUSB 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library