24 lines
1.0 KiB
VHDL
24 lines
1.0 KiB
VHDL
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-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.10.0.111.2
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-- Module Version: 7.5
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-- Sun Apr 22 17:34:06 2018
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-- parameterized module component declaration
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component gram0
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port (DataInA: in std_logic_vector(8 downto 0);
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DataInB: in std_logic_vector(8 downto 0);
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AddressA: in std_logic_vector(12 downto 0);
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AddressB: in std_logic_vector(12 downto 0);
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ClockA: in std_logic; ClockB: in std_logic;
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ClockEnA: in std_logic; ClockEnB: in std_logic;
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WrA: in std_logic; WrB: in std_logic; ResetA: in std_logic;
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ResetB: in std_logic; QA: out std_logic_vector(8 downto 0);
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QB: out std_logic_vector(8 downto 0));
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end component;
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-- parameterized module component instance
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__ : gram0
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port map (DataInA(8 downto 0)=>__, DataInB(8 downto 0)=>__, AddressA(12 downto 0)=>__,
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AddressB(12 downto 0)=>__, ClockA=>__, ClockB=>__, ClockEnA=>__,
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ClockEnB=>__, WrA=>__, WrB=>__, ResetA=>__, ResetB=>__, QA(8 downto 0)=>__,
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QB(8 downto 0)=>__);
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