display:fpga: Fix project file

master
Markus Koch 2020-05-10 20:40:08 +02:00
parent eebd6e5517
commit 3ae19dc20a
2 changed files with 8 additions and 2 deletions

View File

@ -2,7 +2,7 @@
<BaliProject version="3.2" title="lmg6202" device="LCMXO2-1200HC-5SG32C" default_implementation="impl1">
<Options/>
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
<Options def_top="design.top" top="design.top"/>
<Options def_top="design.top" lib="design" top="design.top"/>
<Source name="../ip/gram0/gram0.ipx" type="IPX_Module" type_short="IPX">
<Options/>
</Source>
@ -18,6 +18,12 @@
<Source name="../design/spi_if.vhd" type="VHDL" type_short="VHDL">
<Options lib="design"/>
</Source>
<Source name="../ip/pll0/pll0.vhd" type="VHDL" type_short="VHDL">
<Options lib="ip"/>
</Source>
<Source name="../generics/synchronizer.vhd" type="VHDL" type_short="VHDL">
<Options lib="generics"/>
</Source>
<Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
<Options/>
</Source>

View File

@ -190,7 +190,7 @@
<Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
<Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
<Property name="PROP_SYN_UseLPF" value="True" time="0"/>
<Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
<Property name="PROP_SYN_VHDL2008" value="True" time="0"/>
<Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
<Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
<Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>