display:fpga: update I/O constraints for new hardware
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@ -3,12 +3,7 @@ BLOCK ASYNCPATHS ;
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LOCATE COMP "clk_hw" SITE "28" ;
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LOCATE COMP "rst_hw" SITE "23" ;
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IOBUF PORT "rst_hw" PULLMODE=UP IO_TYPE=LVCMOS33 ;
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LOCATE COMP "lcd_data[0]" SITE "14" ;
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LOCATE COMP "lcd_data[1]" SITE "13" ;
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LOCATE COMP "lcd_clp" SITE "10" ;
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LOCATE COMP "lcd_load" SITE "9" ;
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LOCATE COMP "lcd_frp" SITE "8" ;
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LOCATE COMP "lcd_frmb" SITE "5" ;
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LOCATE COMP "lcd_clp" SITE "9" ;
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IOBUF ALLPORTS IO_TYPE=LVCMOS33 ;
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IOBUF PORT "clk_hw" IO_TYPE=LVCMOS33 ;
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IOBUF PORT "lcd_clp" IO_TYPE=LVCMOS33 ;
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@ -19,15 +14,19 @@ IOBUF PORT "lcd_data[3]" IO_TYPE=LVCMOS33 ;
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IOBUF PORT "lcd_frmb" IO_TYPE=LVCMOS33 ;
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IOBUF PORT "lcd_frp" IO_TYPE=LVCMOS33 ;
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IOBUF PORT "lcd_load" IO_TYPE=LVCMOS33 ;
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LOCATE COMP "lcd_data[2]" SITE "12" ;
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LOCATE COMP "lcd_data[3]" SITE "11" ;
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FREQUENCY NET "clk_hw_c" 12.000000 MHz ;
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IOBUF PORT "spi_cs_n" IO_TYPE=LVCMOS33 PULLMODE=UP ;
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IOBUF PORT "spi_sck" IO_TYPE=LVCMOS33 PULLMODE=DOWN ;
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IOBUF PORT "spi_miso" IO_TYPE=LVCMOS33 ;
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LOCATE COMP "spi_cs_n" SITE "27" ;
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LOCATE COMP "led_red" SITE "20" ;
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LOCATE COMP "led_green" SITE "21" ;
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LOCATE COMP "lcd_data[1]" SITE "4" ;
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LOCATE COMP "lcd_data[2]" SITE "5" ;
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LOCATE COMP "lcd_data[3]" SITE "8" ;
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LOCATE COMP "lcd_load" SITE "10" ;
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LOCATE COMP "lcd_frp" SITE "11" ;
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LOCATE COMP "lcd_frmb" SITE "12" ;
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LOCATE COMP "lcd_data[0]" SITE "13" ;
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LOCATE COMP "spi_mosi" SITE "17" ;
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LOCATE COMP "spi_sck" SITE "16" ;
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LOCATE COMP "spi_miso" SITE "25" ;
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LOCATE COMP "led_green" SITE "21" ;
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LOCATE COMP "led_red" SITE "20" ;
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LOCATE COMP "spi_cs_n" SITE "27" ;
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