library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library design; use design.all; entity bench_top is end entity bench_top; architecture RTL of bench_top is signal clk : std_logic; signal rst_hw : std_logic; signal lcd_data : std_logic_vector(3 downto 0); signal lcd_clp : std_logic; signal lcd_load : std_logic; signal lcd_frp : std_logic; signal lcd_frmb : std_logic; signal spi_cs_n : std_logic; signal spi_sck : std_logic; signal spi_mosi : std_logic; signal spi_miso : std_logic; begin top_inst : entity design.top port map( spi_cs_n => spi_cs_n, spi_sck => spi_sck, spi_mosi => spi_mosi, spi_miso => spi_miso, clk_hw => clk, rst_hw => rst_hw, lcd_data => lcd_data, lcd_clp => lcd_clp, lcd_load => lcd_load, lcd_frp => lcd_frp, lcd_frmb => lcd_frmb ); clock_driver : process constant period : time := (1 sec / 24000000); begin clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2; end process clock_driver; test : process is begin rst_hw <= '0'; wait for 100 ns; rst_hw <= '1'; wait; end process test; spitest : process is constant CPOL : std_logic := '0'; constant DEL : time := 400 ns; procedure send_byte(data : std_logic_vector(7 downto 0)) is begin for i in 7 downto 0 loop spi_sck <= CPOL; wait for DEL; spi_mosi <= data(i); spi_sck <= not CPOL; wait for DEL; end loop; end procedure send_byte; begin spi_cs_n <= '1'; spi_sck <= '0'; spi_mosi <= CPOL; wait until rst_hw = '1'; wait until rising_edge(clk); wait until rising_edge(clk); wait until rising_edge(clk); wait until rising_edge(clk); wait until rising_edge(clk); spi_cs_n <= '0'; wait for 400 ns; send_byte(x"00"); send_byte(x"00"); send_byte(x"00"); send_byte(x"AB"); send_byte(x"CD"); send_byte(x"55"); send_byte(x"AA"); send_byte(x"81"); send_byte(x"2A"); send_byte(x"AB"); send_byte(x"BC"); send_byte(x"CF"); send_byte(x"AB"); send_byte(x"CD"); send_byte(x"55"); send_byte(x"AA"); send_byte(x"81"); send_byte(x"2A"); send_byte(x"AB"); send_byte(x"BC"); send_byte(x"CF"); spi_cs_n <= '1'; wait; end process spitest; end architecture RTL;