library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity ram is generic( WIDTH : natural := 9; DEPTH : natural := 10 ); port( clk : in std_logic; rst : in std_logic; -- a_addr_in : in std_logic_vector(DEPTH - 1 downto 0); a_data_in : in std_logic_vector(WIDTH - 1 downto 0); a_data_out : out std_logic_vector(WIDTH - 1 downto 0); a_we : in std_logic; -- b_addr_in : in std_logic_vector(DEPTH - 1 downto 0); b_data_out : out std_logic_vector(WIDTH - 1 downto 0) ); end entity ram; architecture RTL of ram is type memory_t is array (0 to 2**DEPTH - 1) of std_logic_vector(WIDTH - 1 downto 0); signal memory : memory_t; begin mem_p : process(clk, rst) is begin if (rst = '1') then a_data_out <= (others => '0'); b_data_out <= (others => '0'); -- memory(0) <= "111100001"; -- memory(1) <= "100101001"; -- memory(2) <= "000000000"; -- memory(3) <= "101010100"; -- -- memory(4) <= "111111111"; -- memory(5) <= "000000000"; -- memory(6) <= "000000000"; -- memory(7) <= "000000000"; ---- ---- memory(0) <= "111111111"; ---- memory(1) <= "111111111"; ---- memory(2) <= "111111111"; ---- memory(3) <= "111111111"; ---- memory(4) <= "111111111"; ---- memory(5) <= "111111111"; ---- memory(6) <= "111111111"; ---- memory(7) <= "111111111"; -- -- memory(0) <= "101010101"; -- memory(1) <= "101010100"; -- memory(2) <= "101010101"; -- memory(3) <= "101010100"; -- -- memory(4) <= "101010101"; -- memory(5) <= "101010100"; -- memory(6) <= "101010101"; -- memory(7) <= "101010100"; elsif (rising_edge(clk)) then a_data_out <= memory(to_integer(unsigned(a_addr_in))); b_data_out <= memory(to_integer(unsigned(b_addr_in))); if (a_we = '1') then memory(to_integer(unsigned(a_addr_in))) <= a_data_in; end if; end if; end process mem_p; end architecture RTL;