library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity synchronizer is generic( INIT : std_logic := '0' ); port( clk : in std_logic; rst : in std_logic; din : in std_logic; dout : out std_logic ); end entity synchronizer; architecture RTL of synchronizer is signal tmp : std_logic_vector(1 downto 0); begin sync_p : process(clk, rst) is begin if (rst = '1') then tmp <= (others => INIT); dout <= INIT; elsif (rising_edge(clk)) then tmp <= tmp(0) & din; dout <= tmp(1); end if; end process sync_p; end architecture RTL;