Starting process: Module Starting process: SCUBA, Version Diamond (64-bit) 3.10.0.111.2 Tue Apr 24 22:15:53 2018 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved. BEGIN SCUBA Module Synthesis Issued command : /usr/local/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n pll0 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 12 -fclkop 96 -fclkop_tol 0.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1 -lock Circuit name : pll0 Module type : pll Module Version : 5.7 Ports : Inputs : CLKI Outputs : CLKOP, LOCK I/O buffer : not inserted EDIF output : pll0.edn VHDL output : pll0.vhd VHDL template : pll0_tmpl.vhd VHDL purpose : for synthesis and simulation Bus notation : big endian Report output : pll0.srp Estimated Resource Usage: END SCUBA Module Synthesis File: pll0.lpc created. End process: completed successfully. Total Warnings: 0 Total Errors: 0