46 lines
		
	
	
		
			1003 B
		
	
	
	
		
			VHDL
		
	
	
	
	
	
			
		
		
	
	
			46 lines
		
	
	
		
			1003 B
		
	
	
	
		
			VHDL
		
	
	
	
	
	
| library ieee;
 | |
| use ieee.std_logic_1164.all;
 | |
| use ieee.numeric_std.all;
 | |
| 
 | |
| library generics;
 | |
| use generics.all;
 | |
| 
 | |
| entity gram0 is
 | |
| 	port(
 | |
| 		DataInA  : in  std_logic_vector(8 downto 0);
 | |
| 		DataInB  : in  std_logic_vector(8 downto 0);
 | |
| 		AddressA : in  std_logic_vector(12 downto 0);
 | |
| 		AddressB : in  std_logic_vector(12 downto 0);
 | |
| 		ClockA   : in  std_logic;
 | |
| 		ClockB   : in  std_logic;
 | |
| 		ClockEnA : in  std_logic;
 | |
| 		ClockEnB : in  std_logic;
 | |
| 		WrA      : in  std_logic;
 | |
| 		WrB      : in  std_logic;
 | |
| 		ResetA   : in  std_logic;
 | |
| 		ResetB   : in  std_logic;
 | |
| 		QA       : out std_logic_vector(8 downto 0);
 | |
| 		QB       : out std_logic_vector(8 downto 0));
 | |
| end gram0;
 | |
| 
 | |
| architecture RTL of gram0 is
 | |
| 
 | |
| begin
 | |
| 	ram_inst : entity generics.ram
 | |
| 		generic map(
 | |
| 			WIDTH => 9,
 | |
| 			DEPTH  => 13
 | |
| 		)
 | |
| 		port map(
 | |
| 			clk        => ClockA,
 | |
| 			rst        => ResetA,
 | |
| 			a_addr_in  => AddressA,
 | |
| 			a_data_in  => DataInA,
 | |
| 			a_data_out => QA,
 | |
| 			a_we       => WrA,
 | |
| 			b_addr_in  => AddressB,
 | |
| 			b_data_out => QB
 | |
| 		);
 | |
| 	
 | |
| end architecture RTL;
 |