1
0
mirror of https://git.shimatta.de/pcb/headphone-amp.git synced 2024-12-22 22:45:05 +01:00
shimatta-hpa/headphone-amp.kicad_pcb

175 lines
4.1 KiB
Plaintext
Raw Normal View History

2017-06-09 00:41:36 +02:00
(kicad_pcb (version 4) (host pcbnew 4.0.6)
(general
(links 156)
(no_connects 0)
(area 10.624999 12.124999 132.405001 70.100001)
2017-06-09 00:41:36 +02:00
(thickness 1.6)
(drawings 0)
(tracks 0)
2017-06-09 00:41:36 +02:00
(zones 0)
(modules 0)
(nets 1)
2017-06-09 00:41:36 +02:00
)
(page A4)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user hide)
(49 F.Fab user hide)
)
(setup
(last_trace_width 0.4)
(user_trace_width 0.2)
(user_trace_width 0.25)
(user_trace_width 0.6)
(user_trace_width 0.8)
(user_trace_width 1.5)
(trace_clearance 0.2)
(zone_clearance 0.3)
(zone_45_only no)
(trace_min 0.2)
(segment_width 0.2)
(edge_width 0.15)
(via_size 0.6)
(via_drill 0.4)
(via_min_size 0.4)
(via_min_drill 0.3)
(user_via 0.5 0.3)
(user_via 1.3 1)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.15)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1.524 1.524)
(pad_drill 0.762)
(pad_to_mask_clearance 0.2)
(aux_axis_origin 0 0)
(visible_elements FFFFFFFF)
(pcbplotparams
(layerselection 0x00030_80000001)
(usegerberextensions false)
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15)
(hpglpenoverlay 2)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory ""))
)
(net 0 "")
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.4)
(via_dia 0.6)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net +12V)
(add_net +3V3)
(add_net +5V)
(add_net -12V)
(add_net /D+)
(add_net /D-)
(add_net /LUSB)
(add_net /RUSB)
(add_net Earth)
(add_net GNDA)
(add_net GNDPWR)
(add_net "Net-(C1-Pad1)")
(add_net "Net-(C10-Pad1)")
(add_net "Net-(C12-Pad1)")
(add_net "Net-(C13-Pad2)")
(add_net "Net-(C14-Pad1)")
(add_net "Net-(C15-Pad1)")
(add_net "Net-(C16-Pad1)")
(add_net "Net-(C17-Pad2)")
(add_net "Net-(C18-Pad2)")
(add_net "Net-(C21-Pad1)")
(add_net "Net-(C22-Pad2)")
(add_net "Net-(C27-Pad1)")
(add_net "Net-(C29-Pad1)")
(add_net "Net-(C30-Pad1)")
(add_net "Net-(C31-Pad1)")
(add_net "Net-(C33-Pad2)")
(add_net "Net-(C35-Pad2)")
(add_net "Net-(C4-Pad2)")
(add_net "Net-(C5-Pad1)")
(add_net "Net-(C7-Pad1)")
(add_net "Net-(C7-Pad2)")
(add_net "Net-(C8-Pad1)")
(add_net "Net-(C8-Pad2)")
(add_net "Net-(C9-Pad1)")
(add_net "Net-(D1-Pad1)")
(add_net "Net-(J3-Pad1)")
(add_net "Net-(J4-Pad2)")
(add_net "Net-(J4-Pad3)")
(add_net "Net-(J4-Pad4)")
(add_net "Net-(J4-Pad5)")
(add_net "Net-(J4-Pad6)")
(add_net "Net-(K1-Pad3)")
(add_net "Net-(K1-Pad6)")
(add_net "Net-(R10-Pad2)")
(add_net "Net-(R11-Pad2)")
(add_net "Net-(R12-Pad2)")
(add_net "Net-(R13-Pad2)")
(add_net "Net-(R14-Pad1)")
(add_net "Net-(R15-Pad2)")
(add_net "Net-(R16-Pad1)")
(add_net "Net-(R2-Pad2)")
(add_net "Net-(R3-Pad1)")
(add_net "Net-(R7-Pad2)")
(add_net "Net-(RV1-Pad12)")
(add_net "Net-(RV1-Pad22)")
(add_net "Net-(U1-Pad2)")
(add_net "Net-(U1-Pad22)")
(add_net "Net-(U1-Pad23)")
(add_net "Net-(U1-Pad24)")
(add_net "Net-(U1-Pad27)")
(add_net "Net-(U1-Pad3)")
(add_net "Net-(U1-Pad5)")
)
)