Reannotate schematic

master rev01
Markus Koch 2017-10-01 23:12:04 +02:00
parent 6bcb9c32ce
commit 18151985c0
4 changed files with 224 additions and 262 deletions

186
fpga.sch
View File

@ -96,16 +96,16 @@ U 1 1 59CE9484
P 1350 1700
F 0 "U4" H 1750 2587 60 0000 C CNN
F 1 "12MHz" H 1750 2481 60 0000 C CNN
F 2 "Crystals:Crystal_SMD_7050-4pin_7.0x5.0mm" H 1550 1550 60 0001 C CNN
F 2 "Oscillators:Oscillator_SMD_EuroQuartz_XO91-4pin_7.0x5.0mm" H 1550 1550 60 0001 C CNN
F 3 "" H 1550 1550 60 0000 C CNN
1 1350 1700
1 0 0 -1
$EndComp
$Comp
L GND #PWR016
L GND #PWR019
U 1 1 59CE95DE
P 950 1650
F 0 "#PWR016" H 950 1400 50 0001 C CNN
F 0 "#PWR019" H 950 1400 50 0001 C CNN
F 1 "GND" H 955 1477 50 0000 C CNN
F 2 "" H 950 1650 50 0001 C CNN
F 3 "" H 950 1650 50 0001 C CNN
@ -113,10 +113,10 @@ F 3 "" H 950 1650 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L +3V3 #PWR015
L +3V3 #PWR016
U 1 1 59CE9655
P 950 1050
F 0 "#PWR015" H 950 900 50 0001 C CNN
F 0 "#PWR016" H 950 900 50 0001 C CNN
F 1 "+3V3" H 965 1223 50 0000 C CNN
F 2 "" H 950 1050 50 0001 C CNN
F 3 "" H 950 1050 50 0001 C CNN
@ -136,10 +136,10 @@ F 3 "" H 950 1350 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L +3V3 #PWR026
L +3V3 #PWR024
U 1 1 59CE9C96
P 8550 3450
F 0 "#PWR026" H 8550 3300 50 0001 C CNN
F 0 "#PWR024" H 8550 3300 50 0001 C CNN
F 1 "+3V3" H 8565 3623 50 0000 C CNN
F 2 "" H 8550 3450 50 0001 C CNN
F 3 "" H 8550 3450 50 0001 C CNN
@ -147,10 +147,10 @@ F 3 "" H 8550 3450 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L R R9
L R R2
U 1 1 59CEA10C
P 2800 1250
F 0 "R9" V 2700 1250 50 0000 C CNN
F 0 "R2" V 2700 1250 50 0000 C CNN
F 1 "33" V 2800 1250 50 0000 C CNN
F 2 "Resistors_SMD:R_0603" V 2730 1250 50 0001 C CNN
F 3 "" H 2800 1250 50 0001 C CNN
@ -158,10 +158,10 @@ F 3 "" H 2800 1250 50 0001 C CNN
0 1 1 0
$EndComp
$Comp
L R R10
L R R3
U 1 1 59CEA1C2
P 2800 1450
F 0 "R10" V 2700 1450 50 0000 C CNN
F 0 "R3" V 2700 1450 50 0000 C CNN
F 1 "33" V 2800 1450 50 0000 C CNN
F 2 "Resistors_SMD:R_0603" V 2730 1450 50 0001 C CNN
F 3 "" H 2800 1450 50 0001 C CNN
@ -208,10 +208,10 @@ F 3 "" H 9350 1400 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L GND #PWR028
L GND #PWR020
U 1 1 59CEB96A
P 8950 1750
F 0 "#PWR028" H 8950 1500 50 0001 C CNN
F 0 "#PWR020" H 8950 1500 50 0001 C CNN
F 1 "GND" H 8955 1577 50 0000 C CNN
F 2 "" H 8950 1750 50 0001 C CNN
F 3 "" H 8950 1750 50 0001 C CNN
@ -219,10 +219,10 @@ F 3 "" H 8950 1750 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L +3V3 #PWR027
L +3V3 #PWR015
U 1 1 59CEB9F3
P 8950 1000
F 0 "#PWR027" H 8950 850 50 0001 C CNN
F 0 "#PWR015" H 8950 850 50 0001 C CNN
F 1 "+3V3" H 8965 1173 50 0000 C CNN
F 2 "" H 8950 1000 50 0001 C CNN
F 3 "" H 8950 1000 50 0001 C CNN
@ -265,10 +265,10 @@ F 3 "" H 10750 1400 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L GND #PWR029
L GND #PWR021
U 1 1 59CEBF83
P 10350 1750
F 0 "#PWR029" H 10350 1500 50 0001 C CNN
F 0 "#PWR021" H 10350 1500 50 0001 C CNN
F 1 "GND" H 10355 1577 50 0000 C CNN
F 2 "" H 10350 1750 50 0001 C CNN
F 3 "" H 10350 1750 50 0001 C CNN
@ -282,10 +282,10 @@ VCCIO23
Text Label 1550 4600 0 60 ~ 0
VCCIO23
$Comp
L R R3
L R R9
U 1 1 59CEC5BE
P 1300 4600
F 0 "R3" V 1200 4600 50 0000 C CNN
F 0 "R9" V 1200 4600 50 0000 C CNN
F 1 "DNP" V 1300 4600 50 0000 C CNN
F 2 "Resistors_SMD:R_0603" V 1230 4600 50 0001 C CNN
F 3 "" H 1300 4600 50 0001 C CNN
@ -293,10 +293,10 @@ F 3 "" H 1300 4600 50 0001 C CNN
0 1 1 0
$EndComp
$Comp
L +3V3 #PWR017
L +3V3 #PWR030
U 1 1 59CECD95
P 1050 4500
F 0 "#PWR017" H 1050 4350 50 0001 C CNN
F 0 "#PWR030" H 1050 4350 50 0001 C CNN
F 1 "+3V3" H 1065 4673 50 0000 C CNN
F 2 "" H 1050 4500 50 0001 C CNN
F 3 "" H 1050 4500 50 0001 C CNN
@ -318,10 +318,10 @@ JTAG_TDI
Text Label 8650 3200 2 60 ~ 0
JTAG_TDO
$Comp
L Conn_01x15 J3
L Conn_01x15 J4
U 1 1 59CE3A58
P 5900 3550
F 0 "J3" H 5900 2750 50 0000 C CNN
F 0 "J4" H 5900 2750 50 0000 C CNN
F 1 "Conn_Right" H 5800 4350 50 0000 C CNN
F 2 "Pin_Headers:Pin_Header_Straight_1x15_Pitch2.54mm" H 5900 3550 50 0001 C CNN
F 3 "" H 5900 3550 50 0001 C CNN
@ -329,10 +329,10 @@ F 3 "" H 5900 3550 50 0001 C CNN
-1 0 0 -1
$EndComp
$Comp
L VBUS #PWR021
L VBUS #PWR026
U 1 1 59CE4228
P 4600 4150
F 0 "#PWR021" H 4600 4000 50 0001 C CNN
F 0 "#PWR026" H 4600 4000 50 0001 C CNN
F 1 "VBUS" H 4615 4323 50 0000 C CNN
F 2 "" H 4600 4150 50 0001 C CNN
F 3 "" H 4600 4150 50 0001 C CNN
@ -342,10 +342,10 @@ $EndComp
Text Label 8650 2600 2 60 ~ 0
JTAG_EN
$Comp
L +3V3 #PWR023
L +3V3 #PWR027
U 1 1 59CE4C57
P 6600 4150
F 0 "#PWR023" H 6600 4000 50 0001 C CNN
F 0 "#PWR027" H 6600 4000 50 0001 C CNN
F 1 "+3V3" H 6615 4323 50 0000 C CNN
F 2 "" H 6600 4150 50 0001 C CNN
F 3 "" H 6600 4150 50 0001 C CNN
@ -353,10 +353,10 @@ F 3 "" H 6600 4150 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L GND #PWR019
L GND #PWR028
U 1 1 59CE5028
P 5000 4350
F 0 "#PWR019" H 5000 4100 50 0001 C CNN
F 0 "#PWR028" H 5000 4100 50 0001 C CNN
F 1 "GND" H 5005 4177 50 0000 C CNN
F 2 "" H 5000 4350 50 0001 C CNN
F 3 "" H 5000 4350 50 0001 C CNN
@ -364,10 +364,10 @@ F 3 "" H 5000 4350 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L R R4
L R R6
U 1 1 59CE5A45
P 1400 3850
F 0 "R4" V 1350 4000 50 0000 C CNN
F 0 "R6" V 1350 4000 50 0000 C CNN
F 1 "1k" V 1400 3850 50 0000 C CNN
F 2 "Resistors_SMD:R_0603" V 1330 3850 50 0001 C CNN
F 3 "" H 1400 3850 50 0001 C CNN
@ -375,10 +375,10 @@ F 3 "" H 1400 3850 50 0001 C CNN
0 1 1 0
$EndComp
$Comp
L R R5
L R R7
U 1 1 59CE5D31
P 1400 3950
F 0 "R5" V 1350 4100 50 0000 C CNN
F 0 "R7" V 1350 4100 50 0000 C CNN
F 1 "1k" V 1400 3950 50 0000 C CNN
F 2 "Resistors_SMD:R_0603" V 1330 3950 50 0001 C CNN
F 3 "" H 1400 3950 50 0001 C CNN
@ -386,10 +386,10 @@ F 3 "" H 1400 3950 50 0001 C CNN
0 1 1 0
$EndComp
$Comp
L R R6
L R R8
U 1 1 59CE5D67
P 1400 4050
F 0 "R6" V 1350 4200 50 0000 C CNN
F 0 "R8" V 1350 4200 50 0000 C CNN
F 1 "1k" V 1400 4050 50 0000 C CNN
F 2 "Resistors_SMD:R_0603" V 1330 4050 50 0001 C CNN
F 3 "" H 1400 4050 50 0001 C CNN
@ -433,10 +433,10 @@ F 3 "" H 1650 3100 50 0001 C CNN
0 -1 -1 0
$EndComp
$Comp
L R R8
L R R5
U 1 1 59CEBBCC
P 1850 3500
F 0 "R8" H 1850 3350 50 0000 L CNN
F 0 "R5" H 1850 3350 50 0000 L CNN
F 1 "1k" V 1850 3450 50 0000 L CNN
F 2 "Resistors_SMD:R_0603" V 1780 3500 50 0001 C CNN
F 3 "" H 1850 3500 50 0001 C CNN
@ -444,10 +444,10 @@ F 3 "" H 1850 3500 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L R R7
L R R4
U 1 1 59CEBC90
P 1650 3500
F 0 "R7" H 1650 3350 50 0000 L CNN
F 0 "R4" H 1650 3350 50 0000 L CNN
F 1 "1k" V 1650 3450 50 0000 L CNN
F 2 "Resistors_SMD:R_0603" V 1580 3500 50 0001 C CNN
F 3 "" H 1650 3500 50 0001 C CNN
@ -455,10 +455,10 @@ F 3 "" H 1650 3500 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L +3V3 #PWR018
L +3V3 #PWR022
U 1 1 59CEC837
P 1750 2750
F 0 "#PWR018" H 1750 2600 50 0001 C CNN
F 0 "#PWR022" H 1750 2600 50 0001 C CNN
F 1 "+3V3" H 1765 2923 50 0000 C CNN
F 2 "" H 1750 2750 50 0001 C CNN
F 3 "" H 1750 2750 50 0001 C CNN
@ -496,10 +496,10 @@ P5
Text Label 8650 6100 2 60 ~ 0
P4
$Comp
L Conn_02x04_Odd_Even J4
L Conn_02x04_Odd_Even J2
U 1 1 59CE71D1
P 5550 1550
F 0 "J4" H 5600 1867 50 0000 C CNN
F 0 "J2" H 5600 1867 50 0000 C CNN
F 1 "JTAG" H 5600 1776 50 0000 C CNN
F 2 "Pin_Headers:Pin_Header_Straight_2x04_Pitch2.54mm" H 5550 1550 50 0001 C CNN
F 3 "" H 5550 1550 50 0001 C CNN
@ -518,10 +518,10 @@ Text Label 5950 1750 0 60 ~ 0
JTAG_EN
NoConn ~ 5850 1650
$Comp
L Conn_01x15 J2
L Conn_01x15 J3
U 1 1 59CE37F9
P 5300 3550
F 0 "J2" H 5250 2750 50 0000 L CNN
F 0 "J3" H 5250 2750 50 0000 L CNN
F 1 "Conn_Left" H 5050 4350 50 0000 L CNN
F 2 "Pin_Headers:Pin_Header_Straight_1x15_Pitch2.54mm" H 5300 3550 50 0001 C CNN
F 3 "" H 5300 3550 50 0001 C CNN
@ -557,10 +557,10 @@ CLK_FPGA
Text Label 6300 3650 0 60 ~ 0
P25
$Comp
L GND #PWR025
L GND #PWR018
U 1 1 59CF1BA4
P 6500 1600
F 0 "#PWR025" H 6500 1350 50 0001 C CNN
F 0 "#PWR018" H 6500 1350 50 0001 C CNN
F 1 "GND" H 6505 1427 50 0000 C CNN
F 2 "" H 6500 1600 50 0001 C CNN
F 3 "" H 6500 1600 50 0001 C CNN
@ -568,10 +568,10 @@ F 3 "" H 6500 1600 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L +3V3 #PWR024
L +3V3 #PWR017
U 1 1 59CF1EB2
P 6500 1400
F 0 "#PWR024" H 6500 1250 50 0001 C CNN
F 0 "#PWR017" H 6500 1250 50 0001 C CNN
F 1 "+3V3" H 6515 1573 50 0000 C CNN
F 2 "" H 6500 1400 50 0001 C CNN
F 3 "" H 6500 1400 50 0001 C CNN
@ -579,10 +579,10 @@ F 3 "" H 6500 1400 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L GND #PWR020
L GND #PWR029
U 1 1 59CFD9A4
P 6200 4350
F 0 "#PWR020" H 6200 4100 50 0001 C CNN
F 0 "#PWR029" H 6200 4100 50 0001 C CNN
F 1 "GND" H 6205 4177 50 0000 C CNN
F 2 "" H 6200 4350 50 0001 C CNN
F 3 "" H 6200 4350 50 0001 C CNN
@ -598,10 +598,10 @@ JTAG_TCK
Text Label 6300 3150 0 60 ~ 0
JTAG_TMS
$Comp
L +3V3 #PWR022
L +3V3 #PWR023
U 1 1 59D0394F
P 4600 2750
F 0 "#PWR022" H 4600 2600 50 0001 C CNN
F 0 "#PWR023" H 4600 2600 50 0001 C CNN
F 1 "+3V3" H 4615 2923 50 0000 C CNN
F 2 "" H 4600 2750 50 0001 C CNN
F 3 "" H 4600 2750 50 0001 C CNN
@ -615,10 +615,10 @@ TX
Text Label 8650 4000 2 60 ~ 0
RX
$Comp
L GND #PWR031
L GND #PWR025
U 1 1 59D138A1
P 6950 3900
F 0 "#PWR031" H 6950 3650 50 0001 C CNN
F 0 "#PWR025" H 6950 3650 50 0001 C CNN
F 1 "GND" H 6955 3727 50 0000 C CNN
F 2 "" H 6950 3900 50 0001 C CNN
F 3 "" H 6950 3900 50 0001 C CNN
@ -629,36 +629,26 @@ Wire Wire Line
6100 3250 6300 3250
Connection ~ 6950 3750
Wire Wire Line
6950 3350 6950 3750
Wire Wire Line
6950 3750 6950 3900
6950 3350 6950 3900
Wire Wire Line
1050 1150 950 1150
Wire Wire Line
950 1050 950 1150
Wire Wire Line
950 1150 950 1250
950 1050 950 1250
Wire Wire Line
1050 1550 950 1550
Wire Wire Line
950 1450 950 1550
Wire Wire Line
950 1550 950 1650
950 1450 950 1650
Connection ~ 950 1550
Connection ~ 950 1150
Wire Wire Line
8650 3350 8650 3450
Wire Wire Line
8650 3450 8650 3750
8650 3350 8650 3750
Wire Wire Line
8650 3350 8750 3350
Connection ~ 8650 3450
Wire Wire Line
2450 1350 2550 1350
Wire Wire Line
2550 1250 2550 1350
Wire Wire Line
2550 1350 2550 1450
2550 1250 2550 1450
Wire Wire Line
2550 1250 2650 1250
Wire Wire Line
@ -671,20 +661,14 @@ Wire Wire Line
Wire Wire Line
8650 5850 8750 5850
Wire Wire Line
8650 5450 8650 5550
8650 5450 8650 5850
Wire Wire Line
8650 5550 8650 5850
Wire Wire Line
8500 5550 8650 5550
Wire Wire Line
8650 5550 8750 5550
8500 5550 8750 5550
Wire Wire Line
8650 5450 8750 5450
Connection ~ 8650 5550
Wire Wire Line
8550 3750 8650 3750
Wire Wire Line
8650 3750 8750 3750
8550 3750 8750 3750
Wire Wire Line
8750 3450 8650 3450
Wire Wire Line
@ -693,28 +677,20 @@ Connection ~ 8650 3750
Wire Wire Line
9350 1650 9350 1550
Wire Wire Line
8550 1650 8950 1650
Wire Wire Line
8950 1650 9350 1650
8550 1650 9350 1650
Wire Wire Line
8550 1650 8550 1550
Wire Wire Line
8950 1550 8950 1650
Wire Wire Line
8950 1650 8950 1750
8950 1550 8950 1750
Connection ~ 8950 1650
Wire Wire Line
9350 1100 9350 1250
Wire Wire Line
8550 1100 8950 1100
Wire Wire Line
8950 1100 9350 1100
8550 1100 9350 1100
Wire Wire Line
8550 1100 8550 1250
Wire Wire Line
8950 1000 8950 1100
Wire Wire Line
8950 1100 8950 1250
8950 1000 8950 1250
Connection ~ 8950 1100
Wire Notes Line
8350 700 9650 700
@ -727,28 +703,20 @@ Wire Notes Line
Wire Wire Line
10750 1650 10750 1550
Wire Wire Line
9950 1650 10350 1650
Wire Wire Line
10350 1650 10750 1650
9950 1650 10750 1650
Wire Wire Line
9950 1650 9950 1550
Wire Wire Line
10350 1550 10350 1650
Wire Wire Line
10350 1650 10350 1750
10350 1550 10350 1750
Connection ~ 10350 1650
Wire Wire Line
10750 1100 10750 1250
Wire Wire Line
9950 1100 10350 1100
Wire Wire Line
10350 1100 10750 1100
9950 1100 10750 1100
Wire Wire Line
9950 1100 9950 1250
Wire Wire Line
10350 1000 10350 1100
Wire Wire Line
10350 1100 10350 1250
10350 1000 10350 1250
Connection ~ 10350 1100
Wire Notes Line
9750 700 11050 700
@ -787,13 +755,9 @@ Wire Wire Line
Wire Wire Line
1150 4050 1250 4050
Wire Wire Line
1550 3850 1650 3850
1550 3850 1950 3850
Wire Wire Line
1650 3850 1950 3850
Wire Wire Line
1550 3950 1850 3950
Wire Wire Line
1850 3950 1950 3950
1550 3950 1950 3950
Wire Wire Line
1550 4050 1950 4050
Wire Notes Line
@ -833,9 +797,7 @@ Wire Wire Line
Connection ~ 1850 3950
Connection ~ 1650 3850
Wire Wire Line
1650 2850 1750 2850
Wire Wire Line
1750 2850 1850 2850
1650 2850 1850 2850
Wire Wire Line
1750 2850 1750 2750
Connection ~ 1750 2850

View File

@ -58,10 +58,10 @@ F 3 "" H 1850 950 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L C_Small C2
L C_Small C6
U 1 1 59CE0D8D
P 1300 1400
F 0 "C2" H 1392 1446 50 0000 L CNN
F 0 "C6" H 1392 1446 50 0000 L CNN
F 1 "100n" H 1392 1355 50 0000 L CNN
F 2 "Capacitors_SMD:C_0603" H 1300 1400 50 0001 C CNN
F 3 "" H 1300 1400 50 0001 C CNN
@ -69,10 +69,10 @@ F 3 "" H 1300 1400 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L CP_Small C1
L CP_Small C5
U 1 1 59CE0E72
P 1100 1400
F 0 "C1" H 1187 1446 50 0000 L CNN
F 0 "C5" H 1187 1446 50 0000 L CNN
F 1 "1u" H 1187 1355 50 0000 L CNN
F 2 "Capacitors_SMD:C_0805" H 1100 1400 50 0001 C CNN
F 3 "" H 1100 1400 50 0001 C CNN
@ -80,10 +80,10 @@ F 3 "" H 1100 1400 50 0001 C CNN
-1 0 0 -1
$EndComp
$Comp
L C_Small C3
L C_Small C7
U 1 1 59CE1081
P 2200 1400
F 0 "C3" H 2108 1354 50 0000 R CNN
F 0 "C7" H 2108 1354 50 0000 R CNN
F 1 "100n" H 2108 1445 50 0000 R CNN
F 2 "Capacitors_SMD:C_0603" H 2200 1400 50 0001 C CNN
F 3 "" H 2200 1400 50 0001 C CNN
@ -91,10 +91,10 @@ F 3 "" H 2200 1400 50 0001 C CNN
1 0 0 1
$EndComp
$Comp
L GND #PWR02
L GND #PWR05
U 1 1 59CE11F3
P 1750 1700
F 0 "#PWR02" H 1750 1450 50 0001 C CNN
F 0 "#PWR05" H 1750 1450 50 0001 C CNN
F 1 "GND" H 1755 1527 50 0000 C CNN
F 2 "" H 1750 1700 50 0001 C CNN
F 3 "" H 1750 1700 50 0001 C CNN
@ -102,10 +102,10 @@ F 3 "" H 1750 1700 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L +3V3 #PWR05
L +3V3 #PWR02
U 1 1 59CE142B
P 2200 1100
F 0 "#PWR05" H 2200 950 50 0001 C CNN
F 0 "#PWR02" H 2200 950 50 0001 C CNN
F 1 "+3V3" H 2215 1273 50 0000 C CNN
F 2 "" H 2200 1100 50 0001 C CNN
F 3 "" H 2200 1100 50 0001 C CNN
@ -113,10 +113,10 @@ F 3 "" H 2200 1100 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L VBUS #PWR01
L VBUS #PWR03
U 1 1 59CE157B
P 1200 1150
F 0 "#PWR01" H 1200 1000 50 0001 C CNN
F 0 "#PWR03" H 1200 1000 50 0001 C CNN
F 1 "VBUS" H 1215 1323 50 0000 C CNN
F 2 "" H 1200 1150 50 0001 C CNN
F 3 "" H 1200 1150 50 0001 C CNN
@ -135,10 +135,10 @@ F 3 "" H 3950 1750 60 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L C_Small C4
L C_Small C1
U 1 1 59CE1FC1
P 3600 1350
F 0 "C4" H 3500 1300 50 0000 R CNN
F 0 "C1" H 3500 1300 50 0000 R CNN
F 1 "10n" H 3600 1400 50 0000 R CNN
F 2 "Capacitors_SMD:C_0603" H 3600 1350 50 0001 C CNN
F 3 "" H 3600 1350 50 0001 C CNN
@ -146,10 +146,10 @@ F 3 "" H 3600 1350 50 0001 C CNN
1 0 0 1
$EndComp
$Comp
L GND #PWR010
L GND #PWR09
U 1 1 59CE28E2
P 4800 3000
F 0 "#PWR010" H 4800 2750 50 0001 C CNN
F 0 "#PWR09" H 4800 2750 50 0001 C CNN
F 1 "GND" H 4805 2827 50 0000 C CNN
F 2 "" H 4800 3000 50 0001 C CNN
F 3 "" H 4800 3000 50 0001 C CNN
@ -157,10 +157,10 @@ F 3 "" H 4800 3000 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L +3V3 #PWR06
L +3V3 #PWR07
U 1 1 59CE2901
P 3400 2550
F 0 "#PWR06" H 3400 2400 50 0001 C CNN
F 0 "#PWR07" H 3400 2400 50 0001 C CNN
F 1 "+3V3" H 3400 2700 50 0000 C CNN
F 2 "" H 3400 2550 50 0001 C CNN
F 3 "" H 3400 2550 50 0001 C CNN
@ -168,10 +168,10 @@ F 3 "" H 3400 2550 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L C_Small C5
L C_Small C2
U 1 1 59CE2F41
P 3900 1350
F 0 "C5" H 3800 1300 50 0000 R CNN
F 0 "C2" H 3800 1300 50 0000 R CNN
F 1 "100n" H 3900 1400 50 0000 R CNN
F 2 "Capacitors_SMD:C_0603" H 3900 1350 50 0001 C CNN
F 3 "" H 3900 1350 50 0001 C CNN
@ -179,10 +179,10 @@ F 3 "" H 3900 1350 50 0001 C CNN
1 0 0 1
$EndComp
$Comp
L C_Small C6
L C_Small C3
U 1 1 59CE300F
P 4200 1350
F 0 "C6" H 4100 1300 50 0000 R CNN
F 0 "C3" H 4100 1300 50 0000 R CNN
F 1 "10n" H 4200 1400 50 0000 R CNN
F 2 "Capacitors_SMD:C_0603" H 4200 1350 50 0001 C CNN
F 3 "" H 4200 1350 50 0001 C CNN
@ -190,10 +190,10 @@ F 3 "" H 4200 1350 50 0001 C CNN
1 0 0 1
$EndComp
$Comp
L C_Small C7
L C_Small C4
U 1 1 59CE303F
P 4500 1350
F 0 "C7" H 4400 1300 50 0000 R CNN
F 0 "C4" H 4400 1300 50 0000 R CNN
F 1 "100n" H 4500 1400 50 0000 R CNN
F 2 "Capacitors_SMD:C_0603" H 4500 1350 50 0001 C CNN
F 3 "" H 4500 1350 50 0001 C CNN
@ -270,10 +270,10 @@ Wire Wire Line
4050 1150 4050 1050
Connection ~ 4050 1150
$Comp
L +3V3 #PWR08
L +3V3 #PWR01
U 1 1 59CE365D
P 4050 1050
F 0 "#PWR08" H 4050 900 50 0001 C CNN
F 0 "#PWR01" H 4050 900 50 0001 C CNN
F 1 "+3V3" H 4050 1200 50 0000 C CNN
F 2 "" H 4050 1050 50 0001 C CNN
F 3 "" H 4050 1050 50 0001 C CNN
@ -281,10 +281,10 @@ F 3 "" H 4050 1050 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L GND #PWR09
L GND #PWR04
U 1 1 59CE3680
P 4050 1650
F 0 "#PWR09" H 4050 1400 50 0001 C CNN
F 0 "#PWR04" H 4050 1400 50 0001 C CNN
F 1 "GND" H 4055 1477 50 0000 C CNN
F 2 "" H 4050 1650 50 0001 C CNN
F 3 "" H 4050 1650 50 0001 C CNN
@ -296,10 +296,10 @@ Wire Wire Line
Wire Wire Line
3400 2900 3400 3000
$Comp
L GND #PWR07
L GND #PWR08
U 1 1 59CEF312
P 3400 3000
F 0 "#PWR07" H 3400 2750 50 0001 C CNN
F 0 "#PWR08" H 3400 2750 50 0001 C CNN
F 1 "GND" H 3405 2827 50 0000 C CNN
F 2 "" H 3400 3000 50 0001 C CNN
F 3 "" H 3400 3000 50 0001 C CNN
@ -329,10 +329,10 @@ F 3 "" H 1750 2700 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L +3V3 #PWR03
L +3V3 #PWR06
U 1 1 59CF2CC4
P 1750 2450
F 0 "#PWR03" H 1750 2300 50 0001 C CNN
F 0 "#PWR06" H 1750 2300 50 0001 C CNN
F 1 "+3V3" H 1765 2623 50 0000 C CNN
F 2 "" H 1750 2450 50 0001 C CNN
F 3 "" H 1750 2450 50 0001 C CNN
@ -340,10 +340,10 @@ F 3 "" H 1750 2450 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L GND #PWR04
L GND #PWR010
U 1 1 59CF2CE5
P 1750 3350
F 0 "#PWR04" H 1750 3100 50 0001 C CNN
F 0 "#PWR010" H 1750 3100 50 0001 C CNN
F 1 "GND" H 1755 3177 50 0000 C CNN
F 2 "" H 1750 3350 50 0001 C CNN
F 3 "" H 1750 3350 50 0001 C CNN

View File

@ -34,7 +34,7 @@
)
(setup
(last_trace_width 0.15)
(last_trace_width 0.25)
(user_trace_width 0.15)
(user_trace_width 0.4)
(trace_clearance 0.15)
@ -123,24 +123,24 @@
(net 27 /fpga/P5)
(net 28 /fpga/P4)
(net 29 /fpga/P17)
(net 30 "Net-(J4-Pad6)")
(net 31 "Net-(D1-Pad2)")
(net 32 /fpga/TXD)
(net 33 /fpga/RXD)
(net 34 /fpga/CLK_FPGA)
(net 35 /fpga/CLK_USBSER)
(net 36 "Net-(U4-Pad1)")
(net 37 "Net-(U3-Pad15)")
(net 38 "Net-(U3-Pad14)")
(net 39 "Net-(U3-Pad12)")
(net 40 "Net-(U3-Pad11)")
(net 41 "Net-(U3-Pad10)")
(net 42 "Net-(U3-Pad9)")
(net 43 "Net-(R10-Pad2)")
(net 44 /usbserial/VU)
(net 45 "Net-(D3-Pad1)")
(net 46 "Net-(D4-Pad1)")
(net 47 "Net-(J1-Pad4)")
(net 30 "Net-(D1-Pad2)")
(net 31 /fpga/TXD)
(net 32 /fpga/RXD)
(net 33 /fpga/CLK_FPGA)
(net 34 /fpga/CLK_USBSER)
(net 35 "Net-(U4-Pad1)")
(net 36 "Net-(U3-Pad15)")
(net 37 "Net-(U3-Pad14)")
(net 38 "Net-(U3-Pad12)")
(net 39 "Net-(U3-Pad11)")
(net 40 "Net-(U3-Pad10)")
(net 41 "Net-(U3-Pad9)")
(net 42 /usbserial/VU)
(net 43 "Net-(D3-Pad1)")
(net 44 "Net-(D4-Pad1)")
(net 45 "Net-(J1-Pad4)")
(net 46 "Net-(J2-Pad6)")
(net 47 "Net-(R2-Pad2)")
(net_class Default "This is the default net class."
(clearance 0.15)
@ -182,8 +182,8 @@
(add_net "Net-(D3-Pad1)")
(add_net "Net-(D4-Pad1)")
(add_net "Net-(J1-Pad4)")
(add_net "Net-(J4-Pad6)")
(add_net "Net-(R10-Pad2)")
(add_net "Net-(J2-Pad6)")
(add_net "Net-(R2-Pad2)")
(add_net "Net-(U3-Pad10)")
(add_net "Net-(U3-Pad11)")
(add_net "Net-(U3-Pad12)")
@ -528,7 +528,7 @@
(fp_line (start -0.2 -0.2) (end -0.2 0.2) (layer F.Fab) (width 0.1))
(fp_line (start -1.3 -0.5) (end -1.3 0.5) (layer F.SilkS) (width 0.12))
(pad 1 smd rect (at -0.8 0 270) (size 0.8 0.8) (layers F.Cu F.Paste F.Mask)
(net 45 "Net-(D3-Pad1)"))
(net 43 "Net-(D3-Pad1)"))
(pad 2 smd rect (at 0.8 0 270) (size 0.8 0.8) (layers F.Cu F.Paste F.Mask)
(net 7 +3V3))
(model ${KISYS3DMOD}/LEDs.3dshapes/LED_0603.wrl
@ -568,7 +568,7 @@
(pad 2 smd rect (at 0.8 0 270) (size 0.8 0.8) (layers F.Cu F.Paste F.Mask)
(net 7 +3V3))
(pad 1 smd rect (at -0.8 0 270) (size 0.8 0.8) (layers F.Cu F.Paste F.Mask)
(net 46 "Net-(D4-Pad1)"))
(net 44 "Net-(D4-Pad1)"))
(model ${KISYS3DMOD}/LEDs.3dshapes/LED_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
@ -581,7 +581,7 @@
(descr "Through hole straight pin header, 1x15, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x15 2.54mm single row")
(path /59CE819F/59CE37F9)
(fp_text reference J2 (at 0 2.33 180) (layer B.SilkS)
(fp_text reference J3 (at 0 2.33 180) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value Conn_Left (at 0 -37.89 180) (layer B.Fab)
@ -647,7 +647,7 @@
(descr "Through hole straight pin header, 1x15, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x15 2.54mm single row")
(path /59CE819F/59CE3A58)
(fp_text reference J3 (at 0 2.33 180) (layer B.SilkS)
(fp_text reference J4 (at 0 2.33 180) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value Conn_Right (at 0 -37.89 180) (layer B.Fab)
@ -688,7 +688,7 @@
(pad 8 thru_hole oval (at 0 -17.78 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 17 /fpga/P27))
(pad 7 thru_hole oval (at 0 -15.24 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 34 /fpga/CLK_FPGA))
(net 33 /fpga/CLK_FPGA))
(pad 6 thru_hole oval (at 0 -12.7 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 4 GND))
(pad 5 thru_hole oval (at 0 -10.16 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
@ -796,7 +796,7 @@
(pad 29 smd rect (at -0.25 -2.4 45) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)
(net 10 /fpga/JTAG_TMS))
(pad 28 smd rect (at 0.25 -2.4 45) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)
(net 34 /fpga/CLK_FPGA))
(net 33 /fpga/CLK_FPGA))
(pad 27 smd rect (at 0.75 -2.4 45) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)
(net 17 /fpga/P27))
(pad 26 smd rect (at 1.25 -2.4 45) (size 0.7 0.25) (layers F.Cu F.Paste F.Mask)
@ -892,23 +892,23 @@
(pad 16 smd rect (at 2.7 4.445 270) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
(net 7 +3V3))
(pad 15 smd rect (at 2.7 3.175 270) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
(net 37 "Net-(U3-Pad15)"))
(net 36 "Net-(U3-Pad15)"))
(pad 14 smd rect (at 2.7 1.905 270) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
(net 38 "Net-(U3-Pad14)"))
(net 37 "Net-(U3-Pad14)"))
(pad 13 smd rect (at 2.7 0.635 270) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
(net 13 /usbserial/DTR))
(pad 12 smd rect (at 2.7 -0.635 270) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
(net 39 "Net-(U3-Pad12)"))
(net 38 "Net-(U3-Pad12)"))
(pad 11 smd rect (at 2.7 -1.905 270) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
(net 40 "Net-(U3-Pad11)"))
(net 39 "Net-(U3-Pad11)"))
(pad 10 smd rect (at 2.7 -3.175 270) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
(net 41 "Net-(U3-Pad10)"))
(net 40 "Net-(U3-Pad10)"))
(pad 9 smd rect (at 2.7 -4.445 270) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
(net 42 "Net-(U3-Pad9)"))
(net 41 "Net-(U3-Pad9)"))
(pad 8 smd rect (at -2.7 -4.445 270) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
(net 14 "Net-(U3-Pad8)"))
(pad 7 smd rect (at -2.7 -3.175 270) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
(net 35 /fpga/CLK_USBSER))
(net 34 /fpga/CLK_USBSER))
(pad 6 smd rect (at -2.7 -1.905 270) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
(net 15 /usbserial/USB-))
(pad 5 smd rect (at -2.7 -0.635 270) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
@ -916,9 +916,9 @@
(pad 4 smd rect (at -2.7 0.635 270) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
(net 7 +3V3))
(pad 3 smd rect (at -2.7 1.905 270) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
(net 33 /fpga/RXD))
(net 32 /fpga/RXD))
(pad 2 smd rect (at -2.7 3.175 270) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
(net 32 /fpga/TXD))
(net 31 /fpga/TXD))
(pad 1 smd rect (at -2.7 4.445 270) (size 1.5 0.6) (layers B.Cu B.Paste B.Mask)
(net 4 GND))
(model ${KISYS3DMOD}/Housings_SOIC.3dshapes/SOIC-16_3.9x9.9mm_Pitch1.27mm.wrl
@ -933,7 +933,7 @@
(descr "Through hole straight pin header, 2x04, 2.54mm pitch, double rows")
(tags "Through hole pin header THT 2x04 2.54mm double row")
(path /59CE819F/59CE71D1)
(fp_text reference J4 (at 2.921 -2.413 180) (layer F.SilkS)
(fp_text reference J2 (at 2.921 -2.413 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value JTAG (at 1.27 9.95 90) (layer F.Fab)
@ -964,7 +964,7 @@
(pad 7 thru_hole oval (at 0 7.62 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 10 /fpga/JTAG_TMS))
(pad 6 thru_hole oval (at 2.54 5.08 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 30 "Net-(J4-Pad6)"))
(net 46 "Net-(J2-Pad6)"))
(pad 5 thru_hole oval (at 0 5.08 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 9 /fpga/JTAG_TCK))
(pad 4 thru_hole oval (at 2.54 2.54 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
@ -988,7 +988,7 @@
(tags "capacitor 0805")
(path /59CE0A28/59CE0E72)
(attr smd)
(fp_text reference C1 (at 0 -1.524) (layer B.SilkS)
(fp_text reference C5 (at 0 -1.524) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 1u (at 0 -1.75) (layer B.Fab)
@ -1024,7 +1024,7 @@
(tags "capacitor 0603")
(path /59CE0A28/59CE0D8D)
(attr smd)
(fp_text reference C2 (at 2.147 0 270) (layer B.SilkS)
(fp_text reference C6 (at 2.147 0 270) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 100n (at 0 -1.5 270) (layer B.Fab)
@ -1060,7 +1060,7 @@
(tags "capacitor 0603")
(path /59CE0A28/59CE1081)
(attr smd)
(fp_text reference C3 (at -2.552 0.127 90) (layer B.SilkS)
(fp_text reference C7 (at -2.552 0.127 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 100n (at 0 -1.5 90) (layer B.Fab)
@ -1096,7 +1096,7 @@
(tags "capacitor 0603")
(path /59CE0A28/59CE1FC1)
(attr smd)
(fp_text reference C4 (at 2.514472 0 315) (layer B.SilkS)
(fp_text reference C1 (at 2.514472 0 315) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 10n (at 0 -1.5 315) (layer B.Fab)
@ -1132,7 +1132,7 @@
(tags "capacitor 0603")
(path /59CE0A28/59CE2F41)
(attr smd)
(fp_text reference C5 (at 0.035921 1.436841 315) (layer B.SilkS)
(fp_text reference C2 (at 0.035921 1.436841 315) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 100n (at 0 -1.5 315) (layer B.Fab)
@ -1168,7 +1168,7 @@
(tags "capacitor 0603")
(path /59CE0A28/59CE300F)
(attr smd)
(fp_text reference C6 (at -2.424669 -0.089803 135) (layer B.SilkS)
(fp_text reference C3 (at -2.424669 -0.089803 135) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 10n (at 0 -1.5 135) (layer B.Fab)
@ -1204,7 +1204,7 @@
(tags "capacitor 0603")
(path /59CE0A28/59CE303F)
(attr smd)
(fp_text reference C7 (at 2.424669 -0.089803 135) (layer B.SilkS)
(fp_text reference C4 (at 2.424669 -0.089803 135) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 100n (at 0 -1.5 135) (layer B.Fab)
@ -1556,13 +1556,13 @@
(pad 5 smd rect (at 2.8 1.6 90) (size 2.3 0.5) (layers F.Cu F.Paste F.Mask)
(net 4 GND))
(pad 4 smd rect (at 2.8 0.8 90) (size 2.3 0.5) (layers F.Cu F.Paste F.Mask)
(net 47 "Net-(J1-Pad4)"))
(net 45 "Net-(J1-Pad4)"))
(pad 3 smd rect (at 2.8 0 90) (size 2.3 0.5) (layers F.Cu F.Paste F.Mask)
(net 16 /usbserial/USB+))
(pad 2 smd rect (at 2.8 -0.8 90) (size 2.3 0.5) (layers F.Cu F.Paste F.Mask)
(net 15 /usbserial/USB-))
(pad 1 smd rect (at 2.8 -1.6 90) (size 2.3 0.5) (layers F.Cu F.Paste F.Mask)
(net 44 /usbserial/VU))
(net 42 /usbserial/VU))
(model ${KISYS3DMOD}/smd.shapes3d/USB_JACK.x3d
(at (xyz -0.02362204724409449 0 0))
(scale (xyz 1 1 1))
@ -1576,7 +1576,7 @@
(tags "resistor 0603")
(path /59CE819F/59CEC5BE)
(attr smd)
(fp_text reference R3 (at 0 -1.436841 45) (layer B.SilkS)
(fp_text reference R9 (at 0 -1.436841 45) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value DNP (at 0 -1.5 45) (layer B.Fab)
@ -1612,7 +1612,7 @@
(tags "resistor 0603")
(path /59CE819F/59CE5A45)
(attr smd)
(fp_text reference R4 (at -2.159 0.4445 90) (layer F.SilkS)
(fp_text reference R6 (at -2.159 0.4445 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.5 90) (layer F.Fab)
@ -1632,7 +1632,7 @@
(effects (font (size 0.4 0.4) (thickness 0.075)))
)
(pad 2 smd rect (at 0.75 0 90) (size 0.5 0.9) (layers F.Cu F.Paste F.Mask)
(net 32 /fpga/TXD))
(net 31 /fpga/TXD))
(pad 1 smd rect (at -0.75 0 90) (size 0.5 0.9) (layers F.Cu F.Paste F.Mask)
(net 1 /fpga/TX))
(model ${KISYS3DMOD}/Resistors_SMD.3dshapes/R_0603.wrl
@ -1648,7 +1648,7 @@
(tags "resistor 0603")
(path /59CE819F/59CE5D31)
(attr smd)
(fp_text reference R5 (at -2.2225 -0.1905 90) (layer F.SilkS)
(fp_text reference R7 (at -2.2225 -0.1905 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.5 90) (layer F.Fab)
@ -1668,7 +1668,7 @@
(effects (font (size 0.4 0.4) (thickness 0.075)))
)
(pad 2 smd rect (at 0.75 0 90) (size 0.5 0.9) (layers F.Cu F.Paste F.Mask)
(net 33 /fpga/RXD))
(net 32 /fpga/RXD))
(pad 1 smd rect (at -0.75 0 90) (size 0.5 0.9) (layers F.Cu F.Paste F.Mask)
(net 2 /fpga/RX))
(model ${KISYS3DMOD}/Resistors_SMD.3dshapes/R_0603.wrl
@ -1684,7 +1684,7 @@
(tags "resistor 0603")
(path /59CE819F/59CE5D67)
(attr smd)
(fp_text reference R6 (at 0 -1.45 180) (layer F.SilkS)
(fp_text reference R8 (at 0 -1.45 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.5 180) (layer F.Fab)
@ -1720,7 +1720,7 @@
(tags "resistor 0603")
(path /59CE819F/59CEBC90)
(attr smd)
(fp_text reference R7 (at 2.159 -0.127 270) (layer F.SilkS)
(fp_text reference R4 (at 2.159 -0.127 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.5 270) (layer F.Fab)
@ -1742,7 +1742,7 @@
(pad 2 smd rect (at 0.75 0 270) (size 0.5 0.9) (layers F.Cu F.Paste F.Mask)
(net 1 /fpga/TX))
(pad 1 smd rect (at -0.75 0 270) (size 0.5 0.9) (layers F.Cu F.Paste F.Mask)
(net 45 "Net-(D3-Pad1)"))
(net 43 "Net-(D3-Pad1)"))
(model ${KISYS3DMOD}/Resistors_SMD.3dshapes/R_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
@ -1756,7 +1756,7 @@
(tags "resistor 0603")
(path /59CE819F/59CEBBCC)
(attr smd)
(fp_text reference R8 (at 0.0635 -0.0635 270) (layer F.SilkS) hide
(fp_text reference R5 (at 0.0635 -0.0635 270) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.5 270) (layer F.Fab)
@ -1778,7 +1778,7 @@
(pad 2 smd rect (at 0.75 0 270) (size 0.5 0.9) (layers F.Cu F.Paste F.Mask)
(net 2 /fpga/RX))
(pad 1 smd rect (at -0.75 0 270) (size 0.5 0.9) (layers F.Cu F.Paste F.Mask)
(net 46 "Net-(D4-Pad1)"))
(net 44 "Net-(D4-Pad1)"))
(model ${KISYS3DMOD}/Resistors_SMD.3dshapes/R_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
@ -1792,7 +1792,7 @@
(tags "resistor 0603")
(path /59CE819F/59CEA10C)
(attr smd)
(fp_text reference R9 (at 0 -1.524 180) (layer B.SilkS)
(fp_text reference R2 (at 0 -1.524 180) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 33 (at 0 -1.5 180) (layer B.Fab)
@ -1812,9 +1812,9 @@
(fp_line (start 1.25 -0.7) (end 1.25 0.7) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.25 -0.7) (end -1.25 -0.7) (layer B.CrtYd) (width 0.05))
(pad 1 smd rect (at -0.75 0 180) (size 0.5 0.9) (layers B.Cu B.Paste B.Mask)
(net 34 /fpga/CLK_FPGA))
(net 33 /fpga/CLK_FPGA))
(pad 2 smd rect (at 0.75 0 180) (size 0.5 0.9) (layers B.Cu B.Paste B.Mask)
(net 43 "Net-(R10-Pad2)"))
(net 47 "Net-(R2-Pad2)"))
(model ${KISYS3DMOD}/Resistors_SMD.3dshapes/R_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
@ -1828,7 +1828,7 @@
(tags "resistor 0603")
(path /59CE819F/59CEA1C2)
(attr smd)
(fp_text reference R10 (at 0 -1.397 90) (layer B.SilkS)
(fp_text reference R3 (at 0 -1.397 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 33 (at 0 -1.5 90) (layer B.Fab)
@ -1848,9 +1848,9 @@
(effects (font (size 0.4 0.4) (thickness 0.075)) (justify mirror))
)
(pad 2 smd rect (at 0.75 0 90) (size 0.5 0.9) (layers B.Cu B.Paste B.Mask)
(net 43 "Net-(R10-Pad2)"))
(net 47 "Net-(R2-Pad2)"))
(pad 1 smd rect (at -0.75 0 90) (size 0.5 0.9) (layers B.Cu B.Paste B.Mask)
(net 35 /fpga/CLK_USBSER))
(net 34 /fpga/CLK_USBSER))
(model ${KISYS3DMOD}/Resistors_SMD.3dshapes/R_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
@ -1891,7 +1891,7 @@
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(pad 2 smd rect (at 1.05 0 270) (size 0.8 0.9) (layers B.Cu B.Paste B.Mask)
(net 44 /usbserial/VU))
(net 42 /usbserial/VU))
(pad 1 smd rect (at -1.05 0 270) (size 0.8 0.9) (layers B.Cu B.Paste B.Mask)
(net 5 VBUS))
(model ${KISYS3DMOD}/Diodes_SMD.3dshapes/D_0805.wrl
@ -1931,7 +1931,7 @@
(pad 1 smd rect (at -0.8 0 90) (size 0.8 0.8) (layers F.Cu F.Paste F.Mask)
(net 4 GND))
(pad 2 smd rect (at 0.8 0 90) (size 0.8 0.8) (layers F.Cu F.Paste F.Mask)
(net 31 "Net-(D1-Pad2)"))
(net 30 "Net-(D1-Pad2)"))
(model ${KISYS3DMOD}/LEDs.3dshapes/LED_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
@ -1965,7 +1965,7 @@
(effects (font (size 0.4 0.4) (thickness 0.075)))
)
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View File

@ -80,10 +80,10 @@ F 3 "" H 1700 1100 50 0001 C CNN
-1 0 0 1
$EndComp
$Comp
L GND #PWR011
L GND #PWR013
U 1 1 59CE582B
P 1100 1850
F 0 "#PWR011" H 1100 1600 50 0001 C CNN
F 0 "#PWR013" H 1100 1600 50 0001 C CNN
F 1 "GND" H 1105 1677 50 0000 C CNN
F 2 "" H 1100 1850 50 0001 C CNN
F 3 "" H 1100 1850 50 0001 C CNN
@ -91,10 +91,10 @@ F 3 "" H 1100 1850 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L VBUS #PWR012
L VBUS #PWR011
U 1 1 59CE5831
P 1950 1000
F 0 "#PWR012" H 1950 850 50 0001 C CNN
F 0 "#PWR011" H 1950 850 50 0001 C CNN
F 1 "VBUS" H 1965 1173 50 0000 C CNN
F 2 "" H 1950 1000 50 0001 C CNN
F 3 "" H 1950 1000 50 0001 C CNN
@ -128,10 +128,10 @@ F 3 "" H 3850 2400 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L +3V3 #PWR013
L +3V3 #PWR012
U 1 1 59CE5E77
P 3700 1700
F 0 "#PWR013" H 3700 1550 50 0001 C CNN
F 0 "#PWR012" H 3700 1550 50 0001 C CNN
F 1 "+3V3" H 3715 1873 50 0000 C CNN
F 2 "" H 3700 1700 50 0001 C CNN
F 3 "" H 3700 1700 50 0001 C CNN