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doc: Editorial, remove draft watermark

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Markus Koch 2017-11-16 22:05:17 +01:00
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13
doc/acro.tex
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@ -8,18 +8,15 @@
\addcontentsline{toc}{chapter}{List of Abbreviations}
% Sort acronyms: (let ((sort-fold-case t)) (sort-regexp-fields nil "^[[:space:]]*\\\\acro\{\\([^}]*\\)\}.*$" "\\1" (point-min) (point-max)))
% \acro{} {}
\begin{acronym}[TDMA]
%
\acro{dtr} [DTR] {data terminal ready}
\acro{fpga} [FPGA] {field-programmable gate array}
\acro{uart} [UART] {universal asynchronous receiver / transmitter}
\acro{jtag} [JTAG] {Joint Test Action Group}
\acro{usb} [USB] {universal serial bus}
\acro{led} [LED] {light emitting diode}
\acro{io} [I/O] {input / output}
\acro{jtag} [JTAG] {Joint Test Action Group}
\acro{led} [LED] {light emitting diode}
\acro{ldo} [LDO] {low-dropout regulator}
\acro{rx} [RX] {receive}
\acro{tx} [TX] {transmit}
\acro{} [] {}
\acro{} [] {}
\acro{uart} [UART] {universal asynchronous receiver / transmitter}
\acro{usb} [USB] {universal serial bus}
\end{acronym}

68
doc/tiny-xo2-documentation.tex
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@ -5,7 +5,7 @@
% http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/MachXO23/MachXO2FamilyDataSheet.pdf?document_id=38834
\documentclass[openany,oneside]{scrbook}
\usepackage[printonlyused, withpage]{acronym}
\usepackage[printonlyused]{acronym}
\usepackage[
pdftitle={Tiny-XO2 Development Kit},
pdfauthor={Markus Koch},
@ -27,6 +27,7 @@ pdflang=en,
bookmarksnumbered=true
}
\usepackage{booktabs}
\usepackage{multirow}
\usepackage{graphicx}
\usepackage{color}
\usepackage{pdfpages}
@ -43,9 +44,12 @@ bibencoding=utf8
\addbibresource{lit.bib}
\DeclareLanguageMapping{american}{american-apa}
\usepackage{draftwatermark}
\SetWatermarkScale{5}
\SetWatermarkLightness{0.94}
\usepackage{caption}
\captionsetup{labelfont=bf}
%\usepackage{draftwatermark}
%\SetWatermarkScale{5}
%\SetWatermarkLightness{0.94}
\title{Tiny-XO2 Development Kit}
\author{Markus Koch $\langle$markus@notsyncing.net$\rangle$}
@ -59,6 +63,7 @@ bibencoding=utf8
\maketitle
\include{acro}
\acused{led}
\tableofcontents
@ -69,7 +74,7 @@ In addition to the \ac{fpga}, it provides a \ac{usb} to \ac{uart} converter and
\chapter{Hardware}
In this chapter, all available hardware functions are explained.
This chapter explains all available hardware functions.
\section{Overview}
Figure \ref{fig:overview} and Table \ref{tab:overview} show an overview of all the functions of the board.
@ -88,7 +93,7 @@ Figure \ref{fig:overview} and Table \ref{tab:overview} show an overview of all t
\begin{tabular}{ll} \toprule
1 & \acs{jtag} programming header \\
2 & Lattice LCMXO2-1200HC \acs{fpga} \\
3 & Power LED (Orange) \\
3 & Power \ac{led} (Orange) \\
4 & \acs{uart} \acs{tx} (Board $\rightarrow$ PC) \acs{led} (Red) \\
5 & \acs{uart} \acs{rx} (PC $\rightarrow$ Board) \acs{led} (Green) \\
6 & \acs{usb} socket for \acs{uart} and power \\
@ -104,7 +109,7 @@ Figure \ref{fig:overview} and Table \ref{tab:overview} show an overview of all t
\label{power}
The board can be powered either via \ac{usb} or using the \texttt{VB} pin on pin header \texttt{J3}. The input voltage can range from 5 V to 15 V \parencite[page 4]{tlv1117}. A diode between the \ac{usb} jack and the \texttt{VB} pin prevents backfeeding of current into the \ac{usb} connection.
The \texttt{3V} pins on the pin headers can be used to supply the on-board generated 3.3 V to supporting circuitry. The maximum current to be drawn from these pins is 500 mA \footnote{The maximum current of the AP1117 voltage regulator is 800 mA\parencite[page 4]{tlv1117}. Watch the temperature of the IC when drawing high amounts of current.}.
The \texttt{3V} pins on the pin headers can be used to supply the on-board generated 3.3 V to supporting circuitry. The maximum current to be drawn from these pins is 500 mA\footnote{The maximum current of the AP1117 voltage regulator is 800 mA\parencite[page 4]{tlv1117}. Watch the temperature of \texttt{U1} when drawing high amounts of current.}.
All \ac{io} pins on header \texttt{J3} use the voltage on pin \texttt{VX} as bank voltage. By populating \texttt{R9} with a zero Ohm resistor, the bank can be connected to the on-board 3.3 V supply. In this case, \texttt{VX} becomes a normal \texttt{3V} pin. See chapter \ref{ioheaders} for more details.
@ -117,23 +122,25 @@ The \ac{fpga} present on the board is a Lattice LCMXO2-1200HC-\emph{4}SG32C or L
\label{tab:fpgafeatures}
\centering
\begin{tabular}{ll} \toprule
\textbf{Property} & \textbf{Value} \\
\textbf{Property} & \textbf{Value} \\ \midrule
\ac{io} & 21* \\
LUTs & 1280 \\
Distributed RAM & 10 kbits \\
EBR SRAM & 64 kbits \\
User flash & 64 kbits \\
Hard IPs & 2x i2c, 1x SPI, 1x Timer / Counter, 1x PLL \\ \bottomrule
Hard IPs & 2x I$^2$C, 1x SPI, 1x Timer / Counter, 1x PLL \\ \bottomrule
\end{tabular}
\\ \textit{* Not all \acp{io} may be usable. Refer to chapter \ref{ioheaders}.}
\\ \textit{* Not all \acp{io} may be usable, see chapter \ref{ioheaders}.}
\end{table}
Depending on the version of the board, either speedgrade 4 or 6 are installed. Check the marking on the chip to determine which version applies.
Depending on the version of the board, either speedgrade 4 or 6 is installed. Check the marking on the chip to determine which version applies.
\section{\acs{uart} and \acsp{led}}
\label{uart}
The board features a CH340G \ac{usb}-to-\ac{uart} converter. Its \ac{tx} line is connected to pin \texttt{21}, the \ac{rx} line is connected to pin \texttt{20}. Pin \texttt{23} is connected to the DTR signal from the chip, which is pulled low as soon as the terminal is opened on the PC.
The board features a CH340G \ac{usb}-to-\ac{uart} converter. Its \ac{tx} line is connected to pin \texttt{21}, the \ac{rx} line is connected to pin \texttt{20}. Pin \texttt{23} is connected to the \ac{dtr} signal from the chip, which is pulled low as soon as the terminal is opened on the PC.
See the markings on the board for a quick reference of the pin functions.
Additionally, the \ac{rx} and \ac{tx} lines have an \ac{led} connected in parallel. Should a specific \ac{led} or \ac{uart} function be not wanted, refer to table \ref{tab:uartresistors} to see how to disable individual features.
@ -145,7 +152,7 @@ Additionally, the \ac{rx} and \ac{tx} lines have an \ac{led} connected in parall
\textbf{Resistor} & \textbf{Description} \\ \midrule
R6 & \ac{uart} \ac{tx} \\
R7 & \ac{uart} \ac{rx} \\
R8 & \ac{uart} DTR \\
R8 & \ac{uart} \ac{dtr} \\
\midrule
R4 & \ac{tx} \ac{led} \\
R5 & \ac{rx} \ac{led} \\ \bottomrule
@ -154,11 +161,11 @@ Additionally, the \ac{rx} and \ac{tx} lines have an \ac{led} connected in parall
\section{Crystal Oscillator}
\label{crystal}
The board features a 12 MHz crystal oscillator. This is used to supply the clock to the \ac{usb}-to-\ac{uart} converter and is also connected to pin \texttt{28} of the \ac{fpga}. If the 12 MHz clock signal is not needed on the \ac{fpga}, resistor \texttt{R2} can be removed to free pin \texttt{28} as a general purpose \ac{io} pin.
The board features a 12 MHz crystal oscillator. It supplies the clock to the \ac{usb}-to-\ac{uart} converter and is also connected to pin \texttt{28} of the \ac{fpga}. If the 12 MHz clock signal is not needed on the \ac{fpga}, resistor \texttt{R2} can be removed to free pin \texttt{28} as a general purpose \ac{io} pin.
\section{\acs{io} Headers}
\label{ioheaders}
The \ac{io} headers break out all available \ac{io} pins of the \ac{fpga}.
The \ac{io} headers break out all available \ac{io} pins of the \ac{fpga}. The pin number is marked next to each pin on the board.
Header \texttt{J3} has no special functions and uses \texttt{VX} as bank voltage. This voltage can be tied to the 3.3 V supply of the board by installing a zero ohm resistor for component \texttt{R9}.
@ -168,12 +175,20 @@ Header \texttt{J4} has special functions assigned to most of its pins. Refer to
\caption{\acs{io} pin special functions}
\label{tab:iofunctions}
\centering
\begin{tabular}{cll} \toprule
\textbf{Pins} & \textbf{Description} & \textbf{Note} \\ \midrule
\texttt{26} & \acs{jtag} multiplex & See chapter \ref{progopt:multiplex} \\
\texttt{29}, \texttt{30}, \texttt{31}, \texttt{01} & \acs{jtag} & See chapter \ref{progopt:always} \\
\texttt{20}, \texttt{21}, \texttt{23} & \acs{uart} & See chapter \ref{uart} \\
\texttt{28} & 12 MHz clock & See chapter \ref{crystal} \\ \bottomrule
\begin{tabular}{clll} \toprule
\textbf{Function} & \textbf{Pin} & \textbf{Name} & \textbf{Note} \\ \midrule
\acs{jtag} multiplex & \texttt{26} & $\overline{\textrm{JTAGENB}}$ & See chapter \ref{progopt:multiplex} \\ \midrule
\multirow{4}{3em}{\acs{jtag}} & \texttt{29} & TMS & \multirow{4}{8em}{See chapter \ref{progopt:always}} \\
& \texttt{30} & TCK \\
& \texttt{31} & TDI \\
& \texttt{01} & TDO \\ \midrule
\multirow{3}{3em}{\acs{uart}} & \texttt{20} & \acs{rx} & \multirow{3}{8em}{See chapter \ref{uart}} \\
& \texttt{21} & \acs{tx} \\
& \texttt{23} & \ac{dtr} \\ \midrule
Clock & \texttt{28} & 12 MHz clock & See chapter \ref{crystal} \\ \bottomrule
\end{tabular}
\end{table}
@ -212,7 +227,7 @@ To use this method, no special configuration needs to be applied in the Lattice
The following connections need to be made between the programmer and the \ac{jtag} header \texttt{J2}: TDO (\texttt{TO}), TDI (\texttt{TI}), TCK (\texttt{TC}), TMS (\texttt{TM}).
Pins 29, 30, 31 and 01 are not available as user \ac{io} in this configuration. All other pins are available as normal user \ac{io}.
Pins \texttt{29}, \texttt{30}, \texttt{31} and \texttt{01} are not available as user \acp{io} in this configuration. All other pins are available as normal user \acp{io}.
\subsection{Multiplexed \acs{jtag}}
\label{progopt:multiplex}
@ -239,11 +254,11 @@ To enable this mode, the following settings need to be configured in the \textit
\end{tabular}
\end{table}
When programming the \ac{fpga} in circuit, the user needs to ensure that all \ac{jtag} lines are high-Z when programming actions are active (when \texttt{26} (\texttt{EN}) is low). Also, the \ac{jtag} bit patterns should not affect any components attached to the \ac{jtag} pins during a programming operation.
When programming the \ac{fpga} in circuit, the user needs to ensure that all \ac{jtag} lines are high-Z during programming (when \texttt{26} (\texttt{EN}) is low). Also, the \ac{jtag} bit patterns should not affect any components attached to the \ac{jtag} pins during a programming operation.
The following connections need to be made between the programmer and the \ac{jtag} header \texttt{J2}: TDO (\texttt{TO}), TDI (\texttt{TI}), TCK (\texttt{TC}), TMS (\texttt{TM}), PROGRAMN (\texttt{EN}).
Pin \texttt{26} is not available as user \ac{io} in this configuration. Care needs to be taken when selecting which components to connect to pins \texttt{29}, \texttt{30}, \texttt{31} and \texttt{01}. All other pins are available as normal user \ac{io}.
Pin \texttt{26} is not available as user \ac{io} in this configuration. Care needs to be taken when selecting which components to connect to pins \texttt{29}, \texttt{30}, \texttt{31} and \texttt{01}. All other pins are available as normal user \acp{io}.
\subsection{\acs{uart} Bootloader}
\label{progopt:bootloader}
@ -262,7 +277,7 @@ Pin \texttt{26} is not available as user \ac{io} in this configuration. Care nee
\end{tabular}
\end{table}
All \ac{io} pins are available as user \ac{io}.
All \ac{io} pins are available as user \acp{io}.
\chapter{Appendix}
@ -273,7 +288,8 @@ All \ac{io} pins are available as user \ac{io}.
\centering
\begin{tabular}{ll} \toprule
\textbf{Version} & \textbf{Comment} \\ \midrule
2017-11-10 & Initial draft\\ \bottomrule
2017-11-16 & Editorial changes \\
2017-11-10 & Initial draft \\ \bottomrule
\end{tabular}
\end{table}