EESchema Schematic File Version 3 LIBS:power LIBS:device LIBS:transistors LIBS:conn LIBS:linear LIBS:regul LIBS:74xx LIBS:cmos4000 LIBS:adc-dac LIBS:memory LIBS:xilinx LIBS:microcontrollers LIBS:dsp LIBS:microchip LIBS:analog_switches LIBS:motorola LIBS:texas LIBS:intel LIBS:audio LIBS:interface LIBS:digital-audio LIBS:philips LIBS:display LIBS:cypress LIBS:siliconi LIBS:opto LIBS:atmel LIBS:contrib LIBS:valves LIBS:lattice LIBS:usbserial LIBS:clock LIBS:tiny-xo2-cache EELAYER 26 0 EELAYER END $Descr A4 11693 8268 encoding utf-8 Sheet 1 4 Title "Tiny-XO2" Date "2017-09-30" Rev "02" Comp "Markus Koch - notsyncing.net" Comment1 "Licensed under CC BY-SA 3.0" Comment2 "https://l.notsyncing.net/tinyxo2" Comment3 "" Comment4 "Schematic Overview" $EndDescr $Sheet S 850 900 1650 1050 U 59CE0A28 F0 "Power" 60 F1 "power.sch" 60 $EndSheet $Sheet S 4750 900 1650 1050 U 59CE3CDF F0 "usbserial" 60 F1 "usbserial.sch" 60 F2 "CLK_USBSER" I L 4750 1100 60 F3 "TXD" O L 4750 1250 60 F4 "RXD" I L 4750 1350 60 F5 "DTR" O L 4750 1500 60 $EndSheet $Sheet S 2800 900 1650 1050 U 59CE819F F0 "fpga" 60 F1 "fpga.sch" 60 F2 "CLK_USBSER" O R 4450 1100 60 F3 "TXD" I R 4450 1250 60 F4 "RXD" O R 4450 1350 60 F5 "RTS" I R 4450 1500 60 $EndSheet Wire Wire Line 4450 1100 4750 1100 Wire Wire Line 4750 1250 4450 1250 Wire Wire Line 4450 1350 4750 1350 Wire Wire Line 4750 1500 4450 1500 $EndSCHEMATC