diff --git a/fpga/hdl/bench/bench_top_manual.vhd b/fpga/hdl/bench/bench_top_manual.vhd index ad79c92..72a3a9d 100644 --- a/fpga/hdl/bench/bench_top_manual.vhd +++ b/fpga/hdl/bench/bench_top_manual.vhd @@ -73,7 +73,7 @@ begin top_inst : entity design.top port map( - clk_50m => clk, + clk_in => clk, uart_tx => uart_txd, uart_rx => uart_rxd, eth_rx_p => rx_p,