From 0545769bcdbcf95bdff54576bf09a99941ae1bb7 Mon Sep 17 00:00:00 2001 From: Markus Koch Date: Thu, 26 Sep 2024 20:03:05 +0200 Subject: [PATCH] fpga: bench: Fix top level clock pin name --- fpga/hdl/bench/bench_top_manual.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/hdl/bench/bench_top_manual.vhd b/fpga/hdl/bench/bench_top_manual.vhd index ad79c92..72a3a9d 100644 --- a/fpga/hdl/bench/bench_top_manual.vhd +++ b/fpga/hdl/bench/bench_top_manual.vhd @@ -73,7 +73,7 @@ begin top_inst : entity design.top port map( - clk_50m => clk, + clk_in => clk, uart_tx => uart_txd, uart_rx => uart_rxd, eth_rx_p => rx_p,