diff --git a/fpga/hdl/design/aps6404l_controller.vhd b/fpga/hdl/design/aps6404l_controller.vhd index c19fbfd..77d5ff7 100644 --- a/fpga/hdl/design/aps6404l_controller.vhd +++ b/fpga/hdl/design/aps6404l_controller.vhd @@ -13,6 +13,9 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity aps6404l_controller is + generic( + TOGGLE_WRAP_BOUNDARY : boolean := false + ); port( clk : in std_logic; -- Max clock 132 MHz -> 66 MHz SPI rst : in std_logic; -- @@ -204,6 +207,14 @@ begin opmode <= COMMAND; end procedure qpi_stop; + impure function POST_QPI_STATE return state_t is + begin + if TOGGLE_WRAP_BOUNDARY then + return QPI_SET_BOUNDARY; + else + return IDLE; + end if; + end function POST_QPI_STATE; begin if rst then state <= QPI_EXIT; @@ -225,7 +236,7 @@ begin state <= SPI_ENABLE_QPI when qpi_xfer(qpi_to_spi((x"9", x"9"))); when SPI_ENABLE_QPI => - state <= QPI_SET_BOUNDARY when qpi_xfer(qpi_to_spi((x"3", x"5"))); + state <= POST_QPI_STATE when qpi_xfer(qpi_to_spi((x"3", x"5"))); when QPI_SET_BOUNDARY => state <= IDLE when qpi_xfer((x"C", x"0"));