fpga: Implement single-instruction prefetching from external RAM
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fpga/hdl/bench/bench_aps6404l_wb.vhd
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177
fpga/hdl/bench/bench_aps6404l_wb.vhd
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@ -0,0 +1,177 @@
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-- -------------------------------------------------------------------------- --
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-- TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- VUnit test bench for the aps6404l Wishbone IF
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library design;
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use design.all;
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library generics;
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use generics.wishbone_pkg.all;
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library device_models;
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use device_models.all;
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library vunit_lib;
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context vunit_lib.vunit_context;
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entity bench_aps6404l_wb is
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generic(
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runner_cfg : string := runner_cfg_default
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);
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end entity bench_aps6404l_wb;
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architecture RTL of bench_aps6404l_wb is
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signal wbi_o : wishbone_slave_out;
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signal wbi_i : wishbone_slave_in;
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signal wb_o : wishbone_slave_out;
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signal wb_i : wishbone_slave_in;
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signal clk : std_logic;
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signal rst : std_logic;
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signal psram_ce_n : std_logic;
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signal psram_sclk : std_logic;
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signal psram_sio : std_logic_vector(3 downto 0);
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begin
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aps6404l_wb_inst : entity design.aps6404l_wb
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port map(
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clk => clk,
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rst => rst,
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wbi_o => wbi_o,
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wbi_i => wbi_i,
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wb_o => wb_o,
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wb_i => wb_i,
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psram_ce_n => psram_ce_n,
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psram_sclk => psram_sclk,
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psram_sio => psram_sio
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);
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aps6404l_inst : entity device_models.aps6404l
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port map(
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ce_n => psram_ce_n,
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sclk => psram_sclk,
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sio => psram_sio
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);
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test : process is
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procedure bus_write(
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signal master_o : out wishbone_master_out;
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signal master_i : in wishbone_master_in;
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constant address : in wishbone_address;
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constant data : in wishbone_data
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) is
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begin
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info("Writing to address 0x" & to_hstring(address));
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master_o.we <= '1';
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master_o.adr <= address;
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master_o.dat <= data;
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master_o.sel <= (others => '1');
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master_o.cyc <= '1';
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master_o.stb <= '1';
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loop
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wait until rising_edge(clk);
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exit when master_i.ack = '1';
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end loop;
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master_o.cyc <= '0';
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master_o.stb <= '0';
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end procedure bus_write;
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procedure bus_read(
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signal master_o : out wishbone_master_out;
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signal master_i : in wishbone_master_in;
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constant address : in wishbone_address;
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variable data : out wishbone_data
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) is
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begin
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info("Reading from address 0x" & to_hstring(address));
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master_o.we <= '0';
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master_o.adr <= address;
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master_o.sel <= (others => '1');
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master_o.cyc <= '1';
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master_o.stb <= '1';
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loop
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wait until rising_edge(clk);
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exit when master_i.ack = '1';
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end loop;
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data := master_i.dat;
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master_o.cyc <= '0';
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master_o.stb <= '0';
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end procedure bus_read;
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procedure readcheck(signal master_o : out wishbone_master_out;
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signal master_i : in wishbone_master_in;
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constant address : in wishbone_address;
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constant expected : in wishbone_data) is
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variable data : wishbone_data;
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variable time_start : time;
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begin
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time_start := now;
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bus_read(wbi_i, wbi_o, address, data);
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info("Read data: 0x" & to_hstring(data) & " after " & time'image(now - time_start));
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check(data = expected, "Data readback incorrect.");
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end procedure readcheck;
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variable data : wishbone_data;
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begin
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test_runner_setup(runner, runner_cfg);
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wbi_i.sel <= (others => '1');
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wbi_i.cyc <= '0';
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wbi_i.stb <= '0';
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wb_i.cyc <= '0';
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wb_i.stb <= '0';
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while test_suite loop
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info("Resetting DUT");
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rst <= '1';
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wait for 30 ns;
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rst <= '0';
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if run("data") then
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bus_write(wb_i, wb_o, x"00000000", x"12345678");
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bus_read(wb_i, wb_o, x"00000000", data);
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info("Read data: 0x" & to_hstring(data));
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check(data = x"12345678", "Data readback incorrect.");
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wait for 500 ns;
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elsif run("instruction") then
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bus_write(wb_i, wb_o, x"00000000", x"11223344");
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bus_write(wb_i, wb_o, x"00000004", x"55667788");
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bus_write(wb_i, wb_o, x"00000008", x"99aabbcc");
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bus_write(wb_i, wb_o, x"0000000c", x"ddeeff00");
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wait for 1 us;
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readcheck(wbi_i, wbi_o, x"00000000", x"11223344");
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wait for 1 us;
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readcheck(wbi_i, wbi_o, x"00000004", x"55667788");
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wait for 1 us;
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readcheck(wbi_i, wbi_o, x"00000008", x"99aabbcc");
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wait for 1 us;
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readcheck(wbi_i, wbi_o, x"0000000c", x"ddeeff00");
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wait for 1 us;
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end if;
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end loop;
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test_runner_cleanup(runner);
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end process test;
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test_runner_watchdog(runner, 1 ms);
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clock_driver : process
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constant period : time := 20 ns;
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begin
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clk <= '0';
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wait for period / 2;
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clk <= '1';
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wait for period / 2;
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end process clock_driver;
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end architecture RTL;
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@ -8,6 +8,9 @@
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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-- TODO: By default, some (random) value is placed in cached_address, which may corrupt data if this happens to be the
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-- first address accessesd after reset.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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@ -20,6 +23,10 @@ entity aps6404l_wb is
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clk : in std_logic;
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rst : in std_logic; --
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-- Instruction Wishbone IF (32b read access only, caches one instruction ahead)
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wbi_o : out wishbone_slave_out; -- Instruction Wishbone bus (out)
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wbi_i : in wishbone_slave_in; -- Instruction Wishbone bus (in)
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-- Wishbone IF
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wb_o : out wishbone_slave_out; -- Wishbone bus (out)
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wb_i : in wishbone_slave_in; -- Wishbone bus (in)
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@ -32,49 +39,165 @@ entity aps6404l_wb is
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end entity aps6404l_wb;
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architecture rtl of aps6404l_wb is
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signal apsc_addr : std_logic_vector(23 downto 0);
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signal apsc_data_in : std_logic_vector(7 downto 0);
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signal apsc_data_in_next : std_logic;
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signal apsc_data_out : std_logic_vector(7 downto 0);
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signal apsc_data_out_valid : std_logic;
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signal apsc_write_en : std_logic;
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signal apsc_read_en : std_logic;
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type apsc_in is record
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addr : std_logic_vector(23 downto 0);
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data_in : std_logic_vector(7 downto 0);
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write_en : std_logic;
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read_en : std_logic;
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end record apsc_in;
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type apsc_out is record
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data_in_next : std_logic;
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data_out : std_logic_vector(7 downto 0);
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data_out_valid : std_logic;
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end record apsc_out;
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signal apsc_i : apsc_in;
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signal apsc_o : apsc_out;
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signal cached_address : std_logic_vector(apsc_i.addr'range);
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signal cached_data : wishbone_data;
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signal api_i : apsc_in;
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signal api_o : apsc_out;
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signal api_request_count : integer range 0 to 2;
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signal api_bit_cnt : integer range 0 to 3;
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signal apd_i : apsc_in;
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signal apd_o : apsc_out;
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signal bit_cnt : integer range 0 to 4;
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signal data : std_logic_vector(wb_i.dat'range);
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signal ap_sel : integer range 0 to 1;
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begin
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aps6404l_controller_inst : entity work.aps6404l_controller
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port map(
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clk => clk,
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rst => rst,
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addr => apsc_addr,
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data_in => apsc_data_in,
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data_in_next => apsc_data_in_next,
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data_out => apsc_data_out,
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data_out_valid => apsc_data_out_valid,
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write_en => apsc_write_en,
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read_en => apsc_read_en,
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addr => apsc_i.addr,
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data_in => apsc_i.data_in,
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data_in_next => apsc_o.data_in_next,
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data_out => apsc_o.data_out,
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data_out_valid => apsc_o.data_out_valid,
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write_en => apsc_i.write_en,
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read_en => apsc_i.read_en,
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psram_ce_n => psram_ce_n,
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psram_sclk => psram_sclk,
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psram_sio => psram_sio
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);
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ap_arb : process(clk, rst) is
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begin
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if rst then
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ap_sel <= 0;
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elsif rising_edge(clk) then
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if ap_sel = 0 then
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if not (api_i.read_en or api_i.read_en) and (apd_i.read_en or apd_i.write_en) then
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ap_sel <= 1;
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end if;
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else
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if (apd_i.read_en nor apd_i.write_en) then -- lock until APD releases
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ap_sel <= 0;
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end if;
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end if;
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end if;
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end process ap_arb;
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ap_mux : process(all) is
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constant APSC_IN_DEFAULT : apsc_in := (
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addr => (others => '-'),
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data_in => (others => '-'),
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write_en => '0',
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read_en => '0'
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);
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constant APSC_OUT_DEFAULT : apsc_out := (
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data_in_next => '0',
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data_out => (others => '-'),
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data_out_valid => '0'
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);
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begin
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apsc_i <= APSC_IN_DEFAULT;
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api_o <= APSC_OUT_DEFAULT;
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apd_o <= APSC_OUT_DEFAULT;
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if ap_sel = 0 then
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api_o <= apsc_o;
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apsc_i <= api_i;
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else
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apd_o <= apsc_o;
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apsc_i <= apd_i;
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end if;
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end process ap_mux;
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instruction_memory_p : process(clk, rst) is
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begin
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if rst then
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wbi_o.ack <= '0';
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cached_address <= (others => '1'); -- TODO: Set cached_address to 0xFFFFFF
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api_request_count <= 0;
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elsif rising_edge(clk) then
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wbi_o.ack <= '0';
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if wbi_i.cyc and wbi_i.stb then
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if wbi_i.adr(cached_address'range) = cached_address then -- cache hit, return current immediately, retrieve next in meantime
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wbi_o.dat <= cached_data;
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wbi_o.ack <= '1';
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api_i.addr <= std_logic_vector(unsigned(wbi_i.adr(apsc_i.addr'range)) + 4);
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if not api_i.read_en then -- If we haven't yet triggered the retrieve from memory, start it now
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api_request_count <= 1;
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end if;
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else -- cache miss, retrieve current (return asap) + next
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if not api_i.read_en then -- If we haven't yet triggered the retrieve from memory, start it now
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api_i.addr <= wbi_i.adr(apsc_i.addr'range);
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api_request_count <= 2;
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end if;
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end if;
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end if;
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if api_o.data_out_valid then
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cached_data <= api_o.data_out & cached_data(cached_data'high downto 8); -- TODO: this assumes the CPU quickly processes the ACK (within one SPI byte)
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if api_bit_cnt = 3 then
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cached_address <= api_i.addr;
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if api_request_count > 0 then
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api_request_count <= api_request_count - 1;
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end if;
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api_bit_cnt <= 0;
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else
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api_bit_cnt <= api_bit_cnt + 1;
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end if;
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end if;
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if not api_i.read_en then
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api_bit_cnt <= 0;
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end if;
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end if;
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end process instruction_memory_p;
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api_i.read_en <= '1' when api_request_count > 0 else '0';
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api_i.write_en <= '0';
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wbi_o.err <= '0';
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wbi_o.rty <= '0';
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wbi_o.stall <= not wbi_o.ack;
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main : process(clk, rst) is
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variable start_addr : integer range 0 to 3;
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variable stop_addr : integer range 0 to 3;
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variable success : std_logic;
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variable we : std_logic;
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begin
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if rst then
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wb_o.ack <= '0';
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bit_cnt <= 0;
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wb_o.ack <= '0';
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bit_cnt <= 0;
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apd_i.read_en <= '0';
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apd_i.write_en <= '0';
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elsif rising_edge(clk) then
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wb_o.ack <= '0';
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if bit_cnt = 0 then
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apsc_read_en <= '0';
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apsc_write_en <= '0';
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apd_i.read_en <= '0';
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apd_i.write_en <= '0';
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start_addr := 0;
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for i in 0 to 3 loop
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@ -91,35 +214,39 @@ begin
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end if;
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end loop;
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apsc_addr <= wb_i.adr(apsc_addr'length - 1 downto 2) & std_logic_vector(to_unsigned(start_addr, 2));
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data <= wb_i.dat;
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apd_i.addr <= wb_i.adr(apsc_i.addr'length - 1 downto 2) & std_logic_vector(to_unsigned(start_addr, 2));
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data <= wb_i.dat;
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we := wb_i.we;
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if not wb_o.ack and wb_i.stb and wb_i.cyc then
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bit_cnt <= 4;
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if wb_i.we then
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wb_o.ack <= '1'; -- We can ack a write immediately
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end if;
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end if;
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else
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success := '0';
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if bit_cnt >= (4 - stop_addr) and bit_cnt <= (4 - start_addr) then
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apsc_read_en <= not wb_i.we;
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apsc_write_en <= wb_i.we;
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apd_i.read_en <= not we;
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apd_i.write_en <= we;
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else
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apsc_read_en <= '0';
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apsc_write_en <= '0';
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success := '1';
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apd_i.read_en <= '0';
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apd_i.write_en <= '0';
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success := '1';
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end if;
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if wb_i.we and apsc_data_in_next then
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if we and apd_o.data_in_next then
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success := '1';
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elsif not wb_i.we and apsc_data_out_valid then
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elsif not we and apd_o.data_out_valid then
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success := '1';
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end if;
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if success then
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bit_cnt <= bit_cnt - 1;
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wb_o.dat <= apsc_data_out & wb_o.dat(wb_o.dat'high downto 8);
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wb_o.dat <= apd_o.data_out & wb_o.dat(wb_o.dat'high downto 8);
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data <= x"--" & data(data'high downto 8);
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if bit_cnt = 1 then
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if (bit_cnt = 1) and (we = '0') then -- We only need to ack reads, writes were already acked in bit_cnt = 0
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wb_o.ack <= '1';
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end if;
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end if;
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@ -127,7 +254,7 @@ begin
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end if;
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end process main;
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apsc_data_in <= data(apsc_data_in'range);
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apd_i.data_in <= data(apsc_i.data_in'range);
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wb_o.err <= '0';
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wb_o.rty <= '0';
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@ -75,42 +75,62 @@ architecture rtl of top is
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-- System Timer
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signal irq_timer : std_logic;
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-- # Instruction Bus
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-- Wishbone interconnect (master)
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signal wb_masters_o : wishbone_slave_in_vector(1 downto 0);
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signal wb_masters_i : wishbone_slave_out_vector(wb_masters_o'range);
|
||||
alias wbi_o is wb_masters_o(0);
|
||||
alias wbi_i is wb_masters_i(0);
|
||||
alias wbd_o is wb_masters_o(1);
|
||||
alias wbd_i is wb_masters_i(1);
|
||||
signal wbi_masters_o : wishbone_slave_in_vector(0 downto 0);
|
||||
signal wbi_masters_i : wishbone_slave_out_vector(wbi_masters_o'range);
|
||||
alias wbi_o is wbi_masters_o(0);
|
||||
alias wbi_i is wbi_masters_i(0);
|
||||
|
||||
-- Wishbone interconnect (slave)
|
||||
signal wb_slaves_o : wishbone_master_in_vector(4 downto 0);
|
||||
signal wb_slaves_i : wishbone_master_out_vector(wb_slaves_o'range);
|
||||
alias wb_rom_o is wb_slaves_o(0);
|
||||
alias wb_rom_i is wb_slaves_i(0);
|
||||
alias wb_ram_o is wb_slaves_o(1);
|
||||
alias wb_ram_i is wb_slaves_i(1);
|
||||
alias wb_timer_o is wb_slaves_o(2);
|
||||
alias wb_timer_i is wb_slaves_i(2);
|
||||
alias wb_uart_o is wb_slaves_o(3);
|
||||
alias wb_uart_i is wb_slaves_i(3);
|
||||
alias wb_eth_o is wb_slaves_o(4);
|
||||
alias wb_eth_i is wb_slaves_i(4);
|
||||
signal wbi_slaves_o : wishbone_master_in_vector(1 downto 0);
|
||||
signal wbi_slaves_i : wishbone_master_out_vector(wbi_slaves_o'range);
|
||||
alias wbi_rom_o is wbi_slaves_o(0);
|
||||
alias wbi_rom_i is wbi_slaves_i(0);
|
||||
alias wbi_ram_o is wbi_slaves_o(1);
|
||||
alias wbi_ram_i is wbi_slaves_i(1);
|
||||
|
||||
-- Slave address map
|
||||
constant wishbone_addresses : wishbone_address_vector := (
|
||||
constant wishbone_instruction_addresses : wishbone_address_vector := (
|
||||
0 => x"00000000", -- Boot ROM
|
||||
1 => x"40000000", -- RAM
|
||||
2 => x"80000000", -- Timer
|
||||
3 => x"81000000", -- UART
|
||||
4 => x"82000000" -- Eth
|
||||
1 => x"40000000" -- RAM
|
||||
);
|
||||
constant wishbone_masks : wishbone_address_vector := (
|
||||
0 => x"FF000000", -- Boot ROM: 256b
|
||||
1 => x"FF000000", -- RAM: Max 16M
|
||||
2 => x"FF000000", -- Timer
|
||||
3 => x"FF000000", -- UART
|
||||
4 => x"FF000000" -- Eth
|
||||
constant wishbone_instruction_masks : wishbone_address_vector := (
|
||||
0 => x"C0000000", -- Boot ROM
|
||||
1 => x"C0000000" -- RAM
|
||||
);
|
||||
|
||||
-- # Data Bus
|
||||
-- Wishbone interconnect (master)
|
||||
signal wbd_masters_o : wishbone_slave_in_vector(0 downto 0);
|
||||
signal wbd_masters_i : wishbone_slave_out_vector(wbd_masters_o'range);
|
||||
alias wbd_o is wbd_masters_o(0);
|
||||
alias wbd_i is wbd_masters_i(0);
|
||||
|
||||
-- Wishbone interconnect (slave)
|
||||
signal wbd_slaves_o : wishbone_master_in_vector(3 downto 0);
|
||||
signal wbd_slaves_i : wishbone_master_out_vector(wbd_slaves_o'range);
|
||||
alias wb_ram_o is wbd_slaves_o(0);
|
||||
alias wb_ram_i is wbd_slaves_i(0);
|
||||
alias wb_timer_o is wbd_slaves_o(1);
|
||||
alias wb_timer_i is wbd_slaves_i(1);
|
||||
alias wb_uart_o is wbd_slaves_o(2);
|
||||
alias wb_uart_i is wbd_slaves_i(2);
|
||||
alias wb_eth_o is wbd_slaves_o(3);
|
||||
alias wb_eth_i is wbd_slaves_i(3);
|
||||
|
||||
-- Slave address map
|
||||
constant wishbone_data_addresses : wishbone_address_vector := (
|
||||
0 => x"40000000", -- RAM
|
||||
1 => x"80000000", -- Timer
|
||||
2 => x"81000000", -- UART
|
||||
3 => x"82000000" -- Eth
|
||||
);
|
||||
constant wishbone_data_masks : wishbone_address_vector := (
|
||||
0 => x"FF000000", -- RAM: Max 16M
|
||||
1 => x"FF000000", -- Timer
|
||||
2 => x"FF000000", -- UART
|
||||
3 => x"FF000000" -- Eth
|
||||
);
|
||||
|
||||
constant IN_SIMULATION : boolean := false --
|
||||
@ -199,14 +219,16 @@ begin
|
||||
port map(
|
||||
clk => clk,
|
||||
clr => clr,
|
||||
wb_o => wb_rom_o,
|
||||
wb_i => wb_rom_i
|
||||
wb_o => wbi_rom_o,
|
||||
wb_i => wbi_rom_i
|
||||
);
|
||||
|
||||
aps6404l_wb_inst : entity work.aps6404l_wb
|
||||
port map(
|
||||
clk => clk,
|
||||
rst => rst,
|
||||
wbi_o => wbi_ram_o,
|
||||
wbi_i => wbi_ram_i,
|
||||
wb_o => wb_ram_o,
|
||||
wb_i => wb_ram_i,
|
||||
psram_ce_n => psram_ce_n,
|
||||
@ -257,16 +279,28 @@ begin
|
||||
eth_tx_p <= (others => eth_tx_p_i);
|
||||
eth_tx_n <= (others => eth_tx_n_i);
|
||||
|
||||
wishbone_crossbar_inst : entity generics.wishbone_arbiter
|
||||
wishbone_crossbar_data_inst : entity generics.wishbone_arbiter
|
||||
port map(
|
||||
clk => clk,
|
||||
rst => rst,
|
||||
masters_o => wb_masters_o,
|
||||
masters_i => wb_masters_i,
|
||||
slaves_o => wb_slaves_o,
|
||||
slaves_i => wb_slaves_i,
|
||||
address => wishbone_addresses,
|
||||
mask => wishbone_masks
|
||||
masters_o => wbd_masters_o,
|
||||
masters_i => wbd_masters_i,
|
||||
slaves_o => wbd_slaves_o,
|
||||
slaves_i => wbd_slaves_i,
|
||||
address => wishbone_data_addresses,
|
||||
mask => wishbone_data_masks
|
||||
);
|
||||
|
||||
wishbone_crossbar_instruction_inst : entity generics.wishbone_arbiter
|
||||
port map(
|
||||
clk => clk,
|
||||
rst => rst,
|
||||
masters_o => wbi_masters_o,
|
||||
masters_i => wbi_masters_i,
|
||||
slaves_o => wbi_slaves_o,
|
||||
slaves_i => wbi_slaves_i,
|
||||
address => wishbone_instruction_addresses,
|
||||
mask => wishbone_instruction_masks
|
||||
);
|
||||
|
||||
eth_led_green_n <= not eth_led_green;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user