diff --git a/fpga/.library_mapping.xml b/fpga/.library_mapping.xml
new file mode 100644
index 0000000..8e77625
--- /dev/null
+++ b/fpga/.library_mapping.xml
@@ -0,0 +1,16 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/fpga/.project b/fpga/.project
new file mode 100644
index 0000000..dfad4cc
--- /dev/null
+++ b/fpga/.project
@@ -0,0 +1,46 @@
+
+
+ trashernet_soc
+
+
+
+
+
+ org.eclipse.xtext.ui.shared.xtextBuilder
+
+
+
+
+
+ com.sigasi.hdt.vhdl.ui.vhdlNature
+ org.eclipse.xtext.ui.shared.xtextNature
+ com.sigasi.hdt.verilog.ui.verilogNature
+
+
+
+ Common Libraries
+ 2
+ virtual:/virtual
+
+
+ Common Libraries/DRAG_REUSABLE_LIBRARIES_HERE.txt
+ 1
+ sigasiresource:/vhdl/readme.txt
+
+
+ Common Libraries/IEEE
+ 2
+ sigasiresource:/vhdl/2008/IEEE
+
+
+ Common Libraries/IEEE Synopsys
+ 2
+ sigasiresource:/vhdl/2008/IEEE%20Synopsys
+
+
+ Common Libraries/STD
+ 2
+ sigasiresource:/vhdl/2008/STD
+
+
+
diff --git a/fpga/.settings/com.sigasi.hdt.vhdl.version.prefs b/fpga/.settings/com.sigasi.hdt.vhdl.version.prefs
new file mode 100644
index 0000000..e224c1e
--- /dev/null
+++ b/fpga/.settings/com.sigasi.hdt.vhdl.version.prefs
@@ -0,0 +1 @@
+=2008
diff --git a/fpga/hdl/design/top.vhd b/fpga/hdl/design/top.vhd
index 7ef2cfe..dd29383 100644
--- a/fpga/hdl/design/top.vhd
+++ b/fpga/hdl/design/top.vhd
@@ -81,16 +81,16 @@ architecture rtl of top is
-- Wishbone interconnect (master)
signal wbi_masters_o : wishbone_slave_in_vector(0 downto 0);
signal wbi_masters_i : wishbone_slave_out_vector(wbi_masters_o'range);
- alias wbi_o is wbi_masters_o(0);
- alias wbi_i is wbi_masters_i(0);
+ alias wbi_o is wbi_masters_o(0);
+ alias wbi_i is wbi_masters_i(0);
-- Wishbone interconnect (slave)
signal wbi_slaves_o : wishbone_master_in_vector(1 downto 0);
signal wbi_slaves_i : wishbone_master_out_vector(wbi_slaves_o'range);
- alias wbi_rom_o is wbi_slaves_o(0);
- alias wbi_rom_i is wbi_slaves_i(0);
- alias wbi_ram_o is wbi_slaves_o(1);
- alias wbi_ram_i is wbi_slaves_i(1);
+ alias wbi_rom_o is wbi_slaves_o(0);
+ alias wbi_rom_i is wbi_slaves_i(0);
+ alias wbi_ram_o is wbi_slaves_o(1);
+ alias wbi_ram_i is wbi_slaves_i(1);
-- Slave address map
constant wishbone_instruction_addresses : wishbone_address_vector := (
@@ -106,20 +106,20 @@ architecture rtl of top is
-- Wishbone interconnect (master)
signal wbd_masters_o : wishbone_slave_in_vector(0 downto 0);
signal wbd_masters_i : wishbone_slave_out_vector(wbd_masters_o'range);
- alias wbd_o is wbd_masters_o(0);
- alias wbd_i is wbd_masters_i(0);
+ alias wbd_o is wbd_masters_o(0);
+ alias wbd_i is wbd_masters_i(0);
-- Wishbone interconnect (slave)
signal wbd_slaves_o : wishbone_master_in_vector(3 downto 0);
signal wbd_slaves_i : wishbone_master_out_vector(wbd_slaves_o'range);
- alias wb_ram_o is wbd_slaves_o(0);
- alias wb_ram_i is wbd_slaves_i(0);
- alias wb_timer_o is wbd_slaves_o(1);
- alias wb_timer_i is wbd_slaves_i(1);
- alias wb_uart_o is wbd_slaves_o(2);
- alias wb_uart_i is wbd_slaves_i(2);
- alias wb_eth_o is wbd_slaves_o(3);
- alias wb_eth_i is wbd_slaves_i(3);
+ alias wb_ram_o is wbd_slaves_o(0);
+ alias wb_ram_i is wbd_slaves_i(0);
+ alias wb_timer_o is wbd_slaves_o(1);
+ alias wb_timer_i is wbd_slaves_i(1);
+ alias wb_uart_o is wbd_slaves_o(2);
+ alias wb_uart_i is wbd_slaves_i(2);
+ alias wb_eth_o is wbd_slaves_o(3);
+ alias wb_eth_i is wbd_slaves_i(3);
-- Slave address map
constant wishbone_data_addresses : wishbone_address_vector := (