From 79b1153df7eaa761c3a68a419033c44f7d49b351 Mon Sep 17 00:00:00 2001 From: Markus Koch Date: Tue, 23 Jul 2024 18:53:17 +0200 Subject: [PATCH] env: Makefile: Add support for icetime --- fpga/Makefile | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/fpga/Makefile b/fpga/Makefile index bfd30d6..108eb52 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -28,7 +28,7 @@ CONSTRAINTS=constraints.pcf # HW Settings YOSYS_DEVICE=u -DEVICE?=--up5k # --up5k, --u4k +DEVICE?=up5k # up5k, u4k PACKAGE?=sg48 # Programmer Settings @@ -48,7 +48,10 @@ $(BUILD_DIR)/netlist-post-synthesis.json: $(VU_FLAG) $(SOURCES_VERILOG) yosys -m ghdl -p "read_verilog $(SOURCES_VERILOG); ghdl --std=08 $(GHDLINCDIRS) design.top; synth_ice40 -abc9 -device $(YOSYS_DEVICE) -top top -json $@" $(BUILD_DIR)/netlist-post-pnr.asc: $(BUILD_DIR)/netlist-post-synthesis.json $(CONSTRAINTS) - nextpnr-ice40 $(DEVICE) --package $(PACKAGE) --asc $(BUILD_DIR)/netlist-post-pnr.asc --report $(BUILD_DIR)/report.json --detailed-timing-report --json $(BUILD_DIR)/netlist-post-synthesis.json --pcf $(CONSTRAINTS) + nextpnr-ice40 --$(DEVICE) --package $(PACKAGE) --asc $(BUILD_DIR)/netlist-post-pnr.asc --report $(BUILD_DIR)/report.json --detailed-timing-report --json $(BUILD_DIR)/netlist-post-synthesis.json --pcf $(CONSTRAINTS) + +$(BUILD_DIR)/timing.rpt: $(BUILD_DIR)/netlist-post-pnr.asc $(CONSTRAINTS) + icetime -d $(DEVICE) -P $(PACKAGE) -p $(CONSTRAINTS) -mtr $@ $(BUILD_DIR)/netlist-post-pnr.asc $(BUILD_DIR)/bitstream.bin: $(BUILD_DIR)/netlist-post-pnr.asc icepack $< $@ @@ -66,3 +69,4 @@ compile_vhdl: $(VU_FLAG) synth: $(BUILD_DIR)/netlist-post-synthesis.json pnr: $(BUILD_DIR)/netlist-post-pnr.asc pack: $(BUILD_DIR)/bitstream.bin +timing: $(BUILD_DIR)/timing.rpt