diff --git a/fpga/hdl/design/uart_wb.vhd b/fpga/hdl/design/uart_wb.vhd index 870e6e1..f5d4c26 100644 --- a/fpga/hdl/design/uart_wb.vhd +++ b/fpga/hdl/design/uart_wb.vhd @@ -41,6 +41,7 @@ architecture rtl of uart_wb is signal status_register : std_logic_vector(31 downto 0); signal in_data : std_logic_vector(7 downto 0); + signal in_data_latched : std_logic_vector(in_data'range); signal in_data_valid : std_logic; signal in_data_available : std_logic; @@ -104,7 +105,7 @@ begin out_data <= wb_i.dat(out_data'range); out_data_valid <= '1'; else - wb_o.dat <= x"000000" & in_data; + wb_o.dat <= x"000000" & in_data_latched; in_data_available <= '0'; end if; end if; @@ -112,6 +113,7 @@ begin if in_data_valid then in_data_available <= '1'; + in_data_latched <= in_data; end if; end if; end process wb_if;