diff --git a/fpga/hdl/design/top.vhd b/fpga/hdl/design/top.vhd index 09b43e4..1c4cc81 100644 --- a/fpga/hdl/design/top.vhd +++ b/fpga/hdl/design/top.vhd @@ -22,7 +22,7 @@ entity top is -- System configuration F_CLK : integer := 25000000; F_CLK_PHY : integer := 50000000; - UART_BAUD : integer := 19200 + UART_BAUD : integer := 250000 ); port( clk_50m : in std_logic; -- System clock diff --git a/tools/flash.py b/tools/flash.py index 755b75a..4bb4411 100755 --- a/tools/flash.py +++ b/tools/flash.py @@ -17,7 +17,7 @@ from ast import literal_eval def eprint(*args, **kwargs): print(*args, file=sys.stderr, **kwargs) -ser = serial.Serial('/dev/ttyUSB0', 19200, timeout=2) +ser = serial.Serial('/dev/ttyUSB0', 250000, timeout=2) def sread(address, length, quiet = False): if not quiet: