fpga: Continue work on full HW support
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				@ -1,5 +1,20 @@
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#!/bin/bash
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					#!/bin/bash
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					# -------------------------------------------------------------------------- --
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					#              TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs              --
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					# -------------------------------------------------------------------------- --
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					# TODO
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					# -------------------------------------------------------------------------- --
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					# Author       : Markus Koch <markus@notsyncing.net>
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					# Contributors : None
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					# License      : Mozilla Public License (MPL) Version 2
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					# -------------------------------------------------------------------------- --
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					if [ "$1" == "flash" ]; then
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						openFPGALoader --unprotect-flash -f -c ft2232 -b ice40_generic build/bitstream.bin
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						exit 0
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					fi
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mkdir -p build
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					mkdir -p build
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cd build
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					cd build
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@ -8,7 +23,7 @@ set -e
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../run.py --compile
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					../run.py --compile
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BASEDIR=".."
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					BASEDIR=".."
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DEVICE=--u4k # --up5k, --u4k
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					DEVICE=--up5k # --up5k, --u4k
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PACKAGE=sg48
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					PACKAGE=sg48
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# Collect pre-analyzed VHDL sources
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					# Collect pre-analyzed VHDL sources
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@ -22,7 +37,7 @@ VLOGS="$VLOGS $SERV/servant/servant_ram.v $SERV/servant/servant_timer.v"
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# Synthesize and PnR
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					# Synthesize and PnR
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# -device <hx | lp | u>
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					# -device <hx | lp | u>
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yosys -m ghdl -p "read_verilog $VLOGS; ghdl --std=08 $GHDLINCDIRS design.top; synth_ice40 -abc9 -device u -top top -json netlist.json"
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					yosys -m ghdl -p "read_verilog $VLOGS; ghdl --std=08 $GHDLINCDIRS design.top; synth_ice40 -abc9 -device u -top top -json netlist.json"
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nextpnr-ice40 $DEVICE --package $PACKAGE --freq 12 --asc netlist.asc --report report.json --detailed-timing-report --json netlist.json --pcf ../constraints.pcf 
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					nextpnr-ice40 $DEVICE --package $PACKAGE --asc netlist.asc --report report.json --detailed-timing-report --json netlist.json --pcf ../constraints.pcf
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# Generate bitstream
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					# Generate bitstream
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icepack netlist.asc bitstream.bin
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					icepack netlist.asc bitstream.bin
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@ -23,9 +23,9 @@ set_io pmod[7] 31
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set_io uart_rx 37
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					set_io uart_rx 37
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set_io uart_tx 36
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					set_io uart_tx 36
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set_io clk_12m 35
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					set_io clk_50m 35
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set_io eth_rx_n 38
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					#set_io eth_rx_n 38
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set_io eth_rx_p 42
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					set_io eth_rx_p 42
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set_io eth_tx_n[0] 46
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					set_io eth_tx_n[0] 46
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@ -42,3 +42,6 @@ set_io eth_led_green 40
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set_io eth_led_orange 41
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					set_io eth_led_orange 41
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set_io led_user 34
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					set_io led_user 34
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					set_frequency clk 24
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					set_frequency clk_phy 50
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@ -73,11 +73,11 @@ begin
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	top_inst : entity design.top
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						top_inst : entity design.top
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		port map(
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							port map(
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			clk_12m    => clk,
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								clk_50m    => clk,
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			uart_tx    => uart_txd,
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								uart_tx    => uart_txd,
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			uart_rx    => uart_rxd,
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								uart_rx    => uart_rxd,
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			eth_rx_p   => rx_p,
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								eth_rx_p   => rx_p,
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			eth_rx_n   => rx_n,
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								--eth_rx_n   => rx_n,
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			eth_tx_p   => tx_p,
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								eth_tx_p   => tx_p,
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			eth_tx_n   => tx_n,
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								eth_tx_n   => tx_n,
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			psram_ce_n => psram_ce_n,
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								psram_ce_n => psram_ce_n,
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@ -11,15 +11,60 @@
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library IEEE;
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					library IEEE;
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use IEEE.std_logic_1164.all;
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					use IEEE.std_logic_1164.all;
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					library generics;
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					use generics.ice40_components.all;
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entity pll0 is
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					entity pll0 is
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						generic(
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							F_CLK     : in integer;
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							F_CLK_PHY : in integer
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						);
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	port(
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						port(
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		CLKI  : in  std_logic;
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							clk_in      : in  std_logic;
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		CLKOP : out std_logic;
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							clk_out     : out std_logic;
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		LOCK  : out std_logic);
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							clk_out_phy : out std_logic;
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							locked      : out std_logic
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						);
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end pll0;
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					end pll0;
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architecture Structure of pll0 is
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					architecture Structure of pll0 is
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						signal clk_int_osc : std_logic;
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begin
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					begin
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	CLKOP <= CLKI;
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						SB_HFOSC_inst : component SB_HFOSC
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	LOCK  <= '1';
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							generic map(
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								CLKHF_DIV => "0b01"         -- 24 MHz
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							)
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							port map(
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								CLKHFPU => '1',
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								CLKHFEN => '1',
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								CLKHF   => clk_int_osc
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							);
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						--	SB_PLL40_PAD_inst : component SB_PLL40_PAD
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						--		generic map(
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						--			FEEDBACK_PATH => "SIMPLE",
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						--			DIVR          => "0000",
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						--			DIVF          => "1000010",
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						--			DIVQ          => "100",
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						--			FILTER_RANGE  => "001"
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						--		)
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						--		port map(
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						--			RESETB     => '1',
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						--			BYPASS     => '0',
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						--			PACKAGEPIN => clk_in,
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						--			PLLOUTCORE => clk_out_phy
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						--		);
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						clk_out_phy <= clk_in;
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						-- Not clean, but it works...
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						ckdiv2 : process(clk_out_phy) is
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						begin
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							if rising_edge(clk_out_phy) then
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								clk_out <= not clk_out;
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							end if;
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						end process ckdiv2;
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						assert F_CLK = 25000000 report "clk: PLL generates clock different from specified." severity failure;
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						assert F_CLK_PHY = 50000000 report "clk_phy: PLL generates clock different from specified." severity failure;
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end Structure;
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					end Structure;
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@ -15,19 +15,17 @@ use ieee.numeric_std.all;
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library generics;
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					library generics;
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use generics.all;
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					use generics.all;
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use generics.wishbone_pkg.all;
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					use generics.wishbone_pkg.all;
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					use generics.ice40_components.all;
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library trashernet;
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use trashernet.all;
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entity top is
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					entity top is
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	generic(
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						generic(
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		-- System configuration
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							-- System configuration
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		F_CLK     : integer := 12000000;
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							F_CLK     : integer := 25000000;
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		F_CLK_PHY : integer := 48000000;
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							F_CLK_PHY : integer := 50000000;
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		UART_BAUD : integer := 9600
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							UART_BAUD : integer := 19200
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	);
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						);
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	port(
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						port(
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		clk_12m        : in    std_logic; -- System clock
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							clk_50m        : in    std_logic; -- System clock
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		-- UART
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							-- UART
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		uart_tx        : out   std_logic; -- UART TX
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							uart_tx        : out   std_logic; -- UART TX
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@ -35,44 +33,41 @@ entity top is
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		-- Trashernet
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							-- Trashernet
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		eth_rx_p       : in    std_logic; -- Ethernet RX+
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							eth_rx_p       : in    std_logic; -- Ethernet RX+
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		eth_rx_n       : in    std_logic; -- Ethernet RX-
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							--eth_rx_n       : in    std_logic; -- Ethernet RX-
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		eth_tx_p       : out   std_logic_vector(3 downto 0); -- Ethernet TX+
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							eth_tx_p       : out   std_logic_vector(3 downto 0); -- Ethernet TX+
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		eth_tx_n       : out   std_logic_vector(3 downto 0); -- Ethernet TX-
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							eth_tx_n       : out   std_logic_vector(3 downto 0); -- Ethernet TX-
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		-- LEDs
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							-- LEDs
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		eth_led_green  : out   std_logic;
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							eth_led_green  : out   std_logic;
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		eth_led_orange : out   std_logic;
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							eth_led_orange : out   std_logic;
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		led_user       : out   std_logic;
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							led_user       : out   std_logic; --
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		-- PSRAM IF
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							-- PSRAM IF
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		psram_ce_n     : out   std_logic;
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							psram_ce_n     : out   std_logic;
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		psram_sclk     : out   std_logic;
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							psram_sclk     : out   std_logic;
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		psram_sio      : inout std_logic_vector(3 downto 0);
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							psram_sio      : inout std_logic_vector(3 downto 0); --
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		-- Config Flash
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							-- Config Flash
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		flash_ce_n     : out   std_logic;
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							flash_ce_n     : out   std_logic;
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		flash_sclk     : out   std_logic;
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							flash_sclk     : out   std_logic;
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		flash_sio      : inout std_logic_vector(3 downto 0);
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							flash_sio      : inout std_logic_vector(3 downto 0); --
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		-- PMOD
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							-- PMOD
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		pmod           : inout std_logic_vector(7 downto 0)
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							pmod           : inout std_logic_vector(7 downto 0)
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	);
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						);
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end entity top;
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					end entity top;
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architecture rtl of top is
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					architecture rtl of top is
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	component pll0
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		port(
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			CLKI  : in  std_logic;
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			CLKOP : out std_logic;
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			LOCK  : out std_logic
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		);
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	end component pll0;
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	-- System
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						-- System
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	signal pll_locked : std_logic;
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						signal pll_locked : std_logic;
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	signal clk        : std_logic;
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						signal clk        : std_logic;
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						signal clk_phy    : std_logic;
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	signal rst        : std_logic := '1'; -- Asynchronous assert, synchronous release reset
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						signal rst        : std_logic := '1'; -- Asynchronous assert, synchronous release reset
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	signal clr        : std_logic := '1'; -- Fully synchronous reset
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						signal clr        : std_logic := '1'; -- Fully synchronous reset
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	signal eth_tx_p_i : std_logic;
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						signal eth_tx_p_i : std_logic;
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	signal eth_tx_n_i : std_logic;
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						signal eth_tx_n_i : std_logic;
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						signal eth_rx_p_i : std_logic;
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	-- System Timer
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						-- System Timer
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	signal irq_timer : std_logic;
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						signal irq_timer : std_logic;
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@ -120,8 +115,26 @@ architecture rtl of top is
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	                                    or true --
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						                                    or true --
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	                                    -- pragma translate_on
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						                                    -- pragma translate_on
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	                                  ;
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						                                  ;
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begin
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					begin
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						SB_IO_inst : component SB_IO
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							generic map(
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								PIN_TYPE    => "000000",
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								IO_STANDARD => "SB_LVDS_INPUT"
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							)
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							port map(
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								PACKAGE_PIN       => eth_rx_p,
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								LATCH_INPUT_VALUE => '1',
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								CLOCK_ENABLE      => '1',
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								INPUT_CLK         => clk_phy,
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								OUTPUT_CLK        => clk_phy,
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								OUTPUT_ENABLE     => '0',
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								D_OUT_0           => '0',
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								D_OUT_1           => '0',
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								D_IN_0            => eth_rx_p_i,
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								D_IN_1            => open
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							);
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	clockgen : if IN_SIMULATION generate
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						clockgen : if IN_SIMULATION generate
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		clock_driver : process
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							clock_driver : process
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			constant period : time := 1 sec / real(F_CLK);
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								constant period : time := 1 sec / real(F_CLK);
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@ -135,21 +148,31 @@ begin
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		pll_locked <= '1';
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							pll_locked <= '1';
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	else generate
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						else generate
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		pll_inst : pll0
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							pll_inst : entity work.pll0
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								generic map(
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									F_CLK     => F_CLK,
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									F_CLK_PHY => F_CLK_PHY
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								)
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			port map(
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								port map(
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				CLKI  => clk_12m,
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									clk_in      => clk_50m,
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				CLKOP => clk,
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									clk_out     => clk,
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				LOCK  => pll_locked
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									clk_out_phy => clk_phy,
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									locked      => pll_locked
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			);
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								);
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	end generate clockgen;
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						end generate clockgen;
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	por : process(clk) is
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						por : process(clk) is
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		variable reset_done : std_logic := '0';
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							variable reset_cnt : integer range 0 to 255 := 0;
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	begin
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						begin
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		if rising_edge(clk) then
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							if rising_edge(clk) then
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			rst        <= not reset_done;
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								if reset_cnt = 255 then
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			clr        <= not reset_done;
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									rst <= '0';
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			reset_done := '1';
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									clr <= '0';
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								else
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									reset_cnt := reset_cnt + 1;
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									rst       <= '1';
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 | 
									clr       <= '1';
 | 
				
			||||||
 | 
								end if;
 | 
				
			||||||
		end if;
 | 
							end if;
 | 
				
			||||||
	end process por;
 | 
						end process por;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
@ -166,7 +189,7 @@ begin
 | 
				
			|||||||
 | 
					
 | 
				
			||||||
	servant_rom_vhdl_inst : entity work.servant_ram_vhdl
 | 
						servant_rom_vhdl_inst : entity work.servant_ram_vhdl
 | 
				
			||||||
		generic map(
 | 
							generic map(
 | 
				
			||||||
			memfile   => "../../sw/bootrom/bootrom.vhex",
 | 
								memfile   => "../sw/bootrom/bootrom.vhex",
 | 
				
			||||||
			read_only => true,
 | 
								read_only => true,
 | 
				
			||||||
			adr_width => 9
 | 
								adr_width => 9
 | 
				
			||||||
		)
 | 
							)
 | 
				
			||||||
@ -200,7 +223,7 @@ begin
 | 
				
			|||||||
	uart_wb_inst : entity work.uart_wb
 | 
						uart_wb_inst : entity work.uart_wb
 | 
				
			||||||
		generic map(
 | 
							generic map(
 | 
				
			||||||
			F_CLK     => F_CLK,
 | 
								F_CLK     => F_CLK,
 | 
				
			||||||
			BAUD_RATE => 9600
 | 
								BAUD_RATE => UART_BAUD
 | 
				
			||||||
		)
 | 
							)
 | 
				
			||||||
		port map(
 | 
							port map(
 | 
				
			||||||
			clk        => clk,
 | 
								clk        => clk,
 | 
				
			||||||
@ -218,11 +241,11 @@ begin
 | 
				
			|||||||
		)
 | 
							)
 | 
				
			||||||
		port map(
 | 
							port map(
 | 
				
			||||||
			clk     => clk,
 | 
								clk     => clk,
 | 
				
			||||||
			phy_clk => clk,
 | 
								phy_clk => clk_phy,
 | 
				
			||||||
			rst     => rst,
 | 
								rst     => rst,
 | 
				
			||||||
			wb_o    => wb_eth_o,
 | 
								wb_o    => wb_eth_o,
 | 
				
			||||||
			wb_i    => wb_eth_i,
 | 
								wb_i    => wb_eth_i,
 | 
				
			||||||
			rx_p    => eth_rx_p,
 | 
								rx_p    => eth_rx_p_i,
 | 
				
			||||||
			tx_p    => eth_tx_p_i,
 | 
								tx_p    => eth_tx_p_i,
 | 
				
			||||||
			tx_n    => eth_tx_n_i
 | 
								tx_n    => eth_tx_n_i
 | 
				
			||||||
		);
 | 
							);
 | 
				
			||||||
@ -241,7 +264,13 @@ begin
 | 
				
			|||||||
			mask      => wishbone_masks
 | 
								mask      => wishbone_masks
 | 
				
			||||||
		);
 | 
							);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	eth_led_green  <= '0';
 | 
						eth_led_green  <= uart_tx;
 | 
				
			||||||
	eth_led_orange <= '1';
 | 
						eth_led_orange <= uart_rx;
 | 
				
			||||||
	led_user       <= '1';
 | 
						led_user       <= not psram_ce_n;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						flash_ce_n <= 'Z';
 | 
				
			||||||
 | 
						flash_sclk <= 'Z';
 | 
				
			||||||
 | 
						flash_sio  <= (others => 'Z');
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						pmod <= (others => 'Z');
 | 
				
			||||||
end architecture rtl;
 | 
					end architecture rtl;
 | 
				
			||||||
 | 
				
			|||||||
@ -16,6 +16,7 @@ library trashernet;
 | 
				
			|||||||
use trashernet.trashernet_pkg.all;
 | 
					use trashernet.trashernet_pkg.all;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
library generics;
 | 
					library generics;
 | 
				
			||||||
 | 
					use generics.all;
 | 
				
			||||||
use generics.wishbone_pkg.all;
 | 
					use generics.wishbone_pkg.all;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
entity trashernet_phy_wb is
 | 
					entity trashernet_phy_wb is
 | 
				
			||||||
@ -45,9 +46,15 @@ architecture RTL of trashernet_phy_wb is
 | 
				
			|||||||
	signal phy_out : phy_out_t;         -- PHY application IF (out)
 | 
						signal phy_out : phy_out_t;         -- PHY application IF (out)
 | 
				
			||||||
	signal phy_in  : phy_in_t;          -- PHY application IF (in)
 | 
						signal phy_in  : phy_in_t;          -- PHY application IF (in)
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	signal wb_adr : unsigned(2 downto 0);
 | 
						signal wb_adr : unsigned(2 downto 2);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	signal status_register : std_logic_vector(31 downto 0);
 | 
						signal status_register : std_logic_vector(31 downto 0);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						signal rx_fifo_read  : std_logic;
 | 
				
			||||||
 | 
						signal rx_fifo_full  : std_logic;
 | 
				
			||||||
 | 
						signal rx_fifo_empty : std_logic;
 | 
				
			||||||
 | 
						signal rx_fifo_data  : std_logic_vector(7 downto 0);
 | 
				
			||||||
 | 
						signal rx_fifo_usage : integer range 0 to 2047;
 | 
				
			||||||
begin
 | 
					begin
 | 
				
			||||||
	trashernet_phy_inst : entity trashernet.trashernet_phy_cdc
 | 
						trashernet_phy_inst : entity trashernet.trashernet_phy_cdc
 | 
				
			||||||
		generic map(
 | 
							generic map(
 | 
				
			||||||
@ -65,22 +72,53 @@ begin
 | 
				
			|||||||
			tx_n    => tx_n
 | 
								tx_n    => tx_n
 | 
				
			||||||
		);
 | 
							);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						rx_fifo_inst : entity generics.fifo_block
 | 
				
			||||||
 | 
							generic map(
 | 
				
			||||||
 | 
								SIZE => 2047
 | 
				
			||||||
 | 
							)
 | 
				
			||||||
 | 
							port map(
 | 
				
			||||||
 | 
								clk        => clk,
 | 
				
			||||||
 | 
								rst_a      => '0',
 | 
				
			||||||
 | 
								clr        => rst,
 | 
				
			||||||
 | 
								data_in    => phy_out.rx_data,
 | 
				
			||||||
 | 
								write      => phy_out.rx_data_valid,
 | 
				
			||||||
 | 
								commit     => not phy_out.rx_active,
 | 
				
			||||||
 | 
								abort      => '0',
 | 
				
			||||||
 | 
								full       => rx_fifo_full,
 | 
				
			||||||
 | 
								data_out   => rx_fifo_data,
 | 
				
			||||||
 | 
								data_first => open,
 | 
				
			||||||
 | 
								empty      => rx_fifo_empty,
 | 
				
			||||||
 | 
								read       => rx_fifo_read,
 | 
				
			||||||
 | 
								usage      => rx_fifo_usage
 | 
				
			||||||
 | 
							);
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	wb_adr <= unsigned(wb_i.adr(wb_adr'range));
 | 
						wb_adr <= unsigned(wb_i.adr(wb_adr'range));
 | 
				
			||||||
	wbif : process(clk, rst) is
 | 
						wbif : process(clk, rst) is
 | 
				
			||||||
 | 
							variable bytes_rxd : unsigned(15 downto 0);
 | 
				
			||||||
	begin
 | 
						begin
 | 
				
			||||||
		if rst then
 | 
							if rst then
 | 
				
			||||||
			wb_o.ack <= '0';
 | 
								wb_o.ack     <= '0';
 | 
				
			||||||
 | 
								rx_fifo_read <= '0';
 | 
				
			||||||
 | 
								bytes_rxd    := (others => '0');
 | 
				
			||||||
 | 
					
 | 
				
			||||||
		elsif rising_edge(clk) then
 | 
							elsif rising_edge(clk) then
 | 
				
			||||||
			wb_o.ack <= '0';
 | 
								wb_o.ack     <= '0';
 | 
				
			||||||
 | 
								rx_fifo_read <= '0';
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
								if (phy_out.rx_data_valid = '1') then
 | 
				
			||||||
 | 
									bytes_rxd := bytes_rxd + 1;
 | 
				
			||||||
 | 
								end if;
 | 
				
			||||||
			if (wb_i.cyc and wb_i.stb) then
 | 
								if (wb_i.cyc and wb_i.stb) then
 | 
				
			||||||
				wb_o.ack <= '1';
 | 
									wb_o.ack <= '1';
 | 
				
			||||||
				if wb_adr = 0 then
 | 
									if wb_adr = 0 then
 | 
				
			||||||
					wb_o.dat <= status_register;
 | 
										wb_o.dat <= status_register;
 | 
				
			||||||
				else
 | 
									else
 | 
				
			||||||
					wb_o.dat             <= (others => '0');
 | 
										wb_o.dat <= (others => '0');
 | 
				
			||||||
					wb_o.dat(7 downto 0) <= phy_out.rx_data; -- TODO: data
 | 
					
 | 
				
			||||||
 | 
										if wb_o.ack = '0' then
 | 
				
			||||||
 | 
											rx_fifo_read <= '1';
 | 
				
			||||||
 | 
										end if;
 | 
				
			||||||
 | 
										wb_o.dat(7 downto 0) <= rx_fifo_data;
 | 
				
			||||||
				end if;
 | 
									end if;
 | 
				
			||||||
			end if;
 | 
								end if;
 | 
				
			||||||
		end if;
 | 
							end if;
 | 
				
			||||||
@ -93,5 +131,5 @@ begin
 | 
				
			|||||||
	phy_in.tx_data_en <= '0';
 | 
						phy_in.tx_data_en <= '0';
 | 
				
			||||||
	phy_in.tx_data    <= (others => '0');
 | 
						phy_in.tx_data    <= (others => '0');
 | 
				
			||||||
 | 
					
 | 
				
			||||||
	status_register <= (x"0000000" & "000" & phy_out.carrier_detect);
 | 
						status_register <= (x"0000" & x"000" & "000" & phy_out.carrier_detect);
 | 
				
			||||||
end architecture RTL;
 | 
					end architecture RTL;
 | 
				
			||||||
 | 
				
			|||||||
@ -39,7 +39,7 @@ entity fifo_block is
 | 
				
			|||||||
		read       : in  std_logic;     -- Acknowledge that `data_out` was read. The word is removed and next one shifted from FIFO when `read and not empty`.
 | 
							read       : in  std_logic;     -- Acknowledge that `data_out` was read. The word is removed and next one shifted from FIFO when `read and not empty`.
 | 
				
			||||||
 | 
					
 | 
				
			||||||
		-- FIFO meta
 | 
							-- FIFO meta
 | 
				
			||||||
		usage      : out integer        -- Usage counter
 | 
							usage      : out integer range 0 to SIZE -- Usage counter
 | 
				
			||||||
	);
 | 
						);
 | 
				
			||||||
end fifo_block;
 | 
					end fifo_block;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
@ -68,6 +68,7 @@ begin
 | 
				
			|||||||
			read_pointer_last       <= SIZE - 1;
 | 
								read_pointer_last       <= SIZE - 1;
 | 
				
			||||||
			write_pointer_committed <= 0;
 | 
								write_pointer_committed <= 0;
 | 
				
			||||||
			current_is_first        <= '1';
 | 
								current_is_first        <= '1';
 | 
				
			||||||
 | 
								usage                   <= 0;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
		elsif rising_edge(clk) then
 | 
							elsif rising_edge(clk) then
 | 
				
			||||||
			succesful_read  := read and not empty;
 | 
								succesful_read  := read and not empty;
 | 
				
			||||||
@ -109,6 +110,7 @@ begin
 | 
				
			|||||||
			if clr then
 | 
								if clr then
 | 
				
			||||||
				read_pointer            <= 0;
 | 
									read_pointer            <= 0;
 | 
				
			||||||
				write_pointer           <= 0;
 | 
									write_pointer           <= 0;
 | 
				
			||||||
 | 
									read_pointer_last       <= SIZE - 1;
 | 
				
			||||||
				write_pointer_committed <= 0;
 | 
									write_pointer_committed <= 0;
 | 
				
			||||||
				current_is_first        <= '1';
 | 
									current_is_first        <= '1';
 | 
				
			||||||
				usage                   <= 0;
 | 
									usage                   <= 0;
 | 
				
			||||||
 | 
				
			|||||||
							
								
								
									
										88
									
								
								fpga/hdl/generics/ice40_components.vhd
									
									
									
									
									
										Normal file
									
								
							
							
						
						
									
										88
									
								
								fpga/hdl/generics/ice40_components.vhd
									
									
									
									
									
										Normal file
									
								
							@ -0,0 +1,88 @@
 | 
				
			|||||||
 | 
					library ieee;
 | 
				
			||||||
 | 
					use ieee.std_logic_1164.all;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
					package ice40_components is
 | 
				
			||||||
 | 
						component SB_PLL40_PAD
 | 
				
			||||||
 | 
							generic(
 | 
				
			||||||
 | 
								FEEDBACK_PATH : string;
 | 
				
			||||||
 | 
								DIVR          : std_logic_vector(3 downto 0);
 | 
				
			||||||
 | 
								DIVF          : std_logic_vector(6 downto 0);
 | 
				
			||||||
 | 
								DIVQ          : std_logic_vector(2 downto 0);
 | 
				
			||||||
 | 
								FILTER_RANGE  : std_logic_vector(2 downto 0)
 | 
				
			||||||
 | 
							);
 | 
				
			||||||
 | 
							port(
 | 
				
			||||||
 | 
								RESETB     : in  std_logic;
 | 
				
			||||||
 | 
								BYPASS     : in  std_logic;
 | 
				
			||||||
 | 
								PACKAGEPIN : in  std_logic;
 | 
				
			||||||
 | 
								PLLOUTCORE : out std_logic
 | 
				
			||||||
 | 
							);
 | 
				
			||||||
 | 
						end component SB_PLL40_PAD;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						component SB_PLL40_CORE
 | 
				
			||||||
 | 
							generic(
 | 
				
			||||||
 | 
								FEEDBACK_PATH : string := "SIMPLE";
 | 
				
			||||||
 | 
								--			DELAY_ADJUSTMENT_MODE_FEEDBACK : string                       := "FIXED";
 | 
				
			||||||
 | 
								--			DELAY_ADJUSTMENT_MODE_RELATIVE : string                       := "FIXED";
 | 
				
			||||||
 | 
								--			PLLOUT_SELECT                  : string                       := "GENCLK";
 | 
				
			||||||
 | 
								--			SHIFTREG_DIV_MODE              : std_logic;
 | 
				
			||||||
 | 
								--			FDA_FEEDBACK                   : std_logic_vector(3 downto 0) := "1111";
 | 
				
			||||||
 | 
								--			FDA_RELATIVE                   : std_logic_vector(3 downto 0) := "1111";
 | 
				
			||||||
 | 
								DIVR          : std_logic_vector(3 downto 0);
 | 
				
			||||||
 | 
								DIVF          : std_logic_vector(6 downto 0);
 | 
				
			||||||
 | 
								DIVQ          : std_logic_vector(2 downto 0);
 | 
				
			||||||
 | 
								FILTER_RANGE  : std_logic_vector(2 downto 0)
 | 
				
			||||||
 | 
								--			ENABLE_ICEGATE                 : std_logic                    := '0';
 | 
				
			||||||
 | 
								--			TEST_MODE                      : std_logic                    := '0'
 | 
				
			||||||
 | 
							);
 | 
				
			||||||
 | 
							port(
 | 
				
			||||||
 | 
								REFERENCECLK : in  std_logic;
 | 
				
			||||||
 | 
								--			PLLOUTCORE      : out std_logic;
 | 
				
			||||||
 | 
								PLLOUTGLOBAL : out std_logic;
 | 
				
			||||||
 | 
								--			EXTFEEDBACK     : in  std_logic;
 | 
				
			||||||
 | 
								--			DYNAMICDELAY    : in  std_logic_vector(7 downto 0);
 | 
				
			||||||
 | 
								LOCK         : out std_logic;
 | 
				
			||||||
 | 
								BYPASS       : in  std_logic;
 | 
				
			||||||
 | 
								RESETB       : in  std_logic
 | 
				
			||||||
 | 
								--			LATCHINPUTVALUE : in  std_logic;
 | 
				
			||||||
 | 
								--			SDO             : out std_logic;
 | 
				
			||||||
 | 
								--			SDI             : in  std_logic;
 | 
				
			||||||
 | 
								--			SCLK            : in  std_logic
 | 
				
			||||||
 | 
							);
 | 
				
			||||||
 | 
						end component SB_PLL40_CORE;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						component SB_HFOSC
 | 
				
			||||||
 | 
							generic(
 | 
				
			||||||
 | 
								CLKHF_DIV : string
 | 
				
			||||||
 | 
							);
 | 
				
			||||||
 | 
							port(
 | 
				
			||||||
 | 
								CLKHFPU : in  std_logic;
 | 
				
			||||||
 | 
								CLKHFEN : in  std_logic;
 | 
				
			||||||
 | 
								CLKHF   : out std_logic
 | 
				
			||||||
 | 
							);
 | 
				
			||||||
 | 
						end component SB_HFOSC;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						COMPONENT SB_IO IS
 | 
				
			||||||
 | 
							GENERIC(
 | 
				
			||||||
 | 
								PIN_TYPE    : std_logic_vector(5 downto 0) := "000000";
 | 
				
			||||||
 | 
								IO_STANDARD : string                       := "SB_LVDS_INPUT"
 | 
				
			||||||
 | 
							);
 | 
				
			||||||
 | 
							PORT(
 | 
				
			||||||
 | 
								PACKAGE_PIN       : in  std_logic;
 | 
				
			||||||
 | 
								LATCH_INPUT_VALUE : in  std_logic;
 | 
				
			||||||
 | 
								CLOCK_ENABLE      : in  std_logic;
 | 
				
			||||||
 | 
								INPUT_CLK         : in  std_logic;
 | 
				
			||||||
 | 
								OUTPUT_CLK        : in  std_logic;
 | 
				
			||||||
 | 
								OUTPUT_ENABLE     : in  std_logic;
 | 
				
			||||||
 | 
								D_OUT_0           : in  std_logic;
 | 
				
			||||||
 | 
								D_OUT_1           : in  std_logic;
 | 
				
			||||||
 | 
								D_IN_0            : out std_logic;
 | 
				
			||||||
 | 
								D_IN_1            : out std_logic
 | 
				
			||||||
 | 
							);
 | 
				
			||||||
 | 
						END COMPONENT SB_IO;
 | 
				
			||||||
 | 
					
 | 
				
			||||||
 | 
						component SB_GB
 | 
				
			||||||
 | 
							port(
 | 
				
			||||||
 | 
								USER_SIGNAL_TO_GLOBAL_BUFFER : in  std_logic;
 | 
				
			||||||
 | 
								GLOBAL_BUFFER_OUTPUT         : out std_logic);
 | 
				
			||||||
 | 
						end component;
 | 
				
			||||||
 | 
					end package ice40_components;
 | 
				
			||||||
@ -1 +1 @@
 | 
				
			|||||||
Subproject commit da7e329939d12e853acbd7636701350babf5e3f4
 | 
					Subproject commit 21a0d0e69aeacf9747bfac0262e0d7ca30a691d9
 | 
				
			||||||
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