diff --git a/fpga/hdl/design/trashernet_phy_wb.vhd b/fpga/hdl/design/trashernet_phy_wb.vhd index 73996a3..4172561 100644 --- a/fpga/hdl/design/trashernet_phy_wb.vhd +++ b/fpga/hdl/design/trashernet_phy_wb.vhd @@ -50,11 +50,13 @@ architecture RTL of trashernet_phy_wb is signal status_register : std_logic_vector(31 downto 0); - signal rx_fifo_read : std_logic; - signal rx_fifo_full : std_logic; - signal rx_fifo_empty : std_logic; - signal rx_fifo_data : std_logic_vector(7 downto 0); - signal rx_fifo_usage : integer range 0 to 2047; + signal rx_fifo_read : std_logic; + signal rx_fifo_data : std_logic_vector(7 downto 0); + + signal tx_fifo_write : std_logic; + signal tx_fifo_commit : std_logic; + signal tx_fifo_empty : std_logic; + signal tx_fifo_data : std_logic_vector(7 downto 0); begin trashernet_phy_inst : entity trashernet.trashernet_phy_cdc generic map( @@ -84,39 +86,68 @@ begin write => phy_out.rx_data_valid, commit => not phy_out.rx_active, abort => '0', - full => rx_fifo_full, + full => open, data_out => rx_fifo_data, data_first => open, - empty => rx_fifo_empty, + empty => open, read => rx_fifo_read, - usage => rx_fifo_usage + usage => open + ); + + tx_fifo_inst : entity generics.fifo_block + generic map( + SIZE => 2047 + ) + port map( + clk => clk, + rst_a => '0', + clr => rst, + data_in => wb_i.dat(7 downto 0), + write => tx_fifo_write, + commit => tx_fifo_commit, + abort => '0', + full => open, + data_out => tx_fifo_data, + data_first => open, + empty => tx_fifo_empty, + read => phy_out.tx_data_ack, + usage => open ); wb_adr <= unsigned(wb_i.adr(wb_adr'range)); wbif : process(clk, rst) is - variable bytes_rxd : unsigned(15 downto 0); begin if rst then - wb_o.ack <= '0'; - rx_fifo_read <= '0'; - bytes_rxd := (others => '0'); + wb_o.ack <= '0'; + rx_fifo_read <= '0'; + tx_fifo_write <= '0'; + tx_fifo_commit <= '0'; elsif rising_edge(clk) then - wb_o.ack <= '0'; - rx_fifo_read <= '0'; + wb_o.ack <= '0'; + rx_fifo_read <= '0'; + tx_fifo_write <= '0'; + tx_fifo_commit <= '0'; - if (phy_out.rx_data_valid = '1') then - bytes_rxd := bytes_rxd + 1; - end if; if (wb_i.cyc and wb_i.stb) then wb_o.ack <= '1'; + if wb_adr = 0 then wb_o.dat <= status_register; + if wb_o.ack = '0' then + if wb_i.we = '1' then + tx_fifo_commit <= '1'; + end if; + end if; else wb_o.dat <= (others => '0'); if wb_o.ack = '0' then - rx_fifo_read <= '1'; + if wb_i.we = '1' then + tx_fifo_write <= '1'; + else + rx_fifo_read <= '1'; + end if; end if; wb_o.dat(7 downto 0) <= rx_fifo_data; end if; @@ -128,8 +159,8 @@ begin wb_o.rty <= '1'; wb_o.stall <= '0'; - phy_in.tx_data_en <= '0'; - phy_in.tx_data <= (others => '0'); + phy_in.tx_data_en <= not tx_fifo_empty; -- FIXME: this does not care about inter-packet gaps indicated by `data_first` + phy_in.tx_data <= tx_fifo_data; status_register <= (x"0000" & x"000" & "000" & phy_out.carrier_detect); end architecture RTL;