diff --git a/fpga/hdl/design/trashernet_phy_wb.vhd b/fpga/hdl/design/trashernet_phy_wb.vhd index 5f3e20a..780478f 100644 --- a/fpga/hdl/design/trashernet_phy_wb.vhd +++ b/fpga/hdl/design/trashernet_phy_wb.vhd @@ -220,35 +220,42 @@ begin x"000" & "0" & (not tx_fifo_empty) & (not rx_fifo_empty) & phy_out.carrier_detect); ledstretch : process(clk) is - constant CMAX : integer := integer(0.2 / (1.0 / real(F_CLK))); - variable cnt : integer range 0 to CMAX; + constant CMAX : integer := integer(0.1 / (1.0 / real(F_CLK))); + constant CMIN : integer := -integer(0.1 / (1.0 / real(F_CLK))); + variable cnt : integer range CMIN to CMAX; begin if rising_edge(clk) then - if cnt = 0 then + if cnt = CMIN then led_rx <= phy_out.carrier_detect; if phy_out.rx_active then - cnt := CMAX; + cnt := CMAX; + led_rx <= not phy_out.carrier_detect; end if; - else - led_rx <= '0'; + elsif cnt = 0 then + led_rx <= phy_out.carrier_detect; cnt := cnt - 1; + else + cnt := cnt - 1; end if; end if; end process ledstretch; ledstretch2 : process(clk) is - constant CMAX : integer := integer(0.2 / (1.0 / real(F_CLK))); - variable cnt : integer range 0 to CMAX; + constant CMAX : integer := integer(0.1 / (1.0 / real(F_CLK))); + constant CMIN : integer := -integer(0.1 / (1.0 / real(F_CLK))); + variable cnt : integer range CMIN to CMAX; begin if rising_edge(clk) then - if cnt = 0 then - led_tx <= '0'; + if cnt = CMIN then if phy_out.tx_active then - cnt := CMAX; + cnt := CMAX; + led_tx <= '1'; end if; - else - led_tx <= '1'; + elsif cnt = 0 then + led_tx <= '0'; cnt := cnt - 1; + else + cnt := cnt - 1; end if; end if; end process ledstretch2;