diff --git a/fpga/Makefile b/fpga/Makefile
index 46eb5fd..339b237 100644
--- a/fpga/Makefile
+++ b/fpga/Makefile
@@ -46,6 +46,7 @@ $(BUILD_DIR)/netlist-post-synthesis.json: $(VU_FLAG) $(SOURCES_VERILOG)
 	# Collect GHDL sources from VUnit
 	$(eval GHDLINCDIRS=$(shell find "$(VU_DIR)/ghdl/libraries" -maxdepth 1 -mindepth 1 -type d | sed "s/^/-P/" | tr '\n' ' '))
 	yosys -m ghdl -p "read_verilog $(SOURCES_VERILOG); ghdl --std=08 $(GHDLINCDIRS) design.top; synth_ice40 -abc9 -device $(YOSYS_DEVICE) -top top -json $@"
+	./patch_asserts.sh $@
 
 $(BUILD_DIR)/netlist-post-pnr.asc: $(BUILD_DIR)/netlist-post-synthesis.json $(CONSTRAINTS)
 	nextpnr-ice40 --$(DEVICE) --package $(PACKAGE) --asc $(BUILD_DIR)/netlist-post-pnr.asc --report $(BUILD_DIR)/report.json --detailed-timing-report --json $(BUILD_DIR)/netlist-post-synthesis.json --pcf $(CONSTRAINTS)
diff --git a/fpga/patch_asserts.sh b/fpga/patch_asserts.sh
new file mode 100755
index 0000000..1d46993
--- /dev/null
+++ b/fpga/patch_asserts.sh
@@ -0,0 +1,14 @@
+#!/bin/bash
+
+file="$1"
+echo "Removing \$assert from $file..."
+
+LOCS=`grep -n '$assert' "$file" | sed 's/:.*//g'`
+
+IFS=$'\n'
+for LOC in $LOCS; do
+	START=$(($LOC-2))
+	END=$(($LOC+14))
+	echo "Deleting lines $START -> $END"
+	sed -i -e "${START},${END}d" "$file"
+done