-- -------------------------------------------------------------------------- -- -- TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs -- -- -------------------------------------------------------------------------- -- -- TODO -- -------------------------------------------------------------------------- -- -- Author : Markus Koch -- Contributors : None -- License : Mozilla Public License (MPL) Version 2 -- -------------------------------------------------------------------------- -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library generics; use generics.wishbone_pkg.all; entity servant_ram_vhdl is generic( memfile : string := "data/empty.hex"; read_only : boolean := false; adr_width : integer := 16 ); port( clk : in std_logic; -- CPU and bus clock clr : in std_logic; -- Synchronous reset wb_o : out wishbone_slave_out; -- Wishbone bus (out) wb_i : in wishbone_slave_in -- Wishbone bus (in) ); end entity servant_ram_vhdl; architecture rtl of servant_ram_vhdl is component servant_ram generic( depth : integer; aw : integer; memfile : string ); port( i_wb_clk : in std_logic; i_wb_rst : in std_logic; i_wb_adr : in std_logic_vector; i_wb_dat : in std_logic_vector; i_wb_sel : in std_logic_vector; i_wb_we : in std_logic; i_wb_cyc : in std_logic; o_wb_rdt : out std_logic_vector; o_wb_ack : out std_logic ); end component servant_ram; begin servant_ram_inst : component servant_ram generic map( depth => 2 ** adr_width, aw => adr_width, memfile => memfile ) port map( i_wb_clk => clk, i_wb_rst => clr, i_wb_adr => wb_i.adr(adr_width - 1 downto 2), i_wb_dat => wb_i.dat, i_wb_sel => wb_i.sel, i_wb_we => wb_i.we, i_wb_cyc => wb_i.cyc and wb_i.stb, o_wb_rdt => wb_o.dat, o_wb_ack => wb_o.ack ); wb_o.rty <= '0'; wb_o.err <= '0'; wb_o.stall <= '0'; rowarn : process(clk) is begin if rising_edge(clk) then if wb_i.cyc and wb_i.stb then if (unsigned(wb_i.adr) > 2 ** adr_width - 1) then report "ERROR: Out of bounds for " & servant_ram_vhdl'path_name & " @0x" & to_hstring(wb_i.adr) severity error; end if; if (wb_i.we = '1' and read_only) then report "ERROR: Write access to ROM @0x" & to_hstring(wb_i.adr) severity warning; end if; end if; end if; end process rowarn; end architecture rtl;