-- -------------------------------------------------------------------------- -- -- TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs -- -- -------------------------------------------------------------------------- -- -- TODO -- -------------------------------------------------------------------------- -- -- Author : Markus Koch -- Contributors : None -- License : Mozilla Public License (MPL) Version 2 -- -------------------------------------------------------------------------- -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; package wishbone_pkg is constant WISHBONE_ADDRESS_WIDTH : integer := 32; constant WISHBONE_DATA_WIDTH : integer := 32; subtype wishbone_address is std_logic_vector(WISHBONE_ADDRESS_WIDTH - 1 downto 0); subtype wishbone_data is std_logic_vector(WISHBONE_DATA_WIDTH - 1 downto 0); subtype wishbone_byte_select is std_logic_vector((WISHBONE_ADDRESS_WIDTH / 8) - 1 downto 0); subtype wishbone_cycle_type is std_logic_vector(2 downto 0); subtype wishbone_burst_type is std_logic_vector(1 downto 0); type wishbone_master_out is record cyc : std_logic; stb : std_logic; adr : wishbone_address; sel : wishbone_byte_select; we : std_logic; dat : wishbone_data; end record wishbone_master_out; subtype wishbone_slave_in is wishbone_master_out; type wishbone_slave_out is record ack : std_logic; err : std_logic; rty : std_logic; stall : std_logic; dat : wishbone_data; end record wishbone_slave_out; subtype wishbone_master_in is wishbone_slave_out; type wishbone_master_out_vector is array (natural range <>) of wishbone_master_out; type wishbone_slave_out_vector is array (natural range <>) of wishbone_slave_out; subtype wishbone_slave_in_vector is wishbone_master_out_vector; subtype wishbone_master_in_vector is wishbone_slave_out_vector; type wishbone_address_vector is array (natural range <>) of wishbone_address; type wishbone_data_vector is array (natural range <>) of wishbone_data; end wishbone_pkg;