-- -------------------------------------------------------------------------- -- -- TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs -- -- -------------------------------------------------------------------------- -- -- TODO -- -------------------------------------------------------------------------- -- -- Author : Markus Koch -- Contributors : None -- License : Mozilla Public License (MPL) Version 2 -- -------------------------------------------------------------------------- -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library generics; use generics.wishbone_pkg.all; entity servant_timer_vhdl is port( clk : in std_logic; -- CPU and bus clock clr : in std_logic; -- Synchronous clear (CPU reset) wb_o : out wishbone_slave_out; -- Wishbone bus (out) wb_i : in wishbone_slave_in; -- Wishbone bus (in) irq : out std_logic -- System Timer Interrupt ); end entity servant_timer_vhdl; architecture rtl of servant_timer_vhdl is component servant_timer generic( WIDTH : integer ); port( i_clk : in std_logic; i_rst : in std_logic; o_irq : out std_logic; i_wb_dat : in std_logic_vector; i_wb_we : in std_logic; i_wb_cyc : in std_logic; o_wb_dat : out std_logic_vector ); end component servant_timer; begin servant_timer_inst : component servant_timer generic map( WIDTH => 32 ) port map( i_clk => clk, i_rst => clr, o_irq => irq, i_wb_dat => wb_i.dat, i_wb_we => wb_i.we, i_wb_cyc => wb_i.cyc and wb_i.stb, o_wb_dat => wb_o.dat ); wb_o.ack <= '1'; wb_o.rty <= '0'; wb_o.err <= '0'; wb_o.stall <= '0'; end architecture rtl;