-- -------------------------------------------------------------------------- -- -- TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs -- -- -------------------------------------------------------------------------- -- -- TODO -- -------------------------------------------------------------------------- -- -- Author : Markus Koch -- Contributors : None -- License : Mozilla Public License (MPL) Version 2 -- -------------------------------------------------------------------------- -- library IEEE; use IEEE.std_logic_1164.all; library generics; use generics.ice40_components.all; entity pll0 is generic( F_IN : in integer; F_CLK : in integer; F_CLK_PHY : in integer ); port( clk_in : in std_logic; clk_out : out std_logic; clk_out_phy : out std_logic; locked : out std_logic ); end pll0; architecture Structure of pll0 is signal clk_out_i : std_logic; begin -- Not clean, but it works... ckdiv2 : process(clk_out_phy) is begin if rising_edge(clk_out_phy) then clk_out_i <= not clk_out_i; end if; end process ckdiv2; SB_GB_inst : component SB_GB port map( USER_SIGNAL_TO_GLOBAL_BUFFER => clk_out_i, GLOBAL_BUFFER_OUTPUT => clk_out ); SB_GB2_inst : component SB_GB port map( USER_SIGNAL_TO_GLOBAL_BUFFER => clk_in, GLOBAL_BUFFER_OUTPUT => clk_out_phy ); assert F_IN = 50000000 report "clk_in: PLL expects clock different from specified." severity failure; assert F_CLK = 25000000 report "clk: PLL generates clock different from specified." severity failure; assert F_CLK_PHY = 50000000 report "clk_phy: PLL generates clock different from specified." severity failure; end Structure;