# -------------------------------------------------------------------------- --
#              TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs              --
# -------------------------------------------------------------------------- --
# TODO
# -------------------------------------------------------------------------- --
# Author       : Markus Koch <markus@notsyncing.net>
# Contributors : None
# License      : Mozilla Public License (MPL) Version 2
# -------------------------------------------------------------------------- --

BUILD_DIR=./build
VU_DIR=$(BUILD_DIR)/vunit_out
VU_FLAG=$(VU_DIR)/flag

# Collect VHDL sources using VUnit
SOURCES_VHDL=$(shell VUNIT_SIMULATOR=ghdl ./run_physical.py -o $(VU_DIR) -f 2>/dev/null | sed -n 's/^\w\+, \(.\+\)$$/\1/p')

# Collect Verilog sources using bash
SERV_DIR=hdl/serv
SOURCES_VERILOG=$(SERV_DIR)/rtl/*.v
SOURCES_VERILOG+=$(SERV_DIR)/servant/servant_ram.v $(SERV_DIR)/servant/servant_timer.v

# Miscellaneous sources that when changed must trigger a rebuild
SOURCES_MISC=../sw/bootrom/bootrom.vhex

# Constraints
CONSTRAINTS=constraints.pcf

# HW Settings
YOSYS_DEVICE=u
DEVICE?=up5k # up5k, u4k
PACKAGE?=sg48

# Programmer Settings
PROGRAMMER=ft2232

# ---------------------------------------------------------------------------- #

default: $(BUILD_DIR)/bitstream.bin

$(VU_FLAG): $(SOURCES_VHDL) $(SOURCES_MISC)
	VUNIT_SIMULATOR=ghdl ./run_physical.py --compile -o $(VU_DIR)
	touch $@

$(BUILD_DIR)/netlist-post-synthesis.json: $(VU_FLAG) $(SOURCES_VERILOG)
	# Collect GHDL sources from VUnit
	$(eval GHDLINCDIRS=$(shell find "$(VU_DIR)/ghdl/libraries" -maxdepth 1 -mindepth 1 -type d | sed "s/^/-P/" | tr '\n' ' '))
	yosys -m ghdl -p "read_verilog $(SOURCES_VERILOG); ghdl --std=08 $(GHDLINCDIRS) design.top; synth_ice40 -abc9 -device $(YOSYS_DEVICE) -top top -json $@"
	./patch_asserts.sh $@

$(BUILD_DIR)/netlist-post-pnr.asc: $(BUILD_DIR)/netlist-post-synthesis.json $(CONSTRAINTS)
	nextpnr-ice40 --$(DEVICE) --package $(PACKAGE) --asc $(BUILD_DIR)/netlist-post-pnr.asc --report $(BUILD_DIR)/report.json --detailed-timing-report --json $(BUILD_DIR)/netlist-post-synthesis.json --pcf $(CONSTRAINTS)

$(BUILD_DIR)/timing.rpt: $(BUILD_DIR)/netlist-post-pnr.asc $(CONSTRAINTS)
	icetime -d $(DEVICE) -P $(PACKAGE) -p $(CONSTRAINTS) -mtr $@ $(BUILD_DIR)/netlist-post-pnr.asc

$(BUILD_DIR)/bitstream.bin: $(BUILD_DIR)/netlist-post-pnr.asc
	icepack $< $@

flash: $(BUILD_DIR)/bitstream.bin
	openFPGALoader --unprotect-flash -f -c $(PROGRAMMER) -b ice40_generic $<

clean:
	# Build artifacts
	rm -rf $(BUILD_DIR)
	# Simulation artifacts
	rm -rf vunit_out
	rm -rf wave.fst*

simulation:
	./run.py

.phony: flash clean simulation

# Useful aliases
compile_vhdl: $(VU_FLAG)
synth: $(BUILD_DIR)/netlist-post-synthesis.json
pnr: $(BUILD_DIR)/netlist-post-pnr.asc
pack: $(BUILD_DIR)/bitstream.bin
timing: $(BUILD_DIR)/timing.rpt