#!/usr/bin/env python

from vunit import VUnit
import os
import pathlib
import subprocess
import pathlib

libraries = {
	# Design files
	os.path.realpath(os.path.join(__file__, "..")) : {
		"bench",
		"design",
		"device_models",
		"generics",
		"serv",
		"neorv32",
		"trashernet"
	}
}

project_dir=pathlib.Path(__file__).parent.resolve()

libs = {}

vu = VUnit.from_argv(compile_builtins=False)
vu.add_vhdl_builtins()

for base_path in libraries:
	for library_name in libraries[base_path]:
		libs[library_name] = vu.add_library(library_name)

		if type(libraries[base_path]) is dict: # Manually specified files
			print("direct")
			for filename in libraries[base_path][library_name]:
				libs[library_name].add_source_files(os.path.join(base_path, filename))
		else: # Auto-detect files
			print(f"Importing: {library_name}")
			if library_name == "trashernet": # Special case: Trashernet submodule
				path = os.path.join(base_path, "hdl", library_name, library_name, "*.vhd")
				libs[library_name].add_source_files(path)
			elif library_name == "neorv32": # Special case: NEORV32 submodule
				path = os.path.join(base_path, "hdl", library_name, "rtl", "core", "*.vhd")
				libs[library_name].add_source_files(path)
			elif library_name == "serv": # Special case: SERV submodule
				print("Skipping SERV. It's Verilog.")
			else: # Normal lib
				path = os.path.join(base_path, "hdl", library_name)
				if os.path.exists(path):
					path=os.path.join(path, "*.vhd")
					libs[library_name].add_source_files(path)

# If we don't already use our own OSVVM implementation, add the default one.
if not "osvvm" in libs:
	vu.add_osvvm()

vu.add_compile_option("ghdl.a_flags", ["-frelaxed", "-fsynopsys"])
vu.add_compile_option("nvc.a_flags", ["--relaxed"])
#vu.set_sim_option("nvc.elab_flags", ["-O3"])
vu.set_sim_option("nvc.heap_size", "256M")
vu.set_sim_option("nvc.sim_flags", ["--format=fst", "--wave=wave.fst", "--dump-arrays"])

vu.main()