-- -------------------------------------------------------------------------- -- -- TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs -- -- -------------------------------------------------------------------------- -- -- TODO -- -------------------------------------------------------------------------- -- -- Author : Markus Koch -- Contributors : None -- License : Mozilla Public License (MPL) Version 2 -- -------------------------------------------------------------------------- -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library device_models; library design; entity bench_aps6404l_controller is end entity bench_aps6404l_controller; architecture bench of bench_aps6404l_controller is signal rst : std_logic; signal clk : std_logic; signal psram_ce_n : std_logic; signal psram_sclk : std_logic; signal psram_sio : std_logic_vector(3 downto 0); signal addr : std_logic_vector(23 downto 0); signal data_in : std_logic_vector(7 downto 0); signal data_in_next : std_logic; signal write_en : std_logic; signal read_en : std_logic; signal data_out : std_logic_vector(7 downto 0); signal data_out_valid : std_logic; begin aps6404l_controller_inst : entity design.aps6404l_controller port map( clk => clk, rst => rst, addr => addr, data_in => data_in, data_in_next => data_in_next, data_out => data_out, data_out_valid => data_out_valid, write_en => write_en, read_en => read_en, psram_ce_n => psram_ce_n, psram_sclk => psram_sclk, psram_sio => psram_sio ); aps6404l_inst : entity device_models.aps6404l port map( ce_n => psram_ce_n, sclk => psram_sclk, sio => psram_sio ); clock_driver : process constant period : time := 20 ns; begin clk <= '0'; wait for period / 2; clk <= '1'; wait for period / 2; end process clock_driver; test : process is begin rst <= '1'; data_in <= (others => '0'); read_en <= '0'; write_en <= '0'; wait for 1 ns; rst <= '0'; wait for 3 us; wait until rising_edge(clk); addr <= x"ABCDEF"; read_en <= '1'; wait for 2 us; wait until rising_edge(clk); read_en <= '0'; wait for 1 us; wait until rising_edge(clk); addr <= x"ABCDEF"; write_en <= '1'; for i in 10 to 15 loop data_in <= std_logic_vector(to_unsigned(160 + i, 8)); loop wait until rising_edge(clk); exit when data_in_next = '1'; end loop; end loop; write_en <= '0'; wait until rising_edge(clk); write_en <= '1'; for i in 10 to 15 loop data_in <= std_logic_vector(to_unsigned(160 + i, 8)); loop wait until rising_edge(clk); exit when data_in_next = '1'; end loop; end loop; write_en <= '0'; wait; end process test; end architecture bench;