-- -------------------------------------------------------------------------- -- -- TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs -- -- -------------------------------------------------------------------------- -- -- TODO -- -------------------------------------------------------------------------- -- -- Author : Markus Koch -- Contributors : None -- License : Mozilla Public License (MPL) Version 2 -- -------------------------------------------------------------------------- -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library generics; use generics.wishbone_pkg.all; entity serv_top_vhdl is port( clk : in std_logic; -- CPU and bus clock clr : in std_logic; -- Synchronous clear (CPU reset) wbi_o : out wishbone_master_out; -- Instruction Wishbone bus (out) wbi_i : in wishbone_master_in; -- Instruction Wishbone bus (in) wbd_o : out wishbone_master_out; -- Data Wishbone bus (out) wbd_i : in wishbone_master_in; -- Data Wishbone bus (in) irq_timer : in std_logic -- System timer interrupt ); end entity serv_top_vhdl; architecture rtl of serv_top_vhdl is component serv_rf_top port( clk : in std_logic; i_rst : in std_logic; i_timer_irq : in std_logic; o_ibus_adr : out std_logic_vector(31 downto 0); o_ibus_cyc : out std_logic; i_ibus_rdt : in std_logic_vector(31 downto 0); i_ibus_ack : in std_logic; o_dbus_adr : out std_logic_vector(31 downto 0); o_dbus_dat : out std_logic_vector(31 downto 0); o_dbus_sel : out std_logic_vector(3 downto 0); o_dbus_we : out std_logic; o_dbus_cyc : out std_logic; i_dbus_rdt : in std_logic_vector(31 downto 0); i_dbus_ack : in std_logic; o_ext_rs1 : out std_logic_vector(31 downto 0); o_ext_rs2 : out std_logic_vector(31 downto 0); o_ext_funct3 : out std_logic_vector(2 downto 0); i_ext_rd : in std_logic_vector(31 downto 0); i_ext_ready : in std_logic; o_mdu_valid : out std_logic ); end component serv_rf_top; signal wbd_o_dat_bv : bit_vector(31 downto 0); begin serv_top : serv_rf_top port map( clk => clk, i_rst => clr, i_timer_irq => irq_timer, o_ibus_adr => wbi_o.adr, o_ibus_cyc => wbi_o.cyc, i_ibus_rdt => wbi_i.dat, i_ibus_ack => wbi_i.ack, o_dbus_adr => wbd_o.adr, o_dbus_dat => wbd_o.dat, o_dbus_sel => wbd_o.sel, o_dbus_we => wbd_o.we, o_dbus_cyc => wbd_o.cyc, i_dbus_rdt => wbd_i.dat, i_dbus_ack => wbd_i.ack, o_ext_rs1 => open, o_ext_rs2 => open, o_ext_funct3 => open, i_ext_rd => (others => '0'), i_ext_ready => '0', o_mdu_valid => open ); --wbd_o.dat <= to_std_logic_vector(wbd_o_dat_bv); wbi_o.stb <= wbi_o.cyc; wbi_o.sel <= (others => '1'); wbi_o.we <= '0'; wbi_o.dat <= (others => '0'); wbd_o.stb <= wbd_o.cyc; end architecture rtl;