26 lines
787 B
VHDL
26 lines
787 B
VHDL
-- -------------------------------------------------------------------------- --
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-- TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- TODO
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity pll0 is
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port(
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CLKI : in std_logic;
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CLKOP : out std_logic;
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LOCK : out std_logic);
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end pll0;
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architecture Structure of pll0 is
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begin
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CLKOP <= CLKI;
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LOCK <= '1';
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end Structure;
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