171 lines
		
	
	
		
			5.4 KiB
		
	
	
	
		
			VHDL
		
	
	
	
	
	
			
		
		
	
	
			171 lines
		
	
	
		
			5.4 KiB
		
	
	
	
		
			VHDL
		
	
	
	
	
	
-- -------------------------------------------------------------------------- --
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--              TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs              --
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-- -------------------------------------------------------------------------- --
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-- Wrapper for NEORV32
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-- -------------------------------------------------------------------------- --
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-- Author       : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License      : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library generics;
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use generics.wishbone_pkg.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_top_vhdl is
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	port(
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		clk       : in  std_logic;      -- CPU and bus clock
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		clr       : in  std_logic;      -- Synchronous clear (CPU reset)
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		wbi_o     : out wishbone_master_out; -- Instruction Wishbone bus (out)
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		wbi_i     : in  wishbone_master_in; -- Instruction Wishbone bus (in)
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		wbd_o     : out wishbone_master_out; -- Data Wishbone bus (out)
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		wbd_i     : in  wishbone_master_in; -- Data Wishbone bus (in)
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		irq_timer : in  std_logic       -- System timer interrupt
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	);
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end entity neorv32_top_vhdl;
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architecture rtl of neorv32_top_vhdl is
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	signal ibus_req_o : bus_req_t;
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	signal ibus_rsp_i : bus_rsp_t;
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	signal dbus_req_o : bus_req_t;
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	signal dbus_rsp_i : bus_rsp_t;
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	signal wbi_rsp_latched : std_logic;
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	signal wbd_rsp_latched : std_logic;
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	signal ibus_req_mask : std_logic;
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	signal ibus_rsp_mask : std_logic;
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	signal dbus_req_mask : std_logic;
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	signal dbus_rsp_mask : std_logic;
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begin
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	neorv32_cpu_inst : entity neorv32.neorv32_cpu
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		generic map(
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			HART_ID                    => x"00000000",
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			VENDOR_ID                  => x"00000000",
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			CPU_BOOT_ADDR              => x"00000000",
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			CPU_DEBUG_PARK_ADDR        => x"00000000",
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			CPU_DEBUG_EXC_ADDR         => x"00000000",
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			CPU_EXTENSION_RISCV_A      => false,
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			CPU_EXTENSION_RISCV_B      => false,
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			CPU_EXTENSION_RISCV_C      => false,
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			CPU_EXTENSION_RISCV_E      => false,
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			CPU_EXTENSION_RISCV_M      => false,
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			CPU_EXTENSION_RISCV_U      => false,
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			CPU_EXTENSION_RISCV_Zbkx   => false,
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			CPU_EXTENSION_RISCV_Zfinx  => false,
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			CPU_EXTENSION_RISCV_Zicntr => false,
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			CPU_EXTENSION_RISCV_Zicond => false,
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			CPU_EXTENSION_RISCV_Zihpm  => false,
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			CPU_EXTENSION_RISCV_Zknd   => false,
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			CPU_EXTENSION_RISCV_Zkne   => false,
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			CPU_EXTENSION_RISCV_Zknh   => false,
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			CPU_EXTENSION_RISCV_Zmmul  => false,
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			CPU_EXTENSION_RISCV_Zxcfu  => false,
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			CPU_EXTENSION_RISCV_Sdext  => false,
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			CPU_EXTENSION_RISCV_Sdtrig => false,
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			CPU_EXTENSION_RISCV_Smpmp  => false,
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			FAST_MUL_EN                => false,
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			FAST_SHIFT_EN              => false,
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			REGFILE_HW_RST             => true,
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			PMP_NUM_REGIONS            => 0,
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			PMP_MIN_GRANULARITY        => 0,
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			PMP_TOR_MODE_EN            => false,
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			PMP_NAP_MODE_EN            => false,
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			HPM_NUM_CNTS               => 0,
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			HPM_CNT_WIDTH              => 0
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		)
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		port map(
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			clk_i      => clk,
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			clk_aux_i  => clk,
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			rstn_i     => not clr,
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			sleep_o    => open,
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			debug_o    => open,
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			msi_i      => '0',
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			mei_i      => '0',
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			mti_i      => irq_timer,
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			firq_i     => x"0000",
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			dbi_i      => '0',
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			ibus_req_o => ibus_req_o,
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			ibus_rsp_i => ibus_rsp_i,
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			dbus_req_o => dbus_req_o,
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			dbus_rsp_i => dbus_rsp_i
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		);
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	-- Instruction bus
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	wbi_o.adr       <= wishbone_address(ibus_req_o.addr);
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	wbi_o.dat       <= wishbone_data(ibus_req_o.data);
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	wbi_o.sel       <= wishbone_byte_select(ibus_req_o.ben);
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	wbi_o.we        <= ibus_req_o.rw; -- TODO: We should also buffer this like we do stb, but in the current version the CPU holds it for us, so :shrug:
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	wbi_o.cyc       <= wbi_o.stb;
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	ibus_rsp_i.data <= std_ulogic_vector(wbi_i.dat);
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	wbi_o.stb      <= ibus_req_mask;
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	ibus_rsp_i.ack <= wbi_i.ack and not (ibus_rsp_mask);
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	ibus_rsp_i.err <= (wbi_i.err or wbi_i.rty) and not (ibus_rsp_mask);
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	wb2bus_i : process(clk) is
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	begin
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		if rising_edge(clk) then
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			if ibus_req_o.stb then
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				ibus_req_mask <= '1';
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				assert ibus_req_o.rvso = '0' report "Error: IBus RVSO not implemented but requested!" severity FAILURE;
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			end if;
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			if (wbi_i.ack or wbi_i.err or wbi_i.rty) and not ibus_req_o.stb then
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				ibus_req_mask <= '0';
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				ibus_rsp_mask <= '1';
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			else
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				ibus_rsp_mask <= '0';
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			end if;
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			if clr then
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				ibus_req_mask <= '0';
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				ibus_rsp_mask <= '0';
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			end if;
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		end if;
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	end process wb2bus_i;
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	-- Data bus
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	wbd_o.adr       <= wishbone_address(dbus_req_o.addr);
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	wbd_o.dat       <= wishbone_data(dbus_req_o.data);
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	wbd_o.sel       <= wishbone_byte_select(dbus_req_o.ben);
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	wbd_o.we        <= dbus_req_o.rw;
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	wbd_o.cyc       <= wbd_o.stb;
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	dbus_rsp_i.data <= std_ulogic_vector(wbd_i.dat);
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	wbd_o.stb      <= dbus_req_mask;
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	dbus_rsp_i.ack <= wbd_i.ack and not (dbus_rsp_mask);
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	dbus_rsp_i.err <= (wbd_i.err or wbd_i.rty) and not (dbus_rsp_mask);
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	wb2bus_d : process(clk) is
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	begin
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		if rising_edge(clk) then
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			if dbus_req_o.stb then
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				dbus_req_mask <= '1';
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				assert dbus_req_o.rvso = '0' report "Error: dbus RVSO not implemented but requested!" severity FAILURE;
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			end if;
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			if (wbd_i.ack or wbd_i.err or wbd_i.rty) and not dbus_req_o.stb then
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				dbus_req_mask <= '0';
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				dbus_rsp_mask <= '1';
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			else
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				dbus_rsp_mask <= '0';
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			end if;
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			if clr then
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				dbus_req_mask <= '0';
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				dbus_rsp_mask <= '0';
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			end if;
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		end if;
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	end process wb2bus_d;
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end architecture rtl;
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