Fix a variety of bugs found during integration
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28adf2340b
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01df956317
@ -281,7 +281,9 @@ int fpga_cell_bitstream_set_bit(char *buffer, char *sbuffer,
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int byteno;
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int byteno;
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int bitno;
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int bitno;
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bitno = bit % 8;
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bit = 47 - bit;
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bitno = 7 - (bit % 8);
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byteno = bit / 8;
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byteno = bit / 8;
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if ((sbuffer[byteno] & (1 << bitno))) { /* Already set */
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if ((sbuffer[byteno] & (1 << bitno))) { /* Already set */
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@ -316,7 +318,9 @@ int fpga_cell_bitstream_is_set(char *buffer, int bit)
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int byteno;
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int byteno;
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int bitno;
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int bitno;
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bitno = bit % 8;
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bit = 47 - bit;
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bitno = 7 - (bit % 8);
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byteno = bit / 8;
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byteno = bit / 8;
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return !!(buffer[byteno] & (1 << bitno));
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return !!(buffer[byteno] & (1 << bitno));
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@ -38,9 +38,9 @@ static int LUT_IN_BITMAP[4][3] = {
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/* LUT OUT MUX Definitions */
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/* LUT OUT MUX Definitions */
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static int LUT_OUT_MUX[4][4] = {
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static int LUT_OUT_MUX[4][4] = {
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{LUT_OUT_C, LUT_OUT_A, LUT_OUT_B, LUT_OUT_B_ASYNC},
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{LUT_OUT_C, LUT_OUT_A, LUT_OUT_B, LUT_OUT_B_ASYNC},
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{LUT_OUT_C, LUT_OUT_B_ASYNC, LUT_OUT_B, LUT_OUT_A},
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{LUT_OUT_C, LUT_OUT_B_ASYNC, LUT_OUT_B, LUT_OUT_A},
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{LUT_OUT_C, LUT_OUT_A, LUT_OUT_B, LUT_OUT_B_ASYNC},
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{LUT_OUT_C, LUT_OUT_A, LUT_OUT_B, LUT_OUT_B_ASYNC},
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{LUT_OUT_C, LUT_OUT_B_ASYNC, LUT_OUT_B, LUT_OUT_A}
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{LUT_OUT_C, LUT_OUT_B_ASYNC, LUT_OUT_B, LUT_OUT_A}
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};
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};
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static int LUT_OUT_BITMAP[4][2] = {
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static int LUT_OUT_BITMAP[4][2] = {
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@ -55,8 +55,8 @@ static int LUT_OUT_EN_N_BITMAP[4] = {
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/* Routing Definitions */
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/* Routing Definitions */
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static int ROUTE_BITMAP[8] = {
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static int ROUTE_BITMAP[8] = {
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5, 1, 2, 0,
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3, 6, 4, 0, /* Left */
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3, 6, 4, 7
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5, 1, 2, 7, /* Top */
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};
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};
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/* LED Definitions */
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/* LED Definitions */
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@ -224,9 +224,9 @@ char *fpga_cell_lut34_isp_generate_bitstream(struct fpga_cell *cell)
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}
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}
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for (i = 0; i < 4; ++i) {
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for (i = 0; i < 4; ++i) {
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temp = fpga_cell_bitstream_is_set(sbuf, LUT_OUT_BITMAP[i][0]); /* At some point, we set a specific output on this MUX */
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temp = fpga_cell_bitstream_is_set(sbuf, LUT_OUT_BITMAP[i][0]); /* At some point, we set a specific output on this MUX */
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BS_SET_BIT(LUT_OUT_EN_N_BITMAP[i], 1,
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BS_SET_BIT(LUT_OUT_EN_N_BITMAP[i], !temp,
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"Couldn't %s output for output %d.",
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"Couldn't %s output for output %d.",
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(temp ? "enable" : "disabled"), i);
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(!temp ? "enable" : "disabled"), i);
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if (!temp) {
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if (!temp) {
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BS_SET_BITS(0, 2 , LUT_OUT_BITMAP[i],
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BS_SET_BITS(0, 2 , LUT_OUT_BITMAP[i],
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"Couldn't set LUT output sel 0 for output %d (undriven by user logic).", i);
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"Couldn't set LUT output sel 0 for output %d (undriven by user logic).", i);
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@ -248,7 +248,7 @@ char *fpga_cell_lut34_isp_generate_bitstream(struct fpga_cell *cell)
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}
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}
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for (i = 0; i < 2; ++i) {
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for (i = 0; i < 2; ++i) {
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if (lut34->LUT3[i] > -1) {
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if (lut34->LUT3[i] > -1) {
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BS_SET_BITS(lut34->LUT3[i], 16, LUT3_BITMAP[i],
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BS_SET_BITS(lut34->LUT3[i], 8, LUT3_BITMAP[i],
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"Error setting LUT3[%d] data. Did you configure a LUT4 before?",
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"Error setting LUT3[%d] data. Did you configure a LUT4 before?",
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i);
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i);
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BS_SET_BIT(BIT_LUT_SPLIT_N, 0, "Couldn't set LUT3-2 mode. Did you configure a LUT4 before?");
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BS_SET_BIT(BIT_LUT_SPLIT_N, 0, "Couldn't set LUT3-2 mode. Did you configure a LUT4 before?");
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@ -22,7 +22,7 @@ int development_test_main(int argc, char *argv[])
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set_log_level(LL_DEBUG);
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set_log_level(LL_DEBUG);
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while((opt = getopt(argc, argv, "f:i:o:a")) != -1)
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while((opt = getopt(argc, argv, "f:i:o:h")) != -1)
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{
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{
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switch(opt)
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switch(opt)
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{
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{
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@ -47,7 +47,7 @@ int development_test_main(int argc, char *argv[])
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" -f\tFDEF FPGA description file, default fdef/4x4.fdef\n"
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" -f\tFDEF FPGA description file, default fdef/4x4.fdef\n"
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" -i\tKousaten input file, default stdin\n"
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" -i\tKousaten input file, default stdin\n"
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" -o\tOutput file, default stdout\n"
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" -o\tOutput file, default stdout\n"
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" -a\tGenerate output as ASCII HEX\n",
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" -h\tGenerate output as ASCII HEX\n",
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argv[0]);
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argv[0]);
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return 0;
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return 0;
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default:
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default:
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