electronics/ttl-fpga
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Fix a variety of bugs found during integration

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This commit is contained in:
Markus Koch 2019-06-22 17:24:09 +02:00
parent 28adf2340b
commit 01df956317
3 changed files with 15 additions and 11 deletions
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8
sw/kousaten/src/fpga_cell.c
View File

@ -281,7 +281,9 @@ int fpga_cell_bitstream_set_bit(char *buffer, char *sbuffer,
int byteno;
int bitno;
bitno = bit % 8;
bit = 47 - bit;
bitno = 7 - (bit % 8);
byteno = bit / 8;
if ((sbuffer[byteno] & (1 << bitno))) { /* Already set */
@ -316,7 +318,9 @@ int fpga_cell_bitstream_is_set(char *buffer, int bit)
int byteno;
int bitno;
bitno = bit % 8;
bit = 47 - bit;
bitno = 7 - (bit % 8);
byteno = bit / 8;
return !!(buffer[byteno] & (1 << bitno));

14
sw/kousaten/src/fpga_cell_lut34.c
View File

@ -38,9 +38,9 @@ static int LUT_IN_BITMAP[4][3] = {
/* LUT OUT MUX Definitions */
static int LUT_OUT_MUX[4][4] = {
{LUT_OUT_C, LUT_OUT_A, LUT_OUT_B, LUT_OUT_B_ASYNC},
{LUT_OUT_C, LUT_OUT_A, LUT_OUT_B, LUT_OUT_B_ASYNC},
{LUT_OUT_C, LUT_OUT_B_ASYNC, LUT_OUT_B, LUT_OUT_A},
{LUT_OUT_C, LUT_OUT_A, LUT_OUT_B, LUT_OUT_B_ASYNC},
{LUT_OUT_C, LUT_OUT_A, LUT_OUT_B, LUT_OUT_B_ASYNC},
{LUT_OUT_C, LUT_OUT_B_ASYNC, LUT_OUT_B, LUT_OUT_A}
};
static int LUT_OUT_BITMAP[4][2] = {
@ -55,8 +55,8 @@ static int LUT_OUT_EN_N_BITMAP[4] = {
/* Routing Definitions */
static int ROUTE_BITMAP[8] = {
5, 1, 2, 0,
3, 6, 4, 7
3, 6, 4, 0, /* Left */
5, 1, 2, 7, /* Top */
};
/* LED Definitions */
@ -224,9 +224,9 @@ char *fpga_cell_lut34_isp_generate_bitstream(struct fpga_cell *cell)
}
for (i = 0; i < 4; ++i) {
temp = fpga_cell_bitstream_is_set(sbuf, LUT_OUT_BITMAP[i][0]); /* At some point, we set a specific output on this MUX */
BS_SET_BIT(LUT_OUT_EN_N_BITMAP[i], 1,
BS_SET_BIT(LUT_OUT_EN_N_BITMAP[i], !temp,
"Couldn't %s output for output %d.",
(temp ? "enable" : "disabled"), i);
(!temp ? "enable" : "disabled"), i);
if (!temp) {
BS_SET_BITS(0, 2 , LUT_OUT_BITMAP[i],
"Couldn't set LUT output sel 0 for output %d (undriven by user logic).", i);
@ -248,7 +248,7 @@ char *fpga_cell_lut34_isp_generate_bitstream(struct fpga_cell *cell)
}
for (i = 0; i < 2; ++i) {
if (lut34->LUT3[i] > -1) {
BS_SET_BITS(lut34->LUT3[i], 16, LUT3_BITMAP[i],
BS_SET_BITS(lut34->LUT3[i], 8, LUT3_BITMAP[i],
"Error setting LUT3[%d] data. Did you configure a LUT4 before?",
i);
BS_SET_BIT(BIT_LUT_SPLIT_N, 0, "Couldn't set LUT3-2 mode. Did you configure a LUT4 before?");

4
sw/kousaten/src/main.c
View File

@ -22,7 +22,7 @@ int development_test_main(int argc, char *argv[])
set_log_level(LL_DEBUG);
while((opt = getopt(argc, argv, "f:i:o:a")) != -1)
while((opt = getopt(argc, argv, "f:i:o:h")) != -1)
{
switch(opt)
{
@ -47,7 +47,7 @@ int development_test_main(int argc, char *argv[])
" -f\tFDEF FPGA description file, default fdef/4x4.fdef\n"
" -i\tKousaten input file, default stdin\n"
" -o\tOutput file, default stdout\n"
" -a\tGenerate output as ASCII HEX\n",
" -h\tGenerate output as ASCII HEX\n",
argv[0]);
return 0;
default: