electronics/ttl-fpga
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Add test configuration for 2-bit counter

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This commit is contained in:
Markus Koch 2019-06-22 17:24:37 +02:00
parent 6846aff71d
commit 15fe4e4ca3
1 changed files with 16 additions and 3 deletions
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19
sw/kousaten/src/main.c
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@ -6,6 +6,8 @@
#include "unistd.h" #include "unistd.h"
#include "string.h" #include "string.h"
#include "fpga_cell_lut34.h" /* For testing purposes only */
#define E_FDEF 1 #define E_FDEF 1
#define E_BITSTREAM 2 #define E_BITSTREAM 2
@ -70,9 +72,20 @@ int development_test_main(int argc, char *argv[])
report(LL_INFO, "Chain loaded."); report(LL_INFO, "Chain loaded.");
/* TODO: Configure application specific logic */ /* TODO: Configure application specific logic */
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->lut_in_sel[0] = 'A'; ((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->lut_in_sel[0] = LUT_NET_F0;
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->drive_sel[0] = 'C'; ((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->lut_in_sel[1] = LUT_NET_F2;
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->LUT4 = 0x0F; ((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->lut_in_sel[2] = LUT_NET_L2;
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->lut_in_sel[3] = LUT_NET_L3;
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->sync = 0;
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->drive_sel[0] = 'A';
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->drive_sel[1] = 'Z';
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->drive_sel[2] = 'B';
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->drive_sel[3] = 'Z';
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->route_en = (1 << ROUTE_T0) | (1 << ROUTE_T1) | (1 << ROUTE_T2) | (1 << ROUTE_T3);
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->LUT3[0] = 0b01100110;
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->LUT3[1] = 0b01010101;
if (fpga_generate_bitstream(chain, bitstream_filename, bitstream_ascii)) { if (fpga_generate_bitstream(chain, bitstream_filename, bitstream_ascii)) {
report(LL_ERROR, "Bitstream generation failed."); report(LL_ERROR, "Bitstream generation failed.");