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sw: Add 16-bit counter demo

sw
Markus Koch 2 years ago
parent
commit
30e18b4357
  1. 58
      sw/kousaten/src/main.c

58
sw/kousaten/src/main.c

@ -11,6 +11,48 @@
#define E_FDEF 1
#define E_BITSTREAM 2
static void test_design_cell_ripple(struct fpga_cell_lut34 *cell, int first, int last)
{
cell->lut_in_sel[0] = LUT_NET_F0; // Own state
cell->lut_in_sel[1] = LUT_NET_F2; // Feedback &-net -- just for fun
cell->lut_in_sel[2] = (first ? LUT_NET_T2 : LUT_NET_L1); // &-state of previous stages
cell->lut_in_sel[3] = LUT_NET_L0; // Previous state -- just for fun
cell->sync = 1;
cell->drive_sel[0] = 'A';
cell->drive_sel[1] = 'b';
cell->drive_sel[2] = (last ? 'b' : 'Z');
cell->drive_sel[3] = 'Z';
cell->route_en = (1 << ROUTE_L2);
cell->LUT3[0] = 0b01011010;
cell->LUT3[1] = 0b10100000;
}
// WARNING: Requires a >=4x4 FPGA FDEF!
static void test_design_counter(struct fpga_cell *entry_cell)
{
struct fpga_cell_lut34 *cell;
int i, j;
for (i = 0; i < 4; ++i) {
cell = ((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]));
for (j = 4 - i; j < 4; ++j) {
cell = (struct fpga_cell_lut34 *)cell->base_cell.cell_connections[BOTTOM];
}
test_design_cell_ripple(cell, 1, 0);
cell = (struct fpga_cell_lut34 *)cell->base_cell.cell_connections[RIGHT];
test_design_cell_ripple(cell, 0, 0);
cell = (struct fpga_cell_lut34 *)cell->base_cell.cell_connections[RIGHT];
test_design_cell_ripple(cell, 0, 0);
cell = (struct fpga_cell_lut34 *)cell->base_cell.cell_connections[RIGHT];
test_design_cell_ripple(cell, 0, 1);
}
}
int development_test_main(int argc, char *argv[])
{
struct fpga_cell *entry_cell;
@ -71,21 +113,7 @@ int development_test_main(int argc, char *argv[])
}
report(LL_INFO, "Chain loaded.");
/* TODO: Configure application specific logic */
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->lut_in_sel[0] = LUT_NET_F0;
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->lut_in_sel[1] = LUT_NET_F2;
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->lut_in_sel[2] = LUT_NET_L2;
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->lut_in_sel[3] = LUT_NET_L3;
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->sync = 1;
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->drive_sel[0] = 'A';
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->drive_sel[1] = 'Z';
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->drive_sel[2] = 'B';
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->drive_sel[3] = 'Z';
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->route_en = (1 << ROUTE_T0) | (1 << ROUTE_T1) | (1 << ROUTE_T2) | (1 << ROUTE_T3);
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->LUT3[0] = 0b01100110;
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->LUT3[1] = 0b01010101;
test_design_counter(entry_cell);
if (fpga_generate_bitstream(chain, bitstream_filename, bitstream_ascii)) {
report(LL_ERROR, "Bitstream generation failed.");

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